92643 lines
7.2 MiB
92643 lines
7.2 MiB
; --------------------------------------------------------------------------------
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; @Title: E3 On-Chip Peripherals
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; @Props: Released
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; @Author: -
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; @Changelog: 2024-02-27 KRZ
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; @Manufacturer: SemiDrive
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; @Doc: E3_SSDK_PTG3.0_Source_Code
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; @Core: Cortex-R5F, CortexR5MPCore
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; @Chip: E3*
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pere3.per 17811 2024-04-23 14:07:55Z kwisniewski $
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config 16. 8.
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sif (CORENAME()=="CORTEXR5F")
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tree "Core Registers (Cortex-R5F)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup.long c15:0x00++0x00
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line.long 0x00 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x100++0x00
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line.long 0x00 "CTR,Cache Type Register"
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bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup.long c15:0x400--0x400
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line.long 0x0 "MPUIR,MPU type register"
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hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
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bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
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rgroup.long c15:0x500++0x00
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
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textline " "
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
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textline " "
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..."
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bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
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bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup.long c15:0x020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,DIvide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,ImmeDIate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,EnDIanness Control Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..."
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bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup.long c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup.long c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup.long c15:0x010++0x00
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb EncoDIng Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup.long c15:0x110++0x00
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line.long 0x00 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup.long c15:0x210++0x00
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line.long 0x00 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup.long c15:0x310++0x00
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line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long c15:0x02f++0x00
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line.long 0x00 "BO1R,Build Options 1 Register"
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hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM"
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bitfld.long 0x00 1. " FLOAT_PRECISION ,InDIcate whether double-precision floating point is implemented" "Not implemented,Implemented"
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textline " "
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bitfld.long 0x00 0. " PP_BUS_ECC ,InDIcate whether bus-ECC is implemented" "Not implemented,Implemented"
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group.long c15:0x12f++0x00
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line.long 0x00 "BO2R,Build Options 2 Register"
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bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2"
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bitfld.long 0x00 30. " LOCK_STEP ,InDIcate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
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textline " "
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bitfld.long 0x00 29. " NO_ICACHE ,InDIcate whether the CPU contains instruction cache" "Yes,No"
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bitfld.long 0x00 28. " NO_DCACHE ,InDIcate whether the CPU contains data cache" "Yes,No"
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textline " "
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bitfld.long 0x00 26.--27. " ATCM_ES ,InDIcate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
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bitfld.long 0x00 23.--25. " BTCM_ES ,InDIcate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
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textline " "
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bitfld.long 0x00 23. " NO_IE ,InDIcate whether the processor supports big-enDIan instructions" "Yes,No"
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bitfld.long 0x00 22. " NO_FPU ,InDIcate whether the CPU contains a floating point unit" "Yes,No"
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textline " "
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bitfld.long 0x00 20.--21. " MPU_REGIONS ,InDIcates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
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bitfld.long 0x00 17.--19. " BREAK_POINTS ,InDIcate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 14.--16. " WATCH_POINTS ,InDIcate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 13. " NO_A_TCM_INF ,InDIcate whether the CPUs contain ATCM ports" "Yes,No"
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textline " "
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bitfld.long 0x00 12. " NO_B0_TCM_INF ,InDIcate whether the CPUs contain B0TCM ports" "Yes,No"
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bitfld.long 0x00 11. " NO_B1_TCM_INF ,InDIcate whether the CPUs contain B1TCM ports" "Yes,No"
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textline " "
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bitfld.long 0x00 10. " TCMBUSPARITY ,InDIcate whether the processor contains TCM address bus parity logic" "No,Yes"
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bitfld.long 0x00 9. " NO_SLAVE ,InDIcate whether the CPU contains an AXI slave port" "Yes,No"
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textline " "
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bitfld.long 0x00 7.--8. " ICACHE_ES ,InDIcate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
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bitfld.long 0x00 5.--6. " DCACHE_ES ,InDIcate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
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textline " "
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bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,InDIcate whether the processor contains cache for corrected TCM errors" "Yes,No"
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bitfld.long 0x00 3. " AXI_BUS_ECC ,InDIcate whether the processor contains AXI bus ECC logic" "No,Yes"
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textline " "
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bitfld.long 0x00 2. " SL ,InDIcate whether the processor has been built with split/lock logic" "No,Yes"
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bitfld.long 0x00 1. " AHB_PP ,InDIcate whether the CPU contain AHB peripheral interfaces" "No,Yes"
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textline " "
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bitfld.long 0x00 0. " MICRO_SCU ,InDIcate whether the processor contain an ACP interface" "No,Yes"
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group.long c15:0x72f++0x00
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line.long 0x00 "POR,Pin Options Register"
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bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High"
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bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High"
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textline " "
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bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High"
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bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High"
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textline " "
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bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group.long c15:0x01++0x00
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line.long 0x00 "SCTLR,Control Register"
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bitfld.long 0x0 31. " IE ,Instruction enDIanness" "Little,Big"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "DIsable,Enable"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "DIsable,Enable"
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bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "DIsable,Enable"
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textline " "
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bitfld.long 0x0 25. " EE ,Exception enDIaness" "Little,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "DIsable,Vectored"
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bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "DIsable,Enable"
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textline " "
|
|
bitfld.long 0x0 19. " DZ ,DIvide by Zero exception bit" "DIsable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "DIsable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch PreDIction Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "DIsable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "DIsable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "DIsable,Enable"
|
|
textline " "
|
|
group.long c15:0x101++0x00
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " DICDI ,DIsable Case C dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 30. " DIB2DI ,DIsable Case B2 dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 29. " DIB1DI ,DIsable Case B1 dual issue control" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DIADI ,DIsable Case A dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "DIsable,Enable"
|
|
bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "DIsable,Enable"
|
|
bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "DIsable,Enable"
|
|
bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DILSM ,DIsable LIL on load/store multiples" "Enable,DIsable"
|
|
bitfld.long 0x00 21. " DEOLP ,DIsable end of loop preDIction" "Enable,DIsable"
|
|
bitfld.long 0x00 20. " DBHE ,DIsable BH extension" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FRCDIS ,Fetch rate control DIsable" "Enable,DIsable"
|
|
bitfld.long 0x00 17. " RSDIS ,Return stack DIsable" "Enable,DIsable"
|
|
bitfld.long 0x00 15.--16. " BP ,Control of the branch preDIction policy" "Normal,Taken,Not taken,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14. " DBWR ,DIsable write_burst on AXI master" "Enable,DIsable"
|
|
bitfld.long 0x00 13. " DLFO ,DIsable linefill optimization in the AXI master" "Enable,DIsable"
|
|
bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DNCH ,DIsable data forwarDIng for Non-cacheable accesses in the AXI master" "Enable,DIsable"
|
|
bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
|
|
bitfld.long 0x00 7. " SMOV ,sMOV DIsabled" "Enabled,DIsabled"
|
|
bitfld.long 0x0 6. " DILS ,DIsable low interrupt latency on all load/store instructions" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,DIsabled parity checking,Not generate abort,Not generate abort,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "DIsable,Enable"
|
|
bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "DIsable,Enable"
|
|
bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "DIsable,Enable"
|
|
textline " "
|
|
group.long c15:0x0f++0x00
|
|
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
|
|
bitfld.long 0x00 22. " DCHE ,DIsable hard-error support in the caches" "Enable,DIsable"
|
|
bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "DIsable,Enable"
|
|
bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,DIsable"
|
|
bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 9. " DZC ,Floating-point DIvide-by-zero exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,DIsable"
|
|
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "DIsable,Enable"
|
|
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "DIsable,Enable"
|
|
textline " "
|
|
group.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,DIsable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 30. " D32DIS ,DIsable use of D16-D31 of the VFP register file" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group.long c15:0x000b++0x00
|
|
line.long 0x00 "SPCR,Slave Port Control Register"
|
|
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
|
|
bitfld.long 0x00 0. " AXISLEN ,AXI slave port DIsable" "Enabled,DIsabled"
|
|
tree.end
|
|
width 0x8
|
|
tree "MPU Control and Configuration"
|
|
group.long c15:0x01++0x00
|
|
line.long 0x00 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction enDIanness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "DIsable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception enDIaness" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "DIsable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 19. " DZ ,DIvide by Zero exception bit" "DIsable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "DIsable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch PreDIction Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "DIsable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "DIsable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "DIsable,Enable"
|
|
textline " "
|
|
group.long c15:0x05++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x15++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability inDIcation" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x06++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability inDIcation" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0016++0x00
|
|
line.long 0x00 "RBAR,Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group.long c15:0x0216++0x00
|
|
line.long 0x00 "RSER,Region Size and Enable Register"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group.long c15:0x0416++0x00
|
|
line.long 0x00 "RACR,Region Access Control Register"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
group.long c15:0x0026++0x00
|
|
line.long 0x00 "MRNR,Memory Region Number Register"
|
|
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group.long c15:0x010d++0x00
|
|
line.long 0x00 "CIDR,Context ID Register"
|
|
group.long c15:0x20d++0x00
|
|
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
|
|
group.long c15:0x30d++0x00
|
|
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
|
|
group.long c15:0x40d++0x00
|
|
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
|
|
width 0x08
|
|
tree "MPU regions"
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RBAR0,Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RSER0,Region Size and Enable Register 0"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RACR0,Region Access Control Register 0"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RBAR1,Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RSER1,Region Size and Enable Register 1"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RACR1,Region Access Control Register 1"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RBAR2,Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RSER2,Region Size and Enable Register 2"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RACR2,Region Access Control Register 2"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RBAR3,Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RSER3,Region Size and Enable Register 3"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RACR3,Region Access Control Register 3"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RBAR4,Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RSER4,Region Size and Enable Register 4"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RACR4,Region Access Control Register 4"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RBAR5,Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RSER5,Region Size and Enable Register 5"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RACR5,Region Access Control Register 5"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RBAR6,Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RSER6,Region Size and Enable Register 6"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RACR6,Region Access Control Register 6"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RBAR7,Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RSER7,Region Size and Enable Register 7"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RACR7,Region Access Control Register 7"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RBAR8,Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RSER8,Region Size and Enable Register 8"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RACR8,Region Access Control Register 8"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RBAR9,Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RSER9,Region Size and Enable Register 9"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RACR9,Region Access Control Register 9"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RBAR10,Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RSER10,Region Size and Enable Register 10"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RACR10,Region Access Control Register 10"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RBAR11,Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RSER11,Region Size and Enable Register 11"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RACR11,Region Access Control Register 11"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RBAR12,Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RSER12,Region Size and Enable Register 12"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RACR12,Region Access Control Register 12"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RBAR13,Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RSER13,Region Size and Enable Register 13"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RACR13,Region Access Control Register 13"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RBAR14,Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RSER14,Region Size and Enable Register 14"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RACR14,Region Access Control Register 14"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RBAR15,Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RSER15,Region Size and Enable Register 15"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RACR15,Region Access Control Register 15"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "TCM Control and Configuration"
|
|
rgroup.long c15:0x200++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x019++0x00
|
|
line.long 0x00 "BTCMRR,BTCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "DIsabled,Enabled"
|
|
group.long c15:0x119++0x00
|
|
line.long 0x00 "ATCMRR,ATCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "DIsabled,Enabled"
|
|
rgroup.long c15:0x29++0x00
|
|
line.long 0x00 "TCMSEL,TCM Selection Register"
|
|
textline " "
|
|
group.long c15:0x10f++0x00
|
|
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "DIsabled,Enabled"
|
|
group.long c15:0x20f++0x00
|
|
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "DIsabled,Enabled"
|
|
group.long c15:0x30f++0x00
|
|
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "DIsabled,Enabled"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x00
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
|
|
rgroup.long c15:0x1700++0x00
|
|
line.long 0x00 "AIDR,Auxiliary ID Register"
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000++0x00
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction"
|
|
group.long c15:0x03f++0x00
|
|
line.long 0x00 "CFLR,Correctable Fault Location Register"
|
|
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
|
|
group.long c15:0x5f++0x00
|
|
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
group.long c15:0xef++0x00
|
|
line.long 0x00 "CSOR,Cache Size Override Register"
|
|
bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xc9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,DIsable PMCCNTR when prohibited" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export enable" "DIsabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock DIvider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Enable" "DIsabled,Enabled"
|
|
group.long c15:0x1c9++0x00
|
|
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / DIsable CCNT" "DIsabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
group.long c15:0x2c9++0x00
|
|
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / DIsable CCNT" "DIsabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
group.long c15:0x3c9++0x00
|
|
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group.long c15:0x4c9++0x00
|
|
line.long 0x0 "PMSWINC,Software Increment Register"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Event Count Register"
|
|
group.long c15:0x5c9++0x00
|
|
line.long 0x00 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
|
|
group.long c15:0xd9++0x00
|
|
line.long 0x00 "PMCCNTR,Cycle Count Register"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "ESR0,Event Selection Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "ESR1,Event Selection Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "ESR2,Event Selection Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0xe9++0x00
|
|
line.long 0x00 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
|
|
group.long c15:0x1e9++0x00
|
|
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
group.long c15:0x2e9++0x00
|
|
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
tree "Validation Registers"
|
|
group.long c15:0x01f++0x00
|
|
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x11f++0x00
|
|
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x21f++0x00
|
|
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x31f++0x00
|
|
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
group.long c15:0x41f++0x00
|
|
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x51f++0x00
|
|
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x61f++0x00
|
|
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x71f++0x00
|
|
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
tree.end
|
|
tree.end
|
|
width 11.
|
|
width 18.
|
|
tree "Debug Registers"
|
|
tree "Processor Identifier Registers"
|
|
rgroup.long c14:832.++0x00
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup.long c14:833.++0x00
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup.long c14:834.++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
group.long c14:835.++0x00
|
|
line.long 0x00 "AMIDR,Alias of MIDR"
|
|
rgroup.long c14:836.++0x00
|
|
line.long 0x00 "MPUTR,MPU Type Register"
|
|
rgroup.long c14:837.++0x00
|
|
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
|
|
group.long c14:838.++0x00
|
|
line.long 0x00 "AMIDR0,Alias of MIDR"
|
|
group.long c14:839.++0x00
|
|
line.long 0x00 "AMIDR1,Alias of MIDR"
|
|
rgroup.long c14:840.++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb EncoDIng Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:841.++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:842.++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup.long c14:843.++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long c14:844.++0x00
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:845.++0x00
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup.long c14:846.++0x00
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.long c14:847.++0x00
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:848.++0x00
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,DIvide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:849.++0x00
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,ImmeDIate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,EnDIanness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:850.++0x00
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:851.++0x00
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:852.++0x00
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:853.++0x00
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
width 15.
|
|
tree "Coresight Management Registers"
|
|
group.long c14:960.++0x00
|
|
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration"
|
|
group.long c14:1000.++0x00
|
|
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set"
|
|
group.long c14:1001.++0x00
|
|
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear"
|
|
wgroup.long c14:1004.++0x00
|
|
line.long 0x00 "DBGLAR,Lock Access Register"
|
|
rgroup.long c14:1005.++0x00
|
|
line.long 0x00 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " 32BA ,InDIcate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked"
|
|
rgroup.long c14:1006.++0x00
|
|
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "DIsabled,Enabled"
|
|
rgroup.long c14:1011.++0x00
|
|
line.long 0x00 "DBGDEVTYPE,Device Type Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
|
|
tree.end
|
|
textline " "
|
|
width 12.
|
|
rgroup.long c14:0.++0x0
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
|
|
textline " "
|
|
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
|
|
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High"
|
|
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts DIscarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug DIsable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug DIsable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "DIsabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "DIsabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel DIsable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt DIsable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "PenDIng,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
group.long c14:7.++0x0
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "DIsabled,Enabled"
|
|
bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "DIsabled,Enabled"
|
|
bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "DIsabled,Enabled"
|
|
bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "DIsabled,Enabled"
|
|
hgroup.long c14:32.++0x0
|
|
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group.long c14:35.++0x00
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
group.long c14:10.++0x0
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Write through DIsable" "No,Yes"
|
|
bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills DIsable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NDL ,L1 data cache line-fills DIsable" "No,Yes"
|
|
wgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
|
|
textline " "
|
|
rgroup.long c14:193.++0x0
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 1. " LOCK_IMP_BIT ,InDIcate whether the OS lock functionality is implemented" "Not implemented,Implemented"
|
|
group.long c14:196.++0x0
|
|
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
|
|
rgroup.long c14:197.++0x0
|
|
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset"
|
|
bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset"
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up"
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group.long c14:64.++0x0
|
|
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group.long c14:80.++0x0
|
|
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:65.++0x0
|
|
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group.long c14:81.++0x0
|
|
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:66.++0x0
|
|
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group.long c14:82.++0x0
|
|
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:67.++0x0
|
|
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group.long c14:83.++0x0
|
|
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:68.++0x0
|
|
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group.long c14:84.++0x0
|
|
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:69.++0x0
|
|
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group.long c14:85.++0x0
|
|
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:70.++0x0
|
|
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
|
|
group.long c14:86.++0x0
|
|
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:71.++0x0
|
|
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
|
|
group.long c14:87.++0x0
|
|
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:96.++0x0
|
|
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:112.++0x0
|
|
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:97.++0x0
|
|
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:113.++0x0
|
|
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:98.++0x0
|
|
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:114.++0x0
|
|
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:99.++0x0
|
|
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:115.++0x0
|
|
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:100.++0x0
|
|
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:116.++0x0
|
|
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:101.++0x0
|
|
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:117.++0x0
|
|
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:102.++0x0
|
|
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:118.++0x0
|
|
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:103.++0x0
|
|
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:119.++0x0
|
|
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:6.++0x0
|
|
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
|
|
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
elif (CORENAME()=="CORTEXR5MPCORE")
|
|
tree "Core Registers (Cortex-R5MPCore)"
|
|
width 0x8
|
|
; --------------------------------------------------------------------------------
|
|
; Identification registers
|
|
; --------------------------------------------------------------------------------
|
|
tree "ID Registers"
|
|
rgroup.long c15:0x00++0x00
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
|
|
textline " "
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
|
|
bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c15:0x100++0x00
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
|
|
bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
|
|
rgroup.long c15:0x400--0x400
|
|
line.long 0x0 "MPUIR,MPU type register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
|
|
bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
|
|
rgroup.long c15:0x500++0x00
|
|
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
|
|
bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
|
|
textline " "
|
|
rgroup.long c15:0x0410++0x00
|
|
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..."
|
|
bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.long c15:0x0510++0x00
|
|
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup.long c15:0x0610++0x00
|
|
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.long c15:0x0710++0x00
|
|
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
|
|
bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x020++0x00
|
|
line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,DIvide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x120++0x00
|
|
line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,ImmeDIate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,EnDIanness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x220++0x00
|
|
line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x320++0x00
|
|
line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x420++0x00
|
|
line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c15:0x0520++0x00
|
|
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
|
|
rgroup.long c15:0x0620++0x00
|
|
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
|
|
rgroup.long c15:0x0720++0x00
|
|
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
|
|
rgroup.long c15:0x010++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb EncoDIng Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x110++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
rgroup.long c15:0x210++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup.long c15:0x310++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long c15:0x02f++0x00
|
|
line.long 0x00 "BO1R,Build Options 1 Register"
|
|
hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM"
|
|
bitfld.long 0x00 1. " FLOAT_PRECISION ,InDIcate whether double-precision floating point is implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PP_BUS_ECC ,InDIcate whether bus-ECC is implemented" "Not implemented,Implemented"
|
|
group.long c15:0x12f++0x00
|
|
line.long 0x00 "BO2R,Build Options 2 Register"
|
|
bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2"
|
|
bitfld.long 0x00 30. " LOCK_STEP ,InDIcate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x00 29. " NO_ICACHE ,InDIcate whether the CPU contains instruction cache" "Yes,No"
|
|
bitfld.long 0x00 28. " NO_DCACHE ,InDIcate whether the CPU contains data cache" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " ATCM_ES ,InDIcate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
|
|
bitfld.long 0x00 23.--25. " BTCM_ES ,InDIcate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " NO_IE ,InDIcate whether the processor supports big-enDIan instructions" "Yes,No"
|
|
bitfld.long 0x00 22. " NO_FPU ,InDIcate whether the CPU contains a floating point unit" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MPU_REGIONS ,InDIcates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
|
|
bitfld.long 0x00 17.--19. " BREAK_POINTS ,InDIcate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--16. " WATCH_POINTS ,InDIcate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13. " NO_A_TCM_INF ,InDIcate whether the CPUs contain ATCM ports" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 12. " NO_B0_TCM_INF ,InDIcate whether the CPUs contain B0TCM ports" "Yes,No"
|
|
bitfld.long 0x00 11. " NO_B1_TCM_INF ,InDIcate whether the CPUs contain B1TCM ports" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TCMBUSPARITY ,InDIcate whether the processor contains TCM address bus parity logic" "No,Yes"
|
|
bitfld.long 0x00 9. " NO_SLAVE ,InDIcate whether the CPU contains an AXI slave port" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " ICACHE_ES ,InDIcate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
|
|
bitfld.long 0x00 5.--6. " DCACHE_ES ,InDIcate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,InDIcate whether the processor contains cache for corrected TCM errors" "Yes,No"
|
|
bitfld.long 0x00 3. " AXI_BUS_ECC ,InDIcate whether the processor contains AXI bus ECC logic" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SL ,InDIcate whether the processor has been built with split/lock logic" "No,Yes"
|
|
bitfld.long 0x00 1. " AHB_PP ,InDIcate whether the CPU contain AHB peripheral interfaces" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MICRO_SCU ,InDIcate whether the processor contain an ACP interface" "No,Yes"
|
|
group.long c15:0x72f++0x00
|
|
line.long 0x00 "POR,Pin Options Register"
|
|
bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High"
|
|
bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High"
|
|
bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High"
|
|
tree.end
|
|
width 0x8
|
|
tree "System Control and Configuration"
|
|
group.long c15:0x01++0x00
|
|
line.long 0x00 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction enDIanness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "DIsable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception enDIaness" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "DIsable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 19. " DZ ,DIvide by Zero exception bit" "DIsable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "DIsable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch PreDIction Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "DIsable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "DIsable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "DIsable,Enable"
|
|
textline " "
|
|
group.long c15:0x101++0x00
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " DICDI ,DIsable Case C dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 30. " DIB2DI ,DIsable Case B2 dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 29. " DIB1DI ,DIsable Case B1 dual issue control" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DIADI ,DIsable Case A dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "DIsable,Enable"
|
|
bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "DIsable,Enable"
|
|
bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "DIsable,Enable"
|
|
bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DILSM ,DIsable LIL on load/store multiples" "Enable,DIsable"
|
|
bitfld.long 0x00 21. " DEOLP ,DIsable end of loop preDIction" "Enable,DIsable"
|
|
bitfld.long 0x00 20. " DBHE ,DIsable BH extension" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FRCDIS ,Fetch rate control DIsable" "Enable,DIsable"
|
|
bitfld.long 0x00 17. " RSDIS ,Return stack DIsable" "Enable,DIsable"
|
|
bitfld.long 0x00 15.--16. " BP ,Control of the branch preDIction policy" "Normal,Taken,Not taken,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14. " DBWR ,DIsable write_burst on AXI master" "Enable,DIsable"
|
|
bitfld.long 0x00 13. " DLFO ,DIsable linefill optimization in the AXI master" "Enable,DIsable"
|
|
bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DNCH ,DIsable data forwarDIng for Non-cacheable accesses in the AXI master" "Enable,DIsable"
|
|
bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
|
|
bitfld.long 0x00 7. " SMOV ,sMOV DIsabled" "Enabled,DIsabled"
|
|
bitfld.long 0x0 6. " DILS ,DIsable low interrupt latency on all load/store instructions" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,DIsabled parity checking,Not generate abort,Not generate abort,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "DIsable,Enable"
|
|
bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "DIsable,Enable"
|
|
bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "DIsable,Enable"
|
|
textline " "
|
|
group.long c15:0x0f++0x00
|
|
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
|
|
bitfld.long 0x00 22. " DCHE ,DIsable hard-error support in the caches" "Enable,DIsable"
|
|
bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "DIsable,Enable"
|
|
bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,DIsable"
|
|
bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,DIsable"
|
|
bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 9. " DZC ,Floating-point DIvide-by-zero exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,DIsable"
|
|
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,DIsable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "DIsable,Enable"
|
|
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "DIsable,Enable"
|
|
textline " "
|
|
group.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,DIsable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 30. " D32DIS ,DIsable use of D16-D31 of the VFP register file" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group.long c15:0x000b++0x00
|
|
line.long 0x00 "SPCR,Slave Port Control Register"
|
|
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
|
|
bitfld.long 0x00 0. " AXISLEN ,AXI slave port DIsable" "Enabled,DIsabled"
|
|
tree.end
|
|
width 0x8
|
|
tree "MPU Control and Configuration"
|
|
group.long c15:0x01++0x00
|
|
line.long 0x00 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction enDIanness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "DIsable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception enDIaness" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "DIsable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "DIsable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 19. " DZ ,DIvide by Zero exception bit" "DIsable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "DIsable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch PreDIction Enable" "DIsable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "DIsable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "DIsable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "DIsable,Enable"
|
|
textline " "
|
|
group.long c15:0x05++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x15++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability inDIcation" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x06++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability inDIcation" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0016++0x00
|
|
line.long 0x00 "RBAR,Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group.long c15:0x0216++0x00
|
|
line.long 0x00 "RSER,Region Size and Enable Register"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group.long c15:0x0416++0x00
|
|
line.long 0x00 "RACR,Region Access Control Register"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
group.long c15:0x0026++0x00
|
|
line.long 0x00 "MRNR,Memory Region Number Register"
|
|
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group.long c15:0x010d++0x00
|
|
line.long 0x00 "CIDR,Context ID Register"
|
|
group.long c15:0x20d++0x00
|
|
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
|
|
group.long c15:0x30d++0x00
|
|
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
|
|
group.long c15:0x40d++0x00
|
|
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
|
|
width 0x08
|
|
tree "MPU regions"
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RBAR0,Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RSER0,Region Size and Enable Register 0"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RACR0,Region Access Control Register 0"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RBAR1,Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RSER1,Region Size and Enable Register 1"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RACR1,Region Access Control Register 1"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RBAR2,Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RSER2,Region Size and Enable Register 2"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RACR2,Region Access Control Register 2"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RBAR3,Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RSER3,Region Size and Enable Register 3"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RACR3,Region Access Control Register 3"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RBAR4,Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RSER4,Region Size and Enable Register 4"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RACR4,Region Access Control Register 4"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RBAR5,Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RSER5,Region Size and Enable Register 5"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RACR5,Region Access Control Register 5"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RBAR6,Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RSER6,Region Size and Enable Register 6"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RACR6,Region Access Control Register 6"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RBAR7,Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RSER7,Region Size and Enable Register 7"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RACR7,Region Access Control Register 7"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RBAR8,Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RSER8,Region Size and Enable Register 8"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RACR8,Region Access Control Register 8"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RBAR9,Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RSER9,Region Size and Enable Register 9"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RACR9,Region Access Control Register 9"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RBAR10,Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RSER10,Region Size and Enable Register 10"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RACR10,Region Access Control Register 10"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RBAR11,Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RSER11,Region Size and Enable Register 11"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RACR11,Region Access Control Register 11"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RBAR12,Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RSER12,Region Size and Enable Register 12"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RACR12,Region Access Control Register 12"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RBAR13,Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RSER13,Region Size and Enable Register 13"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RACR13,Region Access Control Register 13"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RBAR14,Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RSER14,Region Size and Enable Register 14"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RACR14,Region Access Control Register 14"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RBAR15,Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RSER15,Region Size and Enable Register 15"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 DIsable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 DIsable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 DIsable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 DIsable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 DIsable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 DIsable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 DIsable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 DIsable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "UnpreDIctable,UnpreDIctable,UnpreDIctable,UnpreDIctable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "DIsabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RACR15,Region Access Control Register 15"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "TCM Control and Configuration"
|
|
rgroup.long c15:0x200++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x019++0x00
|
|
line.long 0x00 "BTCMRR,BTCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "DIsabled,Enabled"
|
|
group.long c15:0x119++0x00
|
|
line.long 0x00 "ATCMRR,ATCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "DIsabled,Enabled"
|
|
rgroup.long c15:0x29++0x00
|
|
line.long 0x00 "TCMSEL,TCM Selection Register"
|
|
textline " "
|
|
group.long c15:0x10f++0x00
|
|
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "DIsabled,Enabled"
|
|
group.long c15:0x20f++0x00
|
|
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "DIsabled,Enabled"
|
|
group.long c15:0x30f++0x00
|
|
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "DIsabled,Enabled"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x00
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
|
|
rgroup.long c15:0x1700++0x00
|
|
line.long 0x00 "AIDR,Auxiliary ID Register"
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000++0x00
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction"
|
|
group.long c15:0x03f++0x00
|
|
line.long 0x00 "CFLR,Correctable Fault Location Register"
|
|
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
|
|
group.long c15:0x5f++0x00
|
|
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
group.long c15:0xef++0x00
|
|
line.long 0x00 "CSOR,Cache Size Override Register"
|
|
bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xc9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,DIsable PMCCNTR when prohibited" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export enable" "DIsabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock DIvider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Enable" "DIsabled,Enabled"
|
|
group.long c15:0x1c9++0x00
|
|
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / DIsable CCNT" "DIsabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
group.long c15:0x2c9++0x00
|
|
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / DIsable CCNT" "DIsabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / DIsable counter" "DIsabled,Enabled"
|
|
group.long c15:0x3c9++0x00
|
|
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group.long c15:0x4c9++0x00
|
|
line.long 0x0 "PMSWINC,Software Increment Register"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Event Count Register"
|
|
group.long c15:0x5c9++0x00
|
|
line.long 0x00 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
|
|
group.long c15:0xd9++0x00
|
|
line.long 0x00 "PMCCNTR,Cycle Count Register"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "ESR0,Event Selection Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "ESR1,Event Selection Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "ESR2,Event Selection Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0xe9++0x00
|
|
line.long 0x00 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
|
|
group.long c15:0x1e9++0x00
|
|
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
group.long c15:0x2e9++0x00
|
|
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / DIsable Interrupt" "DIsabled,Enabled"
|
|
tree "Validation Registers"
|
|
group.long c15:0x01f++0x00
|
|
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x11f++0x00
|
|
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x21f++0x00
|
|
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x31f++0x00
|
|
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
group.long c15:0x41f++0x00
|
|
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x51f++0x00
|
|
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x61f++0x00
|
|
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x71f++0x00
|
|
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
tree.end
|
|
tree.end
|
|
width 11.
|
|
width 18.
|
|
tree "Debug Registers"
|
|
tree "Processor Identifier Registers"
|
|
rgroup.long c14:832.++0x00
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup.long c14:833.++0x00
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup.long c14:834.++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
group.long c14:835.++0x00
|
|
line.long 0x00 "AMIDR,Alias of MIDR"
|
|
rgroup.long c14:836.++0x00
|
|
line.long 0x00 "MPUTR,MPU Type Register"
|
|
rgroup.long c14:837.++0x00
|
|
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
|
|
group.long c14:838.++0x00
|
|
line.long 0x00 "AMIDR0,Alias of MIDR"
|
|
group.long c14:839.++0x00
|
|
line.long 0x00 "AMIDR1,Alias of MIDR"
|
|
rgroup.long c14:840.++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb EncoDIng Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:841.++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:842.++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup.long c14:843.++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long c14:844.++0x00
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:845.++0x00
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup.long c14:846.++0x00
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.long c14:847.++0x00
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:848.++0x00
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,DIvide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:849.++0x00
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,ImmeDIate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,EnDIanness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:850.++0x00
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:851.++0x00
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:852.++0x00
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:853.++0x00
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
width 15.
|
|
tree "Coresight Management Registers"
|
|
group.long c14:960.++0x00
|
|
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration"
|
|
group.long c14:1000.++0x00
|
|
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set"
|
|
group.long c14:1001.++0x00
|
|
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear"
|
|
wgroup.long c14:1004.++0x00
|
|
line.long 0x00 "DBGLAR,Lock Access Register"
|
|
rgroup.long c14:1005.++0x00
|
|
line.long 0x00 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " 32BA ,InDIcate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked"
|
|
rgroup.long c14:1006.++0x00
|
|
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "DIsabled,Enabled"
|
|
rgroup.long c14:1011.++0x00
|
|
line.long 0x00 "DBGDEVTYPE,Device Type Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
|
|
tree.end
|
|
textline " "
|
|
width 12.
|
|
rgroup.long c14:0.++0x0
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
|
|
textline " "
|
|
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
|
|
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High"
|
|
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts DIscarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug DIsable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug DIsable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "DIsabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "DIsabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel DIsable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt DIsable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "PenDIng,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
group.long c14:7.++0x0
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "DIsabled,Enabled"
|
|
bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "DIsabled,Enabled"
|
|
bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "DIsabled,Enabled"
|
|
bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "DIsabled,Enabled"
|
|
hgroup.long c14:32.++0x0
|
|
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group.long c14:35.++0x00
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
group.long c14:10.++0x0
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Write through DIsable" "No,Yes"
|
|
bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills DIsable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NDL ,L1 data cache line-fills DIsable" "No,Yes"
|
|
wgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
|
|
textline " "
|
|
rgroup.long c14:193.++0x0
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 1. " LOCK_IMP_BIT ,InDIcate whether the OS lock functionality is implemented" "Not implemented,Implemented"
|
|
group.long c14:196.++0x0
|
|
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
|
|
rgroup.long c14:197.++0x0
|
|
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset"
|
|
bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset"
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up"
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group.long c14:64.++0x0
|
|
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group.long c14:80.++0x0
|
|
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:65.++0x0
|
|
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group.long c14:81.++0x0
|
|
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:66.++0x0
|
|
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group.long c14:82.++0x0
|
|
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:67.++0x0
|
|
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group.long c14:83.++0x0
|
|
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:68.++0x0
|
|
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group.long c14:84.++0x0
|
|
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:69.++0x0
|
|
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group.long c14:85.++0x0
|
|
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:70.++0x0
|
|
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
|
|
group.long c14:86.++0x0
|
|
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
group.long c14:71.++0x0
|
|
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
|
|
group.long c14:87.++0x0
|
|
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "DIsabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:96.++0x0
|
|
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:112.++0x0
|
|
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:97.++0x0
|
|
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:113.++0x0
|
|
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:98.++0x0
|
|
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:114.++0x0
|
|
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:99.++0x0
|
|
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:115.++0x0
|
|
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:100.++0x0
|
|
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:116.++0x0
|
|
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:101.++0x0
|
|
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:117.++0x0
|
|
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:102.++0x0
|
|
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:118.++0x0
|
|
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:103.++0x0
|
|
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:119.++0x0
|
|
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "DIsabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "DIsabled,Enabled"
|
|
group.long c14:6.++0x0
|
|
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
|
|
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
enDIf
|
|
tree "ADC"
|
|
tree "ADC1"
|
|
width 28.
|
|
group ad:0xF0F70000++0x03
|
|
line.long 0x00 "SADC_SOFT_RST,SADC soft reset"
|
|
bitfld.long 0x00 5. " RC3_TMR_RST ,rc3 timer soft reset" "0,1"
|
|
bitfld.long 0x00 4. " RC2_TMR_RST ,rc2 timer soft reset" "0,1"
|
|
bitfld.long 0x00 3. " RC1_TMR_RST ,rc1 timer soft reset" "0,1"
|
|
bitfld.long 0x00 2. " RC0_TMR_RST ,rc0 timer soft reset" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "ANA_RST ,analog soft reset default reset analog macro, need software change to 1 when start to work" "0,1"
|
|
bitfld.long 0x00 0. " DIG_RST ,DIgital soft reset" "0,1"
|
|
group ad:0xF0F70004++0x03
|
|
line.long 0x00 "SADC_INIT,SADC init configuration"
|
|
bitfld.long 0x00 24. " DONE ,sadc initial done status" "0,1"
|
|
bitfld.long 0x00 20. " START ,sadc initial start reg. auto clear" "0,1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,sadc initial start value"
|
|
group ad:0xF0F70008++0x03
|
|
line.long 0x00 "SADC_DCOC,SADC dcoc configuration"
|
|
bitfld.long 0x00 31. " DONE ,dcoc done signal" "0,1"
|
|
hexmask.long.word 0x00 16.--28. 1. " VALUE ,bit28: sign bit. bit27~16 : dc offset value"
|
|
bitfld.long 0x00 8. " SOFT_OVWR_EN ,software overwrite dc offset value. auto clear" "0,1"
|
|
bitfld.long 0x00 4. " EN ,1: the ADC result will minus dcoc result. 0: use default value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "START ,1:start to calculate dcoc. auto clear after calculation done" "0,1"
|
|
bitfld.long 0x00 0.--2. " TIMES ,dcoc average calculation times. 0: 1 1: 2 2: 4 3: 8 4:16 5:32 6:64 7:128" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F7000C++0x03
|
|
line.long 0x00 "SADC_HTC,SADC htc register"
|
|
bitfld.long 0x00 31. " READY ,when init or dcoc, SADC can not accept hardware trigger outside. Software read init done and dcoc done, config this reg to 1" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " READY_LEN ,for scheduler sync mode, htc ready length when next slot is RCHT"
|
|
bitfld.long 0x00 0.--3. " DONE_LEN ,htc done length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F70010++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_0,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70014++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_1,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70018++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_2,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F7001C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_3,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70020++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_4,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70024++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_5,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70028++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_6,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F7002C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_7,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70030++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_8,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70034++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_9,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70038++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_10,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F7003C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_11,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70040++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_12,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70044++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_13,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70048++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_14,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F7004C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_15,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70050++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_16,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70054++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_17,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70058++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_18,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F7005C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_19,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70060++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_20,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70064++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_21,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70068++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_22,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F7006C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_23,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70070++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_24,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70074++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_25,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70078++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_26,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F7007C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_27,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70080++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_28,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70084++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_29,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70088++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_30,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F7008C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_31,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F70090++0x03
|
|
line.long 0x00 "SADC_RC0_TIMER,RC0 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER compare value"
|
|
group ad:0xF0F70094++0x03
|
|
line.long 0x00 "SADC_RC1_TIMER,RC1 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER compare value"
|
|
group ad:0xF0F70098++0x03
|
|
line.long 0x00 "SADC_RC2_TIMER,RC2 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER compare value"
|
|
group ad:0xF0F7009C++0x03
|
|
line.long 0x00 "SADC_RC3_TIMER,RC3 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER counter value"
|
|
group ad:0xF0F700A0++0x03
|
|
line.long 0x00 "SADC_RC0,SADC RC0 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F700A4++0x03
|
|
line.long 0x00 "SADC_RC1,SADC RC1 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F700A8++0x03
|
|
line.long 0x00 "SADC_RC2,SADC RC2 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F700AC++0x03
|
|
line.long 0x00 "SADC_RC3,SADC RC3 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear." "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F700B0++0x03
|
|
line.long 0x00 "SADC_INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 24. " MNT_EVT_CONT ,continuous monitor event" "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 12. " TS_OVF ,Scheduler time stamp overflow" "0,1"
|
|
bitfld.long 0x00 11. " WATER_MARK_SUB_3 ,SUB-FIFO3 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 10. " WATER_MARK_SUB_2 ,SUB-FIFO2 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "WATER_MARK_SUB_1 ,SUB-FIFO1 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 8. " WATER_MARK_SUB_0 ,SUB-FIFO0 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 4. " END_COV_RCHT ,rcht end of each conversion" "0,1"
|
|
bitfld.long 0x00 3. " END_COV_RC0 ,rc0 end of each conversion" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "END_COV_RC1 ,rc1 end of each conversion" "0,1"
|
|
bitfld.long 0x00 1. " END_COV_RC2 ,rc2 end of each conversion" "0,1"
|
|
bitfld.long 0x00 0. " END_COV_RC3 ,rc3 end of each conversion" "0,1"
|
|
group ad:0xF0F700B4++0x03
|
|
line.long 0x00 "SADC_INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 24. " MNT_EVT_CONT ,continuous monitor event" "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 12. " TS_OVF ,Scheduler time stamp overflow" "0,1"
|
|
bitfld.long 0x00 11. " WATER_MARK_SUB_3 ,SUB-FIFO3 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 10. " WATER_MARK_SUB_2 ,SUB-FIFO2 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "WATER_MARK_SUB_1 ,SUB-FIFO1 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 8. " WATER_MARK_SUB_0 ,SUB-FIFO0 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 4. " END_COV_RCHT ,rcht end of each conversion" "0,1"
|
|
bitfld.long 0x00 3. " END_COV_RC0 ,rc0 end of each conversion" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "END_COV_RC1 ,rc1 end of each conversion" "0,1"
|
|
bitfld.long 0x00 1. " END_COV_RC2 ,rc2 end of each conversion" "0,1"
|
|
bitfld.long 0x00 0. " END_COV_RC3 ,rc3 end of each conversion" "0,1"
|
|
group ad:0xF0F700B8++0x03
|
|
line.long 0x00 "SADC_INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 24. " MNT_EVT_CONT ,continuous monitor event" "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 12. " TS_OVF ,Scheduler time stamp overflow" "0,1"
|
|
bitfld.long 0x00 11. " WATER_MARK_SUB_3 ,SUB-FIFO3 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 10. " WATER_MARK_SUB_2 ,SUB-FIFO2 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "WATER_MARK_SUB_1 ,SUB-FIFO1 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 8. " WATER_MARK_SUB_0 ,SUB-FIFO0 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 4. " END_COV_RCHT ,rcht end of each conversion" "0,1"
|
|
bitfld.long 0x00 3. " END_COV_RC0 ,rc0 end of each conversion" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "END_COV_RC1 ,rc1 end of each conversion" "0,1"
|
|
bitfld.long 0x00 1. " END_COV_RC2 ,rc2 end of each conversion" "0,1"
|
|
bitfld.long 0x00 0. " END_COV_RC3 ,rc3 end of each conversion" "0,1"
|
|
group ad:0xF0F700C0++0x03
|
|
line.long 0x00 "SADC_COR_ERR_INT_STA,Correctable error interrupt status register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
group ad:0xF0F700C4++0x03
|
|
line.long 0x00 "SADC_COR_ERR_INT_STA_EN,Correctable error interrupt status enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
group ad:0xF0F700C8++0x03
|
|
line.long 0x00 "SADC_COR_ERR_INT_SIG_EN,Correctable error interrupt signal enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
group ad:0xF0F700D0++0x03
|
|
line.long 0x00 "SADC_UNC_ERR_INT_STA,Uncorrectable error interrupt status register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 0. " ANA_EXT_MUX_ERR ,analog external mux error" "0,1"
|
|
group ad:0xF0F700D4++0x03
|
|
line.long 0x00 "SADC_UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 0. " ANA_EXT_MUX_ERR ,analog external mux error" "0,1"
|
|
group ad:0xF0F700D8++0x03
|
|
line.long 0x00 "SADC_UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt signal enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 0. " ANA_EXT_MUX_ERR ,analog external mux error" "0,1"
|
|
group ad:0xF0F700E0++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 4.--6. " DMA1 ,Data error injection for DMA1 channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DMA0 ,Data error injection for DMA0 channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F700E4++0x03
|
|
line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 4.--7. " DMA1 ,Code error injection for DMA 1 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMA0 ,Code error injection for DMA 0 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F700E8++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 4.--7. " DMA1 ,Data error injection for DMA1 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMA0 ,Data error injection for DMA0 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F700EC++0x03
|
|
line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
|
bitfld.long 0x00 4.--7. " DMA1 ,Code error injection for DMA 1 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMA0 ,Code error injection for DMA 0 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F700F0++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 2. " UNC ,uncorrectable error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR ,correctable error injection" "0,1"
|
|
bitfld.long 0x00 0. " FUNC ,function error injection" "0,1"
|
|
group ad:0xF0F70100++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_0,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector [8:6] for analog mux sel. for DIff mode: [5:3] = p [2:0] = n, for single mode: [3]: 1 -> P/ 0 ->N [2:0] control channel"
|
|
group ad:0xF0F70104++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_1,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70108++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_2,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7010C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_3,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70110++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_4,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70114++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_5,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70118++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_6,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7011C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_7,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70120++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_8,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70124++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_9,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70128++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_10,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7012C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_11,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70130++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_12,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70134++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_13,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70138++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_14,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7013C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_15,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70140++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_0,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70144++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_1,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70148++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_2,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7014C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_3,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70150++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_4,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70154++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_5,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70158++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_6,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7015C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_7,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70160++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_8,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70164++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_9,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70168++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_10,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7016C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_11,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70170++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_12,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70174++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_13,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70178++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_14,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7017C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_15,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70180++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_0,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70184++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_1,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70188++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_2,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7018C++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_3,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70190++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_4,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70194++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_5,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70198++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_6,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F7019C++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_7,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701A0++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_8,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701A4++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_9,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701A8++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_10,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701AC++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_11,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701B0++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_12,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701B4++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_13,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701B8++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_14,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701BC++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_15,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701C0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_0,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701C4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_1,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701C8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_2,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701CC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_3,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701D0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_4,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701D4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_5,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701D8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_6,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701DC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_7,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701E0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_8,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701E4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_9,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701E8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_10,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701EC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_11,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701F0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_12,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701F4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_13,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701F8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_14,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F701FC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_15,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F70200++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART1,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_7 ,slot7 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_6 ,slot6 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_5 ,slot5 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_4 ,slot4 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_3 ,slot3 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_2 ,slot2 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_1 ,slot1 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_0 ,slot0 cid 3'h0: rc0 3'h1: rc1 3'h2: rc2 3'h3: rc3 3'h4: rcht 3'h5: merge previous slot. 3'h6: empty, slot interval = slot_int reg 3'h7: move to next non-empty slot after one cycle don't set 4 before 7" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70204++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART2,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_15 ,slot15 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_14 ,slot14 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_13 ,slot13 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_12 ,slot12 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_11 ,slot11 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_10 ,slot10 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_9 ,slot9 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_8 ,slot8 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70208++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART3,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_23 ,slot23 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_22 ,slot22 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_21 ,slot21 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_20 ,slot20 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_19 ,slot18 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_18 ,slot19 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_17 ,slot17 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_16 ,slot16 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F7020C++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART4,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_31 ,slot31 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_30 ,slot30 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_29 ,slot29 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_28 ,slot28 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_27 ,slot27 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_26 ,slot26 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_25 ,slot25 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_24 ,slot24 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70210++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART5,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_39 ,slot39 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_38 ,slot38 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_37 ,slot37 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_36 ,slot36 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_35 ,slot35 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_34 ,slot34 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_33 ,slot33 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_32 ,slot32 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70214++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART6,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_47 ,slot47 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_46 ,slot46 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_45 ,slot45 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_44 ,slot44 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_43 ,slot43 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_42 ,slot42 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_41 ,slot41 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_40 ,slot40 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70218++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART7,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_55 ,slot55 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_54 ,slot54 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_53 ,slot53 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_52 ,slot52 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_51 ,slot51 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_50 ,slot50 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_49 ,slot49 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_48 ,slot48 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F7021C++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART8,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_63 ,slot63 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_62 ,slot62 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_61 ,slo61 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_60 ,slot60 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_59 ,slot59 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_58 ,slot58 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_57 ,slot57 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_56 ,slot56 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70220++0x03
|
|
line.long 0x00 "SADC_TS_VALUE,sadc time stamp value"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,time stamp terminal value"
|
|
group ad:0xF0F70224++0x03
|
|
line.long 0x00 "SADC_SCH_TIMEOUT,sadc schedule slot timeout reg"
|
|
hexmask.long.word 0x00 0.--15. 1. " THRD ,slot length depend on analog out_en mode, the timeout threshold for waiting next trigger this counter is based on ctrl_clk, the threshold must consider analog clock devider"
|
|
group ad:0xF0F70230++0x03
|
|
line.long 0x00 "SADC_SCH_CFG,SADC scheduler configuration"
|
|
bitfld.long 0x00 31. " TS_RST ,1:timestamp soft reset" "0,1"
|
|
bitfld.long 0x00 30. " TS_VLD ,1: timestamp can work 0: timestamp keep current value" "0,1"
|
|
bitfld.long 0x00 28. " RST_DONE ,scheduler reset done flag" "0,1"
|
|
bitfld.long 0x00 25. " SLOT_RST ,1: time slot rotation pointer reset to 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "SLOT_HALT ,1: time slot rotation halt (config if you moDIfy entry configurations)" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLV_DLY ,scheduler slave delay value after EXT_SYNC_I"
|
|
bitfld.long 0x00 12. " ASYNC_STALL ,for async mode, if set to 1, ext_sync_o will send 1 to slave, and all adc will stop senDIng soc to analog" "0,1"
|
|
bitfld.long 0x00 11. " ROT_EN ,1:scheduler sync mode rotation enable 0:scheduler sync mode rotation DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "SYNC_MODE ,1:scheduler is sync mode. 0: scheduler is async mode" "0,1"
|
|
bitfld.long 0x00 9. " MST_MODE ,1:scheduler is master when multi-ADC 0:scheduler is slave when multi-ADC" "0,1"
|
|
bitfld.long 0x00 8. " SLOT_MODE ,1:scheduler slot interval is constant. 0: slot interval depends on ADC conversion time (the feedback 'OUTEN' from analog)" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_INTERVAL ,scheduler interval for each slot is constant"
|
|
group ad:0xF0F70234++0x03
|
|
line.long 0x00 "SADC_SCH_PRIO,SADC scheduler async mode priority(unused)"
|
|
bitfld.long 0x00 16.--18. " RC3 ,RC3 priority (5th)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " RC2 ,RC2 priority (4th)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " RC1 ,RC1 priority (third)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " RC0 ,RC0 priority (second)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "RCHT ,RCHT priority (first)" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70238++0x03
|
|
line.long 0x00 "SADC_CLK_CTRL,SADC clock control"
|
|
bitfld.long 0x00 12.--15. " REF_LOW ,clock low period of the reference clock (ctrl_clk)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " REF_HIGH ,clock high period of the reference clock (ctrl_clk)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " DIV_BYPASS ,1:analog clock DIvider bypass, use control clock DIrectly" "0,1"
|
|
group ad:0xF0F70240++0x03
|
|
line.long 0x00 "SADC_ANA_REF_PART1,SADC analog reference configuration part1"
|
|
hexmask.long.word 0x00 16.--31. 1. " PDC ,safety feature control, ADC negative input switch"
|
|
bitfld.long 0x00 1. " PDBIAS ,BIAS power down" "0,1"
|
|
bitfld.long 0x00 0. " PD ,SAR analog part power down" "0,1"
|
|
group ad:0xF0F70244++0x03
|
|
line.long 0x00 "SADC_ANA_REF_PART2,SADC analog reference configuration part2"
|
|
hexmask.long.word 0x00 16.--31. 1. " MCN ,safety feature control"
|
|
hexmask.long.word 0x00 0.--15. 1. " MCP ,safety feature control"
|
|
group ad:0xF0F70248++0x03
|
|
line.long 0x00 "SADC_CONT_MODE,SADC continuous mode"
|
|
bitfld.long 0x00 31. " SOC ,continuous mode soc" "0,1"
|
|
bitfld.long 0x00 21.--23. " SAMCTRL ,ADC sample time control Please set to 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing . Please set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control Please set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. "CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On Please set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " EN ,1: continuous mode enable" "0,1"
|
|
bitfld.long 0x00 6. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
bitfld.long 0x00 5. " REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. "RC_SEL ,belong to which rc channel. bit4:rcht bit3:rc0 bit2:rc1 bit1:rc2 bit0:rc3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F7024C++0x03
|
|
line.long 0x00 "SADC_CONT_MODE_1,continuous mode part2"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog amsel"
|
|
group ad:0xF0F70250++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_0,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70254++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_1,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70258++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_2,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F7025C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_3,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70260++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_4,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70264++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_5,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70268++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_6,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F7026C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_7,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70270++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_8,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70274++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_9,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70278++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_10,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F7027C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_11,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70280++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_12,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70284++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_13,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70288++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_14,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F7028C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_15,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F70290++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_0,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F70294++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_1,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F70298++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_2,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F7029C++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_3,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F702A0++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_4,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F702A4++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_5,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F702A8++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_6,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F702AC++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_7,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F702B0++0x03
|
|
line.long 0x00 "SADC_MNT_CONT,SADC monitor mask continuous channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} for continuous monitor"
|
|
group ad:0xF0F702B4++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_0,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F702B8++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_1,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F702BC++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_2,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F702C0++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_3,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F702C4++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_4,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F702C8++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_5,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F702CC++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_6,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F702D0++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_7,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F702D4++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_CONT,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F702E0++0x03
|
|
line.long 0x00 "SADC_MNT_CONT_CFG,SADC monitor continuous configuration"
|
|
hexmask.long.byte 0x00 16.--21. 1. " CONT_THRD ,continuous counter threshold"
|
|
bitfld.long 0x00 0. " CONT_MODE ,1:Reset immeDIately when the result does not hit the trigger conDItion 0:Increase on trigger conDItion hit and decrease on trigger conDItion does not hit" "0,1"
|
|
group ad:0xF0F702E4++0x03
|
|
line.long 0x00 "SADC_FIFO_CFG,SADC fifo control configuration"
|
|
bitfld.long 0x00 8. " PACK16_AMSEL_EN ,for pack 16 mode 1: { amsel[3:0] ,sarout[11:0]} 0: {4'h0, sarout[11:0]}" "0,1"
|
|
bitfld.long 0x00 4. " BYPASS ,1:bypass fifo" "0,1"
|
|
bitfld.long 0x00 0.--1. " PACK_MODE ,2'b11: reserved 2'b10: 64bit 2'b01: 32bit 2'b00: 16bit" "0,1,2,3"
|
|
group ad:0xF0F702E8++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_0,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F702EC++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_1,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F702F0++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_2,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F702F4++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_3,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F702F8++0x03
|
|
line.long 0x00 "SADC_DMA,SADC dma configuration"
|
|
bitfld.long 0x00 16.--20. " CHN1_EN ,for DMA channel 1 bit20: rcht enable bit19: sub-fifo 0/ rc0 enable bit18: sub-fifo 1/rc1 enable bit17: sub-fifo 2/rc2 enable bit16: sub-fifo 3/rc3 enable valid bit must <= 1 , valid bits > 1 will cause error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " CHN0_EN ,for DMA channel 0 bit12: rcht enable bit11: sub-fifo 0/ rc0 enable bit10: sub-fifo 1/rc1 enable bit9: sub-fifo 2/rc2 enable bit8: sub-fifo 3/rc3 enable valid bit must <= 1 , valid bits > 1 will cause error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MODE ,bit4: 0:rcht conversion done bit3: 1:sub-fifo0 almost full 0: rc0 conversion done bit2: 1:sub-fifo1 almost full 0: rc1 conversion done bit1: 1:sub-fifo2 almost full 0: rc2 conversion done bit0: 1:sub-fifo3 almost full 0: rc3 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F70400++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,parity error status register bit"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,parity error status register bit" "0,1"
|
|
group ad:0xF0F70404++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,mask enable bit of parity error"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,1: REG_PARITY_ERR_INT_STAT is updated. 0: REG_PARITY_ERR_INT_STAT is not updated" "0,1"
|
|
group ad:0xF0F70408++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,interrupt enable bit of parity error status register bit"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,0: REG_PARITY_ERR_INT_STAT interrupt is DIsabled 1: REG_PARITY_ERR_INT_STAT interrupt is enabled" "0,1"
|
|
group ad:0xF0F70410++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,fusa correctable error interrupt status"
|
|
bitfld.long 0x00 3. " SRAM_RDATA_COR_ERR ,SRAM rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " DMA1_BW_COR_ERR ,DMA 1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_COR_ERR ,DMA 0 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0F70414++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,fusa correctable error interrupt status enable"
|
|
bitfld.long 0x00 3. " SRAM_RDATA_COR_ERR ,SRAM rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " DMA1_BW_COR_ERR ,DMA 1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_COR_ERR ,DMA 0 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0F70418++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,fusa correctable error interrupt signal enable"
|
|
bitfld.long 0x00 3. " SRAM_RDATA_COR_ERR ,SRAM rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " DMA1_BW_COR_ERR ,DMA 1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_COR_ERR ,DMA 0 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0F70420++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,fusa uncorrectable error interrupt status"
|
|
bitfld.long 0x00 14. " SRAM_RDATA_FATAL_ERR ,SRAM rdata fatal error." "0,1"
|
|
bitfld.long 0x00 13. " SRAM_RDATA_UNC_ERR ,SRAM rdata uncorrctable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,dma 1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA0_EOBC_ERR ,dma 0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "DMA1_EOBA_ERR ,dma 1 eoba error" "0,1"
|
|
bitfld.long 0x00 9. " DMA0_EOBA_ERR ,dma 0 eoba error" "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_FATAL_ERR ,DMA 1 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 7. " DMA1_BW_UNC_ERR ,DMA 1 backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DMA0_BW_FATAL_ERR ,DMA 0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_BW_UNC_ERR ,DMA 0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,APB control signals(pwrite,psel,penable) parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PADDR_UNCOR_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error" "0,1"
|
|
group ad:0xF0F70424++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,fusa uncorrectable error interrupt status enable"
|
|
bitfld.long 0x00 14. " SRAM_RDATA_FATAL_ERR ,SRAM rdata fatal error." "0,1"
|
|
bitfld.long 0x00 13. " SRAM_RDATA_UNC_ERR ,SRAM rdata uncorrctable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,dma 1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA0_EOBC_ERR ,dma 0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "DMA1_EOBA_ERR ,dma 1 eoba error" "0,1"
|
|
bitfld.long 0x00 9. " DMA0_EOBA_ERR ,dma 0 eoba error" "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_FATAL_ERR ,DMA 1 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 7. " DMA1_BW_UNC_ERR ,DMA 1 backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DMA0_BW_FATAL_ERR ,DMA 0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_BW_UNC_ERR ,DMA 0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,APB control signals(pwrite,psel,penable) parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PADDR_UNCOR_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error" "0,1"
|
|
group ad:0xF0F70428++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,fusa uncorrectable error interrupt signal enable"
|
|
bitfld.long 0x00 14. " SRAM_RDATA_FATAL_ERR ,SRAM rdata fatal error." "0,1"
|
|
bitfld.long 0x00 13. " SRAM_RDATA_UNC_ERR ,SRAM rdata uncorrctable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,dma 1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA0_EOBC_ERR ,dma 0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "DMA1_EOBA_ERR ,dma 1 eoba error" "0,1"
|
|
bitfld.long 0x00 9. " DMA0_EOBA_ERR ,dma 0 eoba error" "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_FATAL_ERR ,DMA 1 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 7. " DMA1_BW_UNC_ERR ,DMA 1 backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DMA0_BW_FATAL_ERR ,DMA 0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_BW_UNC_ERR ,DMA 0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,APB control signals(pwrite,psel,penable) parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PADDR_UNCOR_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error" "0,1"
|
|
group ad:0xF0F70430++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF0F70434++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF0F70438++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
group ad:0xF0F7043C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0F70450++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,SRAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF0F70454++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0F70458++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,SRAM rdata monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF0F7045C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,SRAM rdata ECC monitorerror injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0F70460++0x03
|
|
line.long 0x00 "SADC_CONV_RCHT_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,{TS[11:0], 1'b0, AMSEL[6:0], SAROUT[11:0]}"
|
|
group ad:0xF0F70464++0x03
|
|
line.long 0x00 "SADC_CONV_RCHT_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,{20'h0, TS[23:12]}"
|
|
group ad:0xF0F70468++0x03
|
|
line.long 0x00 "SADC_CONV_RC0_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F7046C++0x03
|
|
line.long 0x00 "SADC_CONV_RC0_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F70470++0x03
|
|
line.long 0x00 "SADC_CONV_RC1_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F70474++0x03
|
|
line.long 0x00 "SADC_CONV_RC1_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F70478++0x03
|
|
line.long 0x00 "SADC_CONV_RC2_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F7047C++0x03
|
|
line.long 0x00 "SADC_CONV_RC2_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F70480++0x03
|
|
line.long 0x00 "SADC_CONV_RC3_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F70484++0x03
|
|
line.long 0x00 "SADC_CONV_RC3_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F70488++0x03
|
|
line.long 0x00 "ATE_TEST,ATE test mode select"
|
|
bitfld.long 0x00 0. " EN ,ate test enable" "0,1"
|
|
group ad:0xF0F7048C++0x03
|
|
line.long 0x00 "ATE_TEST_CFG,ATE test configuration reg"
|
|
bitfld.long 0x00 24.--26. " EXT_AMSEL ,EXT_AMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " SAMCTRL ,SAMCTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " CCN ,CCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CCP ,CCP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--10. 1. "INSEL ,INSEL"
|
|
bitfld.long 0x00 2. " SDSEL ,SDSEL" "0,1"
|
|
bitfld.long 0x00 1. " REFSEL ,REFSEL" "0,1"
|
|
bitfld.long 0x00 0. " DCOC_EN ,DCOC_EN" "0,1"
|
|
group ad:0xF0F70490++0x03
|
|
line.long 0x00 "SADC_DBG_REG_CTRL,sadc debug control register"
|
|
bitfld.long 0x00 1. " CLEAR ,clear debug data. auto clear" "0,1"
|
|
bitfld.long 0x00 0. " LOCK ,lock debug data" "0,1"
|
|
group ad:0xF0F70494++0x03
|
|
line.long 0x00 "SADC_DBG_REG_0,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " HTC_ACK_CNT ,send ack number"
|
|
group ad:0xF0F70498++0x03
|
|
line.long 0x00 "SADC_DBG_REG_1,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " HTC_CNT ,receive hardware trigger number"
|
|
group ad:0xF0F7049C++0x03
|
|
line.long 0x00 "SADC_DBG_REG_2,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " SOC_CNT ,send soc counter"
|
|
group ad:0xF0F704A0++0x03
|
|
line.long 0x00 "SADC_DBG_REG_3,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC0_REC_CNT ,rc0 receive A_ADC data"
|
|
group ad:0xF0F704A4++0x03
|
|
line.long 0x00 "SADC_DBG_REG_4,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC1_REC_CNT ,rc1 receive A_ADC data"
|
|
group ad:0xF0F704A8++0x03
|
|
line.long 0x00 "SADC_DBG_REG_5,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC2_REC_CNT ,rc2 receive A_ADC data"
|
|
group ad:0xF0F704AC++0x03
|
|
line.long 0x00 "SADC_DBG_REG_6,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC3_REC_CNT ,rc3 receive A_ADC data"
|
|
group ad:0xF0F704B0++0x03
|
|
line.long 0x00 "SADC_DBG_REG_7,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RCHT_REC_CNT ,rcht receive A_ADC data"
|
|
group ad:0xF0F704B4++0x03
|
|
line.long 0x00 "SADC_DBG_REG_8,sadc debug register"
|
|
hexmask.long.byte 0x00 0.--5. 1. " SLOT_CNT ,sync mode slot counter"
|
|
group ad:0xF0F704B8++0x03
|
|
line.long 0x00 "SADC_DBG_REG_9,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " TOTAL_REC_CNT ,total receive A_ADC data"
|
|
tree.end
|
|
tree "ADC2"
|
|
width 28.
|
|
group ad:0xF0F80000++0x03
|
|
line.long 0x00 "SADC_SOFT_RST,SADC soft reset"
|
|
bitfld.long 0x00 5. " RC3_TMR_RST ,rc3 timer soft reset" "0,1"
|
|
bitfld.long 0x00 4. " RC2_TMR_RST ,rc2 timer soft reset" "0,1"
|
|
bitfld.long 0x00 3. " RC1_TMR_RST ,rc1 timer soft reset" "0,1"
|
|
bitfld.long 0x00 2. " RC0_TMR_RST ,rc0 timer soft reset" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "ANA_RST ,analog soft reset default reset analog macro, need software change to 1 when start to work" "0,1"
|
|
bitfld.long 0x00 0. " DIG_RST ,DIgital soft reset" "0,1"
|
|
group ad:0xF0F80004++0x03
|
|
line.long 0x00 "SADC_INIT,SADC init configuration"
|
|
bitfld.long 0x00 24. " DONE ,sadc initial done status" "0,1"
|
|
bitfld.long 0x00 20. " START ,sadc initial start reg. auto clear" "0,1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,sadc initial start value"
|
|
group ad:0xF0F80008++0x03
|
|
line.long 0x00 "SADC_DCOC,SADC dcoc configuration"
|
|
bitfld.long 0x00 31. " DONE ,dcoc done signal" "0,1"
|
|
hexmask.long.word 0x00 16.--28. 1. " VALUE ,bit28: sign bit. bit27~16 : dc offset value"
|
|
bitfld.long 0x00 8. " SOFT_OVWR_EN ,software overwrite dc offset value. auto clear" "0,1"
|
|
bitfld.long 0x00 4. " EN ,1: the ADC result will minus dcoc result. 0: use default value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "START ,1:start to calculate dcoc. auto clear after calculation done" "0,1"
|
|
bitfld.long 0x00 0.--2. " TIMES ,dcoc average calculation times. 0: 1 1: 2 2: 4 3: 8 4:16 5:32 6:64 7:128" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F8000C++0x03
|
|
line.long 0x00 "SADC_HTC,SADC htc register"
|
|
bitfld.long 0x00 31. " READY ,when init or dcoc, SADC can not accept hardware trigger outside. Software read init done and dcoc done, config this reg to 1" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " READY_LEN ,for scheduler sync mode, htc ready length when next slot is RCHT"
|
|
bitfld.long 0x00 0.--3. " DONE_LEN ,htc done length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F80010++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_0,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80014++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_1,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80018++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_2,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F8001C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_3,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80020++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_4,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80024++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_5,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80028++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_6,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F8002C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_7,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80030++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_8,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80034++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_9,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80038++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_10,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F8003C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_11,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80040++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_12,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80044++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_13,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80048++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_14,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F8004C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_15,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80050++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_16,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80054++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_17,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80058++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_18,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F8005C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_19,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80060++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_20,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80064++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_21,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80068++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_22,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F8006C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_23,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80070++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_24,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80074++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_25,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80078++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_26,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F8007C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_27,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80080++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_28,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80084++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_29,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80088++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_30,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F8008C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_31,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F80090++0x03
|
|
line.long 0x00 "SADC_RC0_TIMER,RC0 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER compare value"
|
|
group ad:0xF0F80094++0x03
|
|
line.long 0x00 "SADC_RC1_TIMER,RC1 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER compare value"
|
|
group ad:0xF0F80098++0x03
|
|
line.long 0x00 "SADC_RC2_TIMER,RC2 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER compare value"
|
|
group ad:0xF0F8009C++0x03
|
|
line.long 0x00 "SADC_RC3_TIMER,RC3 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER counter value"
|
|
group ad:0xF0F800A0++0x03
|
|
line.long 0x00 "SADC_RC0,SADC RC0 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F800A4++0x03
|
|
line.long 0x00 "SADC_RC1,SADC RC1 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F800A8++0x03
|
|
line.long 0x00 "SADC_RC2,SADC RC2 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F800AC++0x03
|
|
line.long 0x00 "SADC_RC3,SADC RC3 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear." "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F800B0++0x03
|
|
line.long 0x00 "SADC_INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 24. " MNT_EVT_CONT ,continuous monitor event" "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 12. " TS_OVF ,Scheduler time stamp overflow" "0,1"
|
|
bitfld.long 0x00 11. " WATER_MARK_SUB_3 ,SUB-FIFO3 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 10. " WATER_MARK_SUB_2 ,SUB-FIFO2 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "WATER_MARK_SUB_1 ,SUB-FIFO1 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 8. " WATER_MARK_SUB_0 ,SUB-FIFO0 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 4. " END_COV_RCHT ,rcht end of each conversion" "0,1"
|
|
bitfld.long 0x00 3. " END_COV_RC0 ,rc0 end of each conversion" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "END_COV_RC1 ,rc1 end of each conversion" "0,1"
|
|
bitfld.long 0x00 1. " END_COV_RC2 ,rc2 end of each conversion" "0,1"
|
|
bitfld.long 0x00 0. " END_COV_RC3 ,rc3 end of each conversion" "0,1"
|
|
group ad:0xF0F800B4++0x03
|
|
line.long 0x00 "SADC_INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 24. " MNT_EVT_CONT ,continuous monitor event" "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 12. " TS_OVF ,Scheduler time stamp overflow" "0,1"
|
|
bitfld.long 0x00 11. " WATER_MARK_SUB_3 ,SUB-FIFO3 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 10. " WATER_MARK_SUB_2 ,SUB-FIFO2 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "WATER_MARK_SUB_1 ,SUB-FIFO1 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 8. " WATER_MARK_SUB_0 ,SUB-FIFO0 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 4. " END_COV_RCHT ,rcht end of each conversion" "0,1"
|
|
bitfld.long 0x00 3. " END_COV_RC0 ,rc0 end of each conversion" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "END_COV_RC1 ,rc1 end of each conversion" "0,1"
|
|
bitfld.long 0x00 1. " END_COV_RC2 ,rc2 end of each conversion" "0,1"
|
|
bitfld.long 0x00 0. " END_COV_RC3 ,rc3 end of each conversion" "0,1"
|
|
group ad:0xF0F800B8++0x03
|
|
line.long 0x00 "SADC_INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 24. " MNT_EVT_CONT ,continuous monitor event" "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 12. " TS_OVF ,Scheduler time stamp overflow" "0,1"
|
|
bitfld.long 0x00 11. " WATER_MARK_SUB_3 ,SUB-FIFO3 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 10. " WATER_MARK_SUB_2 ,SUB-FIFO2 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "WATER_MARK_SUB_1 ,SUB-FIFO1 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 8. " WATER_MARK_SUB_0 ,SUB-FIFO0 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 4. " END_COV_RCHT ,rcht end of each conversion" "0,1"
|
|
bitfld.long 0x00 3. " END_COV_RC0 ,rc0 end of each conversion" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "END_COV_RC1 ,rc1 end of each conversion" "0,1"
|
|
bitfld.long 0x00 1. " END_COV_RC2 ,rc2 end of each conversion" "0,1"
|
|
bitfld.long 0x00 0. " END_COV_RC3 ,rc3 end of each conversion" "0,1"
|
|
group ad:0xF0F800C0++0x03
|
|
line.long 0x00 "SADC_COR_ERR_INT_STA,Correctable error interrupt status register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
group ad:0xF0F800C4++0x03
|
|
line.long 0x00 "SADC_COR_ERR_INT_STA_EN,Correctable error interrupt status enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
group ad:0xF0F800C8++0x03
|
|
line.long 0x00 "SADC_COR_ERR_INT_SIG_EN,Correctable error interrupt signal enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
group ad:0xF0F800D0++0x03
|
|
line.long 0x00 "SADC_UNC_ERR_INT_STA,Uncorrectable error interrupt status register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 0. " ANA_EXT_MUX_ERR ,analog external mux error" "0,1"
|
|
group ad:0xF0F800D4++0x03
|
|
line.long 0x00 "SADC_UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 0. " ANA_EXT_MUX_ERR ,analog external mux error" "0,1"
|
|
group ad:0xF0F800D8++0x03
|
|
line.long 0x00 "SADC_UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt signal enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 0. " ANA_EXT_MUX_ERR ,analog external mux error" "0,1"
|
|
group ad:0xF0F800E0++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 4.--6. " DMA1 ,Data error injection for DMA1 channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DMA0 ,Data error injection for DMA0 channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F800E4++0x03
|
|
line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 4.--7. " DMA1 ,Code error injection for DMA 1 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMA0 ,Code error injection for DMA 0 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F800E8++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 4.--7. " DMA1 ,Data error injection for DMA1 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMA0 ,Data error injection for DMA0 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F800EC++0x03
|
|
line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
|
bitfld.long 0x00 4.--7. " DMA1 ,Code error injection for DMA 1 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMA0 ,Code error injection for DMA 0 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F800F0++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 2. " UNC ,uncorrectable error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR ,correctable error injection" "0,1"
|
|
bitfld.long 0x00 0. " FUNC ,function error injection" "0,1"
|
|
group ad:0xF0F80100++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_0,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector [8:6] for analog mux sel. for DIff mode: [5:3] = p [2:0] = n, for single mode: [3]: 1 -> P/ 0 ->N [2:0] control channel"
|
|
group ad:0xF0F80104++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_1,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80108++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_2,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8010C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_3,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80110++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_4,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80114++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_5,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80118++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_6,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8011C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_7,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80120++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_8,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80124++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_9,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80128++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_10,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8012C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_11,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80130++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_12,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80134++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_13,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80138++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_14,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8013C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_15,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80140++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_0,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80144++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_1,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80148++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_2,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8014C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_3,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80150++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_4,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80154++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_5,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80158++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_6,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8015C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_7,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80160++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_8,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80164++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_9,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80168++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_10,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8016C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_11,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80170++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_12,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80174++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_13,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80178++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_14,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8017C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_15,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80180++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_0,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80184++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_1,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80188++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_2,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8018C++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_3,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80190++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_4,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80194++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_5,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80198++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_6,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F8019C++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_7,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801A0++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_8,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801A4++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_9,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801A8++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_10,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801AC++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_11,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801B0++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_12,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801B4++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_13,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801B8++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_14,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801BC++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_15,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801C0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_0,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801C4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_1,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801C8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_2,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801CC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_3,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801D0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_4,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801D4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_5,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801D8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_6,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801DC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_7,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801E0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_8,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801E4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_9,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801E8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_10,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801EC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_11,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801F0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_12,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801F4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_13,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801F8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_14,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F801FC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_15,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F80200++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART1,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_7 ,slot7 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_6 ,slot6 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_5 ,slot5 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_4 ,slot4 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_3 ,slot3 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_2 ,slot2 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_1 ,slot1 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_0 ,slot0 cid 3'h0: rc0 3'h1: rc1 3'h2: rc2 3'h3: rc3 3'h4: rcht 3'h5: merge previous slot. 3'h6: empty, slot interval = slot_int reg 3'h7: move to next non-empty slot after one cycle don't set 4 before 7" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80204++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART2,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_15 ,slot15 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_14 ,slot14 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_13 ,slot13 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_12 ,slot12 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_11 ,slot11 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_10 ,slot10 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_9 ,slot9 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_8 ,slot8 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80208++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART3,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_23 ,slot23 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_22 ,slot22 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_21 ,slot21 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_20 ,slot20 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_19 ,slot18 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_18 ,slot19 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_17 ,slot17 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_16 ,slot16 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F8020C++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART4,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_31 ,slot31 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_30 ,slot30 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_29 ,slot29 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_28 ,slot28 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_27 ,slot27 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_26 ,slot26 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_25 ,slot25 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_24 ,slot24 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80210++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART5,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_39 ,slot39 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_38 ,slot38 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_37 ,slot37 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_36 ,slot36 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_35 ,slot35 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_34 ,slot34 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_33 ,slot33 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_32 ,slot32 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80214++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART6,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_47 ,slot47 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_46 ,slot46 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_45 ,slot45 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_44 ,slot44 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_43 ,slot43 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_42 ,slot42 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_41 ,slot41 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_40 ,slot40 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80218++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART7,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_55 ,slot55 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_54 ,slot54 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_53 ,slot53 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_52 ,slot52 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_51 ,slot51 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_50 ,slot50 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_49 ,slot49 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_48 ,slot48 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F8021C++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART8,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_63 ,slot63 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_62 ,slot62 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_61 ,slo61 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_60 ,slot60 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_59 ,slot59 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_58 ,slot58 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_57 ,slot57 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_56 ,slot56 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80220++0x03
|
|
line.long 0x00 "SADC_TS_VALUE,sadc time stamp value"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,time stamp terminal value"
|
|
group ad:0xF0F80224++0x03
|
|
line.long 0x00 "SADC_SCH_TIMEOUT,sadc schedule slot timeout reg"
|
|
hexmask.long.word 0x00 0.--15. 1. " THRD ,slot length depend on analog out_en mode, the timeout threshold for waiting next trigger this counter is based on ctrl_clk, the threshold must consider analog clock devider"
|
|
group ad:0xF0F80230++0x03
|
|
line.long 0x00 "SADC_SCH_CFG,SADC scheduler configuration"
|
|
bitfld.long 0x00 31. " TS_RST ,1:timestamp soft reset" "0,1"
|
|
bitfld.long 0x00 30. " TS_VLD ,1: timestamp can work 0: timestamp keep current value" "0,1"
|
|
bitfld.long 0x00 28. " RST_DONE ,scheduler reset done flag" "0,1"
|
|
bitfld.long 0x00 25. " SLOT_RST ,1: time slot rotation pointer reset to 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "SLOT_HALT ,1: time slot rotation halt (config if you moDIfy entry configurations)" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLV_DLY ,scheduler slave delay value after EXT_SYNC_I"
|
|
bitfld.long 0x00 12. " ASYNC_STALL ,for async mode, if set to 1, ext_sync_o will send 1 to slave, and all adc will stop senDIng soc to analog" "0,1"
|
|
bitfld.long 0x00 11. " ROT_EN ,1:scheduler sync mode rotation enable 0:scheduler sync mode rotation DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "SYNC_MODE ,1:scheduler is sync mode. 0: scheduler is async mode" "0,1"
|
|
bitfld.long 0x00 9. " MST_MODE ,1:scheduler is master when multi-ADC 0:scheduler is slave when multi-ADC" "0,1"
|
|
bitfld.long 0x00 8. " SLOT_MODE ,1:scheduler slot interval is constant. 0: slot interval depends on ADC conversion time (the feedback 'OUTEN' from analog)" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_INTERVAL ,scheduler interval for each slot is constant"
|
|
group ad:0xF0F80234++0x03
|
|
line.long 0x00 "SADC_SCH_PRIO,SADC scheduler async mode priority(unused)"
|
|
bitfld.long 0x00 16.--18. " RC3 ,RC3 priority (5th)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " RC2 ,RC2 priority (4th)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " RC1 ,RC1 priority (third)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " RC0 ,RC0 priority (second)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "RCHT ,RCHT priority (first)" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80238++0x03
|
|
line.long 0x00 "SADC_CLK_CTRL,SADC clock control"
|
|
bitfld.long 0x00 12.--15. " REF_LOW ,clock low period of the reference clock (ctrl_clk)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " REF_HIGH ,clock high period of the reference clock (ctrl_clk)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " DIV_BYPASS ,1:analog clock DIvider bypass, use control clock DIrectly" "0,1"
|
|
group ad:0xF0F80240++0x03
|
|
line.long 0x00 "SADC_ANA_REF_PART1,SADC analog reference configuration part1"
|
|
hexmask.long.word 0x00 16.--31. 1. " PDC ,safety feature control, ADC negative input switch"
|
|
bitfld.long 0x00 1. " PDBIAS ,BIAS power down" "0,1"
|
|
bitfld.long 0x00 0. " PD ,SAR analog part power down" "0,1"
|
|
group ad:0xF0F80244++0x03
|
|
line.long 0x00 "SADC_ANA_REF_PART2,SADC analog reference configuration part2"
|
|
hexmask.long.word 0x00 16.--31. 1. " MCN ,safety feature control"
|
|
hexmask.long.word 0x00 0.--15. 1. " MCP ,safety feature control"
|
|
group ad:0xF0F80248++0x03
|
|
line.long 0x00 "SADC_CONT_MODE,SADC continuous mode"
|
|
bitfld.long 0x00 31. " SOC ,continuous mode soc" "0,1"
|
|
bitfld.long 0x00 21.--23. " SAMCTRL ,ADC sample time control Please set to 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing . Please set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control Please set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. "CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On Please set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " EN ,1: continuous mode enable" "0,1"
|
|
bitfld.long 0x00 6. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
bitfld.long 0x00 5. " REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. "RC_SEL ,belong to which rc channel. bit4:rcht bit3:rc0 bit2:rc1 bit1:rc2 bit0:rc3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F8024C++0x03
|
|
line.long 0x00 "SADC_CONT_MODE_1,continuous mode part2"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog amsel"
|
|
group ad:0xF0F80250++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_0,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80254++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_1,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80258++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_2,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F8025C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_3,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80260++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_4,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80264++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_5,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80268++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_6,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F8026C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_7,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80270++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_8,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80274++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_9,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80278++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_10,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F8027C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_11,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80280++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_12,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80284++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_13,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80288++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_14,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F8028C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_15,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F80290++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_0,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F80294++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_1,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F80298++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_2,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F8029C++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_3,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F802A0++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_4,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F802A4++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_5,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F802A8++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_6,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F802AC++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_7,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F802B0++0x03
|
|
line.long 0x00 "SADC_MNT_CONT,SADC monitor mask continuous channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} for continuous monitor"
|
|
group ad:0xF0F802B4++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_0,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F802B8++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_1,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F802BC++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_2,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F802C0++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_3,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F802C4++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_4,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F802C8++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_5,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F802CC++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_6,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F802D0++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_7,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F802D4++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_CONT,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F802E0++0x03
|
|
line.long 0x00 "SADC_MNT_CONT_CFG,SADC monitor continuous configuration"
|
|
hexmask.long.byte 0x00 16.--21. 1. " CONT_THRD ,continuous counter threshold"
|
|
bitfld.long 0x00 0. " CONT_MODE ,1:Reset immeDIately when the result does not hit the trigger conDItion 0:Increase on trigger conDItion hit and decrease on trigger conDItion does not hit" "0,1"
|
|
group ad:0xF0F802E4++0x03
|
|
line.long 0x00 "SADC_FIFO_CFG,SADC fifo control configuration"
|
|
bitfld.long 0x00 8. " PACK16_AMSEL_EN ,for pack 16 mode 1: { amsel[3:0] ,sarout[11:0]} 0: {4'h0, sarout[11:0]}" "0,1"
|
|
bitfld.long 0x00 4. " BYPASS ,1:bypass fifo" "0,1"
|
|
bitfld.long 0x00 0.--1. " PACK_MODE ,2'b11: reserved 2'b10: 64bit 2'b01: 32bit 2'b00: 16bit" "0,1,2,3"
|
|
group ad:0xF0F802E8++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_0,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F802EC++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_1,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F802F0++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_2,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F802F4++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_3,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F802F8++0x03
|
|
line.long 0x00 "SADC_DMA,SADC dma configuration"
|
|
bitfld.long 0x00 16.--20. " CHN1_EN ,for DMA channel 1 bit20: rcht enable bit19: sub-fifo 0/ rc0 enable bit18: sub-fifo 1/rc1 enable bit17: sub-fifo 2/rc2 enable bit16: sub-fifo 3/rc3 enable valid bit must <= 1 , valid bits > 1 will cause error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " CHN0_EN ,for DMA channel 0 bit12: rcht enable bit11: sub-fifo 0/ rc0 enable bit10: sub-fifo 1/rc1 enable bit9: sub-fifo 2/rc2 enable bit8: sub-fifo 3/rc3 enable valid bit must <= 1 , valid bits > 1 will cause error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MODE ,bit4: 0:rcht conversion done bit3: 1:sub-fifo0 almost full 0: rc0 conversion done bit2: 1:sub-fifo1 almost full 0: rc1 conversion done bit1: 1:sub-fifo2 almost full 0: rc2 conversion done bit0: 1:sub-fifo3 almost full 0: rc3 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F80400++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,parity error status register bit"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,parity error status register bit" "0,1"
|
|
group ad:0xF0F80404++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,mask enable bit of parity error"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,1: REG_PARITY_ERR_INT_STAT is updated. 0: REG_PARITY_ERR_INT_STAT is not updated" "0,1"
|
|
group ad:0xF0F80408++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,interrupt enable bit of parity error status register bit"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,0: REG_PARITY_ERR_INT_STAT interrupt is DIsabled 1: REG_PARITY_ERR_INT_STAT interrupt is enabled" "0,1"
|
|
group ad:0xF0F80410++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,fusa correctable error interrupt status"
|
|
bitfld.long 0x00 3. " SRAM_RDATA_COR_ERR ,SRAM rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " DMA1_BW_COR_ERR ,DMA 1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_COR_ERR ,DMA 0 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0F80414++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,fusa correctable error interrupt status enable"
|
|
bitfld.long 0x00 3. " SRAM_RDATA_COR_ERR ,SRAM rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " DMA1_BW_COR_ERR ,DMA 1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_COR_ERR ,DMA 0 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0F80418++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,fusa correctable error interrupt signal enable"
|
|
bitfld.long 0x00 3. " SRAM_RDATA_COR_ERR ,SRAM rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " DMA1_BW_COR_ERR ,DMA 1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_COR_ERR ,DMA 0 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0F80420++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,fusa uncorrectable error interrupt status"
|
|
bitfld.long 0x00 14. " SRAM_RDATA_FATAL_ERR ,SRAM rdata fatal error." "0,1"
|
|
bitfld.long 0x00 13. " SRAM_RDATA_UNC_ERR ,SRAM rdata uncorrctable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,dma 1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA0_EOBC_ERR ,dma 0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "DMA1_EOBA_ERR ,dma 1 eoba error" "0,1"
|
|
bitfld.long 0x00 9. " DMA0_EOBA_ERR ,dma 0 eoba error" "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_FATAL_ERR ,DMA 1 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 7. " DMA1_BW_UNC_ERR ,DMA 1 backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DMA0_BW_FATAL_ERR ,DMA 0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_BW_UNC_ERR ,DMA 0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,APB control signals(pwrite,psel,penable) parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PADDR_UNCOR_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error" "0,1"
|
|
group ad:0xF0F80424++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,fusa uncorrectable error interrupt status enable"
|
|
bitfld.long 0x00 14. " SRAM_RDATA_FATAL_ERR ,SRAM rdata fatal error." "0,1"
|
|
bitfld.long 0x00 13. " SRAM_RDATA_UNC_ERR ,SRAM rdata uncorrctable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,dma 1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA0_EOBC_ERR ,dma 0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "DMA1_EOBA_ERR ,dma 1 eoba error" "0,1"
|
|
bitfld.long 0x00 9. " DMA0_EOBA_ERR ,dma 0 eoba error" "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_FATAL_ERR ,DMA 1 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 7. " DMA1_BW_UNC_ERR ,DMA 1 backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DMA0_BW_FATAL_ERR ,DMA 0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_BW_UNC_ERR ,DMA 0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,APB control signals(pwrite,psel,penable) parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PADDR_UNCOR_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error" "0,1"
|
|
group ad:0xF0F80428++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,fusa uncorrectable error interrupt signal enable"
|
|
bitfld.long 0x00 14. " SRAM_RDATA_FATAL_ERR ,SRAM rdata fatal error." "0,1"
|
|
bitfld.long 0x00 13. " SRAM_RDATA_UNC_ERR ,SRAM rdata uncorrctable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,dma 1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA0_EOBC_ERR ,dma 0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "DMA1_EOBA_ERR ,dma 1 eoba error" "0,1"
|
|
bitfld.long 0x00 9. " DMA0_EOBA_ERR ,dma 0 eoba error" "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_FATAL_ERR ,DMA 1 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 7. " DMA1_BW_UNC_ERR ,DMA 1 backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DMA0_BW_FATAL_ERR ,DMA 0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_BW_UNC_ERR ,DMA 0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,APB control signals(pwrite,psel,penable) parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PADDR_UNCOR_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error" "0,1"
|
|
group ad:0xF0F80430++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF0F80434++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF0F80438++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
group ad:0xF0F8043C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0F80450++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,SRAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF0F80454++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0F80458++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,SRAM rdata monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF0F8045C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,SRAM rdata ECC monitorerror injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0F80460++0x03
|
|
line.long 0x00 "SADC_CONV_RCHT_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,{TS[11:0], 1'b0, AMSEL[6:0], SAROUT[11:0]}"
|
|
group ad:0xF0F80464++0x03
|
|
line.long 0x00 "SADC_CONV_RCHT_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,{20'h0, TS[23:12]}"
|
|
group ad:0xF0F80468++0x03
|
|
line.long 0x00 "SADC_CONV_RC0_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F8046C++0x03
|
|
line.long 0x00 "SADC_CONV_RC0_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F80470++0x03
|
|
line.long 0x00 "SADC_CONV_RC1_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F80474++0x03
|
|
line.long 0x00 "SADC_CONV_RC1_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F80478++0x03
|
|
line.long 0x00 "SADC_CONV_RC2_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F8047C++0x03
|
|
line.long 0x00 "SADC_CONV_RC2_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F80480++0x03
|
|
line.long 0x00 "SADC_CONV_RC3_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F80484++0x03
|
|
line.long 0x00 "SADC_CONV_RC3_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F80488++0x03
|
|
line.long 0x00 "ATE_TEST,ATE test mode select"
|
|
bitfld.long 0x00 0. " EN ,ate test enable" "0,1"
|
|
group ad:0xF0F8048C++0x03
|
|
line.long 0x00 "ATE_TEST_CFG,ATE test configuration reg"
|
|
bitfld.long 0x00 24.--26. " EXT_AMSEL ,EXT_AMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " SAMCTRL ,SAMCTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " CCN ,CCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CCP ,CCP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--10. 1. "INSEL ,INSEL"
|
|
bitfld.long 0x00 2. " SDSEL ,SDSEL" "0,1"
|
|
bitfld.long 0x00 1. " REFSEL ,REFSEL" "0,1"
|
|
bitfld.long 0x00 0. " DCOC_EN ,DCOC_EN" "0,1"
|
|
group ad:0xF0F80490++0x03
|
|
line.long 0x00 "SADC_DBG_REG_CTRL,sadc debug control register"
|
|
bitfld.long 0x00 1. " CLEAR ,clear debug data. auto clear" "0,1"
|
|
bitfld.long 0x00 0. " LOCK ,lock debug data" "0,1"
|
|
group ad:0xF0F80494++0x03
|
|
line.long 0x00 "SADC_DBG_REG_0,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " HTC_ACK_CNT ,send ack number"
|
|
group ad:0xF0F80498++0x03
|
|
line.long 0x00 "SADC_DBG_REG_1,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " HTC_CNT ,receive hardware trigger number"
|
|
group ad:0xF0F8049C++0x03
|
|
line.long 0x00 "SADC_DBG_REG_2,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " SOC_CNT ,send soc counter"
|
|
group ad:0xF0F804A0++0x03
|
|
line.long 0x00 "SADC_DBG_REG_3,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC0_REC_CNT ,rc0 receive A_ADC data"
|
|
group ad:0xF0F804A4++0x03
|
|
line.long 0x00 "SADC_DBG_REG_4,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC1_REC_CNT ,rc1 receive A_ADC data"
|
|
group ad:0xF0F804A8++0x03
|
|
line.long 0x00 "SADC_DBG_REG_5,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC2_REC_CNT ,rc2 receive A_ADC data"
|
|
group ad:0xF0F804AC++0x03
|
|
line.long 0x00 "SADC_DBG_REG_6,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC3_REC_CNT ,rc3 receive A_ADC data"
|
|
group ad:0xF0F804B0++0x03
|
|
line.long 0x00 "SADC_DBG_REG_7,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RCHT_REC_CNT ,rcht receive A_ADC data"
|
|
group ad:0xF0F804B4++0x03
|
|
line.long 0x00 "SADC_DBG_REG_8,sadc debug register"
|
|
hexmask.long.byte 0x00 0.--5. 1. " SLOT_CNT ,sync mode slot counter"
|
|
group ad:0xF0F804B8++0x03
|
|
line.long 0x00 "SADC_DBG_REG_9,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " TOTAL_REC_CNT ,total receive A_ADC data"
|
|
tree.end
|
|
tree "ADC3"
|
|
width 28.
|
|
group ad:0xF0F90000++0x03
|
|
line.long 0x00 "SADC_SOFT_RST,SADC soft reset"
|
|
bitfld.long 0x00 5. " RC3_TMR_RST ,rc3 timer soft reset" "0,1"
|
|
bitfld.long 0x00 4. " RC2_TMR_RST ,rc2 timer soft reset" "0,1"
|
|
bitfld.long 0x00 3. " RC1_TMR_RST ,rc1 timer soft reset" "0,1"
|
|
bitfld.long 0x00 2. " RC0_TMR_RST ,rc0 timer soft reset" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "ANA_RST ,analog soft reset default reset analog macro, need software change to 1 when start to work" "0,1"
|
|
bitfld.long 0x00 0. " DIG_RST ,DIgital soft reset" "0,1"
|
|
group ad:0xF0F90004++0x03
|
|
line.long 0x00 "SADC_INIT,SADC init configuration"
|
|
bitfld.long 0x00 24. " DONE ,sadc initial done status" "0,1"
|
|
bitfld.long 0x00 20. " START ,sadc initial start reg. auto clear" "0,1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,sadc initial start value"
|
|
group ad:0xF0F90008++0x03
|
|
line.long 0x00 "SADC_DCOC,SADC dcoc configuration"
|
|
bitfld.long 0x00 31. " DONE ,dcoc done signal" "0,1"
|
|
hexmask.long.word 0x00 16.--28. 1. " VALUE ,bit28: sign bit. bit27~16 : dc offset value"
|
|
bitfld.long 0x00 8. " SOFT_OVWR_EN ,software overwrite dc offset value. auto clear" "0,1"
|
|
bitfld.long 0x00 4. " EN ,1: the ADC result will minus dcoc result. 0: use default value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "START ,1:start to calculate dcoc. auto clear after calculation done" "0,1"
|
|
bitfld.long 0x00 0.--2. " TIMES ,dcoc average calculation times. 0: 1 1: 2 2: 4 3: 8 4:16 5:32 6:64 7:128" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F9000C++0x03
|
|
line.long 0x00 "SADC_HTC,SADC htc register"
|
|
bitfld.long 0x00 31. " READY ,when init or dcoc, SADC can not accept hardware trigger outside. Software read init done and dcoc done, config this reg to 1" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " READY_LEN ,for scheduler sync mode, htc ready length when next slot is RCHT"
|
|
bitfld.long 0x00 0.--3. " DONE_LEN ,htc done length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F90010++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_0,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90014++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_1,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90018++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_2,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F9001C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_3,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90020++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_4,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90024++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_5,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90028++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_6,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F9002C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_7,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90030++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_8,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90034++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_9,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90038++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_10,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F9003C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_11,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90040++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_12,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90044++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_13,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90048++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_14,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F9004C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_15,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90050++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_16,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90054++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_17,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90058++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_18,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F9005C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_19,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90060++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_20,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90064++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_21,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90068++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_22,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F9006C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_23,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90070++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_24,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90074++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_25,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90078++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_26,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F9007C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_27,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90080++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_28,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90084++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_29,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90088++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_30,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F9008C++0x03
|
|
line.long 0x00 "SADC_RCHT_ENTRY_31,SADC RCHT config reg"
|
|
bitfld.long 0x00 24.--26. " REPEAT_TIMES ,SADC repeat times. The total transfer times: 3'b000 -> 1 trans 3'b001 -> 2 trans 3'b010 -> 4 trans 3'b011 -> 8trans 3'b100 -> 16trans others: 1trans if REPEAT_TIME>0, REPEAT_MODE must set to 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,RCHT analog mux selector"
|
|
group ad:0xF0F90090++0x03
|
|
line.long 0x00 "SADC_RC0_TIMER,RC0 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER compare value"
|
|
group ad:0xF0F90094++0x03
|
|
line.long 0x00 "SADC_RC1_TIMER,RC1 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER compare value"
|
|
group ad:0xF0F90098++0x03
|
|
line.long 0x00 "SADC_RC2_TIMER,RC2 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER compare value"
|
|
group ad:0xF0F9009C++0x03
|
|
line.long 0x00 "SADC_RC3_TIMER,RC3 timer value"
|
|
hexmask.long.word 0x00 16.--31. 1. " TMN_VALUE ,SADC TIMER terminal value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_VALUE ,SADC TIMER counter value"
|
|
group ad:0xF0F900A0++0x03
|
|
line.long 0x00 "SADC_RC0,SADC RC0 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F900A4++0x03
|
|
line.long 0x00 "SADC_RC1,SADC RC1 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group ad:0xF0F900A8++0x03
|
|
line.long 0x00 "SADC_RC2,SADC RC2 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F900AC++0x03
|
|
line.long 0x00 "SADC_RC3,SADC RC3 parameter config"
|
|
bitfld.long 0x00 17. " TRG_EN ,SADC RC trigger enable" "0,1"
|
|
bitfld.long 0x00 16. " SOFT_OVWR_POINT_EN ,software overwrite pointer. auto clear." "0,1"
|
|
bitfld.long 0x00 15. " SOFT_TRG ,SADC RC soft trigger. write 1 auto clear." "0,1"
|
|
bitfld.long 0x00 14. " TRG_MODE ,SADC RC trigger mode. 1: software trigger mode. 0:hardware trigger mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TMR_MODE ,SADC RC timer mode. 1:slave mode 0: master mode(independent)" "0,1"
|
|
bitfld.long 0x00 12. " TRG_START ,SADC RC trigger timer start for IT mode" "0,1"
|
|
bitfld.long 0x00 8.--11. " QEND ,SADC RC loop end index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QSTART ,SADC RC loop start index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "CUR_POINTER ,SADC RC current pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F900B0++0x03
|
|
line.long 0x00 "SADC_INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 24. " MNT_EVT_CONT ,continuous monitor event" "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 12. " TS_OVF ,Scheduler time stamp overflow" "0,1"
|
|
bitfld.long 0x00 11. " WATER_MARK_SUB_3 ,SUB-FIFO3 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 10. " WATER_MARK_SUB_2 ,SUB-FIFO2 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "WATER_MARK_SUB_1 ,SUB-FIFO1 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 8. " WATER_MARK_SUB_0 ,SUB-FIFO0 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 4. " END_COV_RCHT ,rcht end of each conversion" "0,1"
|
|
bitfld.long 0x00 3. " END_COV_RC0 ,rc0 end of each conversion" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "END_COV_RC1 ,rc1 end of each conversion" "0,1"
|
|
bitfld.long 0x00 1. " END_COV_RC2 ,rc2 end of each conversion" "0,1"
|
|
bitfld.long 0x00 0. " END_COV_RC3 ,rc3 end of each conversion" "0,1"
|
|
group ad:0xF0F900B4++0x03
|
|
line.long 0x00 "SADC_INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 24. " MNT_EVT_CONT ,continuous monitor event" "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 12. " TS_OVF ,Scheduler time stamp overflow" "0,1"
|
|
bitfld.long 0x00 11. " WATER_MARK_SUB_3 ,SUB-FIFO3 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 10. " WATER_MARK_SUB_2 ,SUB-FIFO2 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "WATER_MARK_SUB_1 ,SUB-FIFO1 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 8. " WATER_MARK_SUB_0 ,SUB-FIFO0 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 4. " END_COV_RCHT ,rcht end of each conversion" "0,1"
|
|
bitfld.long 0x00 3. " END_COV_RC0 ,rc0 end of each conversion" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "END_COV_RC1 ,rc1 end of each conversion" "0,1"
|
|
bitfld.long 0x00 1. " END_COV_RC2 ,rc2 end of each conversion" "0,1"
|
|
bitfld.long 0x00 0. " END_COV_RC3 ,rc3 end of each conversion" "0,1"
|
|
group ad:0xF0F900B8++0x03
|
|
line.long 0x00 "SADC_INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 24. " MNT_EVT_CONT ,continuous monitor event" "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 12. " TS_OVF ,Scheduler time stamp overflow" "0,1"
|
|
bitfld.long 0x00 11. " WATER_MARK_SUB_3 ,SUB-FIFO3 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 10. " WATER_MARK_SUB_2 ,SUB-FIFO2 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "WATER_MARK_SUB_1 ,SUB-FIFO1 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 8. " WATER_MARK_SUB_0 ,SUB-FIFO0 get Water mark of sub-FIFO reaches a preconfigured level" "0,1"
|
|
bitfld.long 0x00 4. " END_COV_RCHT ,rcht end of each conversion" "0,1"
|
|
bitfld.long 0x00 3. " END_COV_RC0 ,rc0 end of each conversion" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "END_COV_RC1 ,rc1 end of each conversion" "0,1"
|
|
bitfld.long 0x00 1. " END_COV_RC2 ,rc2 end of each conversion" "0,1"
|
|
bitfld.long 0x00 0. " END_COV_RC3 ,rc3 end of each conversion" "0,1"
|
|
group ad:0xF0F900C0++0x03
|
|
line.long 0x00 "SADC_COR_ERR_INT_STA,Correctable error interrupt status register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
group ad:0xF0F900C4++0x03
|
|
line.long 0x00 "SADC_COR_ERR_INT_STA_EN,Correctable error interrupt status enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
group ad:0xF0F900C8++0x03
|
|
line.long 0x00 "SADC_COR_ERR_INT_SIG_EN,Correctable error interrupt signal enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
group ad:0xF0F900D0++0x03
|
|
line.long 0x00 "SADC_UNC_ERR_INT_STA,Uncorrectable error interrupt status register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 0. " ANA_EXT_MUX_ERR ,analog external mux error" "0,1"
|
|
group ad:0xF0F900D4++0x03
|
|
line.long 0x00 "SADC_UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 0. " ANA_EXT_MUX_ERR ,analog external mux error" "0,1"
|
|
group ad:0xF0F900D8++0x03
|
|
line.long 0x00 "SADC_UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt signal enable register."
|
|
bitfld.long 0x00 31. " SUB3_OVF ,sub-fifo 3 overflow" "0,1"
|
|
bitfld.long 0x00 30. " SUB2_OVF ,sub-fifo 2 overflow" "0,1"
|
|
bitfld.long 0x00 29. " SUB1_OVF ,sub-fifo 1 overflow" "0,1"
|
|
bitfld.long 0x00 28. " SUB0_OVF ,sub-fifo 0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "MNT_EVT_CONT ,continuous monitor event." "0,1"
|
|
bitfld.long 0x00 23. " MNT_EVT_SINGLE_7 ,single 7 monitor event" "0,1"
|
|
bitfld.long 0x00 22. " MNT_EVT_SINGLE_6 ,single 6 monitor event" "0,1"
|
|
bitfld.long 0x00 21. " MNT_EVT_SINGLE_5 ,single 5 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. "MNT_EVT_SINGLE_4 ,single 4 monitor event" "0,1"
|
|
bitfld.long 0x00 19. " MNT_EVT_SINGLE_3 ,single 3 monitor event" "0,1"
|
|
bitfld.long 0x00 18. " MNT_EVT_SINGLE_2 ,single 2 monitor event" "0,1"
|
|
bitfld.long 0x00 17. " MNT_EVT_SINGLE_1 ,single 1 monitor event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "MNT_EVT_SINGLE_0 ,single 0 monitor event" "0,1"
|
|
bitfld.long 0x00 0. " ANA_EXT_MUX_ERR ,analog external mux error" "0,1"
|
|
group ad:0xF0F900E0++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 4.--6. " DMA1 ,Data error injection for DMA1 channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DMA0 ,Data error injection for DMA0 channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F900E4++0x03
|
|
line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 4.--7. " DMA1 ,Code error injection for DMA 1 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMA0 ,Code error injection for DMA 0 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F900E8++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 4.--7. " DMA1 ,Data error injection for DMA1 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMA0 ,Data error injection for DMA0 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F900EC++0x03
|
|
line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
|
bitfld.long 0x00 4.--7. " DMA1 ,Code error injection for DMA 1 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMA0 ,Code error injection for DMA 0 channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F900F0++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 2. " UNC ,uncorrectable error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR ,correctable error injection" "0,1"
|
|
bitfld.long 0x00 0. " FUNC ,function error injection" "0,1"
|
|
group ad:0xF0F90100++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_0,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector [8:6] for analog mux sel. for DIff mode: [5:3] = p [2:0] = n, for single mode: [3]: 1 -> P/ 0 ->N [2:0] control channel"
|
|
group ad:0xF0F90104++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_1,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90108++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_2,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9010C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_3,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90110++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_4,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90114++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_5,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90118++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_6,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9011C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_7,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90120++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_8,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90124++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_9,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90128++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_10,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9012C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_11,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90130++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_12,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90134++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_13,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90138++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_14,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9013C++0x03
|
|
line.long 0x00 "SADC_RC0_ENTRY_15,SADC RC0 config reg."
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times transfer times = REPEAT_TIME + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode 1: same configuration transfer REPEAT_TIMES to analog SADC by one trigger. 0: same configuration transfer once to analog SADC and next trigger will transfer the same configuration, and this process is .." "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90140++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_0,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90144++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_1,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90148++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_2,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9014C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_3,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90150++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_4,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90154++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_5,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90158++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_6,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9015C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_7,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90160++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_8,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90164++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_9,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90168++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_10,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9016C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_11,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90170++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_12,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90174++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_13,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90178++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_14,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9017C++0x03
|
|
line.long 0x00 "SADC_RC1_ENTRY_15,SADC RC1 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90180++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_0,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90184++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_1,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90188++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_2,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9018C++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_3,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90190++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_4,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90194++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_5,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90198++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_6,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F9019C++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_7,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901A0++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_8,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901A4++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_9,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901A8++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_10,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901AC++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_11,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901B0++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_12,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901B4++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_13,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901B8++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_14,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901BC++0x03
|
|
line.long 0x00 "SADC_RC2_ENTRY_15,SADC RC2 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901C0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_0,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901C4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_1,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901C8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_2,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901CC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_3,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901D0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_4,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901D4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_5,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901D8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_6,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901DC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_7,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901E0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_8,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901E4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_9,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901E8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_10,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901EC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_11,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901F0++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_12,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901F4++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_13,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901F8++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_14,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F901FC++0x03
|
|
line.long 0x00 "SADC_RC3_ENTRY_15,SADC RC3 config reg"
|
|
bitfld.long 0x00 24.--27. " REPEAT_TIMES ,SADC repeat times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " REPEAT_MODE ,SADC repeat mode" "0,1"
|
|
bitfld.long 0x00 12.--15. " CSEL ,SADC config selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog mux selector"
|
|
group ad:0xF0F90200++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART1,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_7 ,slot7 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_6 ,slot6 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_5 ,slot5 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_4 ,slot4 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_3 ,slot3 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_2 ,slot2 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_1 ,slot1 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_0 ,slot0 cid 3'h0: rc0 3'h1: rc1 3'h2: rc2 3'h3: rc3 3'h4: rcht 3'h5: merge previous slot. 3'h6: empty, slot interval = slot_int reg 3'h7: move to next non-empty slot after one cycle don't set 4 before 7" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90204++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART2,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_15 ,slot15 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_14 ,slot14 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_13 ,slot13 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_12 ,slot12 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_11 ,slot11 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_10 ,slot10 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_9 ,slot9 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_8 ,slot8 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90208++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART3,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_23 ,slot23 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_22 ,slot22 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_21 ,slot21 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_20 ,slot20 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_19 ,slot18 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_18 ,slot19 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_17 ,slot17 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_16 ,slot16 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F9020C++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART4,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_31 ,slot31 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_30 ,slot30 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_29 ,slot29 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_28 ,slot28 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_27 ,slot27 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_26 ,slot26 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_25 ,slot25 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_24 ,slot24 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90210++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART5,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_39 ,slot39 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_38 ,slot38 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_37 ,slot37 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_36 ,slot36 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_35 ,slot35 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_34 ,slot34 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_33 ,slot33 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_32 ,slot32 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90214++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART6,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_47 ,slot47 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_46 ,slot46 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_45 ,slot45 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_44 ,slot44 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_43 ,slot43 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_42 ,slot42 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_41 ,slot41 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_40 ,slot40 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90218++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART7,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_55 ,slot55 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_54 ,slot54 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_53 ,slot53 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_52 ,slot52 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_51 ,slot51 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_50 ,slot50 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_49 ,slot49 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_48 ,slot48 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F9021C++0x03
|
|
line.long 0x00 "SADC_SCH_CID_PART8,SADC scheduler CID"
|
|
bitfld.long 0x00 28.--30. " CID_63 ,slot63 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " CID_62 ,slot62 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " CID_61 ,slo61 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CID_60 ,slot60 cid" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. "CID_59 ,slot59 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CID_58 ,slot58 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " CID_57 ,slot57 cid" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CID_56 ,slot56 cid" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90220++0x03
|
|
line.long 0x00 "SADC_TS_VALUE,sadc time stamp value"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,time stamp terminal value"
|
|
group ad:0xF0F90224++0x03
|
|
line.long 0x00 "SADC_SCH_TIMEOUT,sadc schedule slot timeout reg"
|
|
hexmask.long.word 0x00 0.--15. 1. " THRD ,slot length depend on analog out_en mode, the timeout threshold for waiting next trigger this counter is based on ctrl_clk, the threshold must consider analog clock devider"
|
|
group ad:0xF0F90230++0x03
|
|
line.long 0x00 "SADC_SCH_CFG,SADC scheduler configuration"
|
|
bitfld.long 0x00 31. " TS_RST ,1:timestamp soft reset" "0,1"
|
|
bitfld.long 0x00 30. " TS_VLD ,1: timestamp can work 0: timestamp keep current value" "0,1"
|
|
bitfld.long 0x00 28. " RST_DONE ,scheduler reset done flag" "0,1"
|
|
bitfld.long 0x00 25. " SLOT_RST ,1: time slot rotation pointer reset to 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "SLOT_HALT ,1: time slot rotation halt (config if you moDIfy entry configurations)" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLV_DLY ,scheduler slave delay value after EXT_SYNC_I"
|
|
bitfld.long 0x00 12. " ASYNC_STALL ,for async mode, if set to 1, ext_sync_o will send 1 to slave, and all adc will stop senDIng soc to analog" "0,1"
|
|
bitfld.long 0x00 11. " ROT_EN ,1:scheduler sync mode rotation enable 0:scheduler sync mode rotation DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "SYNC_MODE ,1:scheduler is sync mode. 0: scheduler is async mode" "0,1"
|
|
bitfld.long 0x00 9. " MST_MODE ,1:scheduler is master when multi-ADC 0:scheduler is slave when multi-ADC" "0,1"
|
|
bitfld.long 0x00 8. " SLOT_MODE ,1:scheduler slot interval is constant. 0: slot interval depends on ADC conversion time (the feedback 'OUTEN' from analog)" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_INTERVAL ,scheduler interval for each slot is constant"
|
|
group ad:0xF0F90234++0x03
|
|
line.long 0x00 "SADC_SCH_PRIO,SADC scheduler async mode priority(unused)"
|
|
bitfld.long 0x00 16.--18. " RC3 ,RC3 priority (5th)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " RC2 ,RC2 priority (4th)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " RC1 ,RC1 priority (third)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " RC0 ,RC0 priority (second)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "RCHT ,RCHT priority (first)" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90238++0x03
|
|
line.long 0x00 "SADC_CLK_CTRL,SADC clock control"
|
|
bitfld.long 0x00 12.--15. " REF_LOW ,clock low period of the reference clock (ctrl_clk)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " REF_HIGH ,clock high period of the reference clock (ctrl_clk)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " DIV_BYPASS ,1:analog clock DIvider bypass, use control clock DIrectly" "0,1"
|
|
group ad:0xF0F90240++0x03
|
|
line.long 0x00 "SADC_ANA_REF_PART1,SADC analog reference configuration part1"
|
|
hexmask.long.word 0x00 16.--31. 1. " PDC ,safety feature control, ADC negative input switch"
|
|
bitfld.long 0x00 1. " PDBIAS ,BIAS power down" "0,1"
|
|
bitfld.long 0x00 0. " PD ,SAR analog part power down" "0,1"
|
|
group ad:0xF0F90244++0x03
|
|
line.long 0x00 "SADC_ANA_REF_PART2,SADC analog reference configuration part2"
|
|
hexmask.long.word 0x00 16.--31. 1. " MCN ,safety feature control"
|
|
hexmask.long.word 0x00 0.--15. 1. " MCP ,safety feature control"
|
|
group ad:0xF0F90248++0x03
|
|
line.long 0x00 "SADC_CONT_MODE,SADC continuous mode"
|
|
bitfld.long 0x00 31. " SOC ,continuous mode soc" "0,1"
|
|
bitfld.long 0x00 21.--23. " SAMCTRL ,ADC sample time control Please set to 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing . Please set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control Please set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. "CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On Please set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " EN ,1: continuous mode enable" "0,1"
|
|
bitfld.long 0x00 6. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
bitfld.long 0x00 5. " REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. "RC_SEL ,belong to which rc channel. bit4:rcht bit3:rc0 bit2:rc1 bit1:rc2 bit0:rc3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F9024C++0x03
|
|
line.long 0x00 "SADC_CONT_MODE_1,continuous mode part2"
|
|
hexmask.long.word 0x00 0.--8. 1. " AMSEL ,analog amsel"
|
|
group ad:0xF0F90250++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_0,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90254++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_1,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90258++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_2,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F9025C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_3,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90260++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_4,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90264++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_5,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90268++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_6,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F9026C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_7,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90270++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_8,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90274++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_9,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90278++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_10,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F9027C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_11,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90280++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_12,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90284++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_13,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90288++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_14,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F9028C++0x03
|
|
line.long 0x00 "SADC_ANA_PARA_15,SADC analog parameter"
|
|
bitfld.long 0x00 16.--20. " CCT ,timing parameter of conversion check timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " CCN ,safety feature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CCP ,safety feature control, ADC Positive Input: 1'b0: For Each Switch Off 1'b1: For Each Switch On" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " SDSEL ,Single or DIfferential Input Selection: 1: DIfferential Inputs 0: Single-Ended" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "REFSEL ,reference selection 1: Select VREFP2/EQREFP2 0: Select VREFP1/EQREFP1" "0,1"
|
|
bitfld.long 0x00 0.--2. " SAMCTRL ,ADC sample time control" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F90290++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_0,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F90294++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_1,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F90298++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_2,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F9029C++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_3,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F902A0++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_4,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F902A4++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_5,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F902A8++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_6,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F902AC++0x03
|
|
line.long 0x00 "SADC_MNT_SINGLE_7,SADC monitor mask single channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} 1: mask this bit"
|
|
group ad:0xF0F902B0++0x03
|
|
line.long 0x00 "SADC_MNT_CONT,SADC monitor mask continuous channel"
|
|
hexmask.long.word 0x00 16.--28. 1. " MATCH ,the selected {amsel,csel} need matched value"
|
|
hexmask.long.word 0x00 0.--12. 1. " MASK ,config select mask for {amsel, csel} for continuous monitor"
|
|
group ad:0xF0F902B4++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_0,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F902B8++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_1,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F902BC++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_2,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F902C0++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_3,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F902C4++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_4,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F902C8++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_5,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F902CC++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_6,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F902D0++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_SINGLE_7,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F902D4++0x03
|
|
line.long 0x00 "SADC_MNT_THRD_CONT,SADC monitor threshold"
|
|
bitfld.long 0x00 28.--29. " MODE ,2'b11: reserved 2'b10: between high level threshold and low level threshold 2'b01: under low level threshold 2'b00: over high level threshold" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " LTHRD ,low level threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " HTHRD ,high level threshold"
|
|
group ad:0xF0F902E0++0x03
|
|
line.long 0x00 "SADC_MNT_CONT_CFG,SADC monitor continuous configuration"
|
|
hexmask.long.byte 0x00 16.--21. 1. " CONT_THRD ,continuous counter threshold"
|
|
bitfld.long 0x00 0. " CONT_MODE ,1:Reset immeDIately when the result does not hit the trigger conDItion 0:Increase on trigger conDItion hit and decrease on trigger conDItion does not hit" "0,1"
|
|
group ad:0xF0F902E4++0x03
|
|
line.long 0x00 "SADC_FIFO_CFG,SADC fifo control configuration"
|
|
bitfld.long 0x00 8. " PACK16_AMSEL_EN ,for pack 16 mode 1: { amsel[3:0] ,sarout[11:0]} 0: {4'h0, sarout[11:0]}" "0,1"
|
|
bitfld.long 0x00 4. " BYPASS ,1:bypass fifo" "0,1"
|
|
bitfld.long 0x00 0.--1. " PACK_MODE ,2'b11: reserved 2'b10: 64bit 2'b01: 32bit 2'b00: 16bit" "0,1,2,3"
|
|
group ad:0xF0F902E8++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_0,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F902EC++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_1,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F902F0++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_2,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F902F4++0x03
|
|
line.long 0x00 "SADC_SUB_FIFO_3,SADC sub-fifo control"
|
|
bitfld.long 0x00 25. " FULL ,full flag" "0,1"
|
|
bitfld.long 0x00 24. " EMPTY ,empty flag" "0,1"
|
|
bitfld.long 0x00 16.--20. " SUB_RC_EN ,{ RCHT, RC0, RC1, RC2, RC3}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SUB_THRD ,sub fifo water mark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "SUB_START ,sub fifo start address"
|
|
group ad:0xF0F902F8++0x03
|
|
line.long 0x00 "SADC_DMA,SADC dma configuration"
|
|
bitfld.long 0x00 16.--20. " CHN1_EN ,for DMA channel 1 bit20: rcht enable bit19: sub-fifo 0/ rc0 enable bit18: sub-fifo 1/rc1 enable bit17: sub-fifo 2/rc2 enable bit16: sub-fifo 3/rc3 enable valid bit must <= 1 , valid bits > 1 will cause error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " CHN0_EN ,for DMA channel 0 bit12: rcht enable bit11: sub-fifo 0/ rc0 enable bit10: sub-fifo 1/rc1 enable bit9: sub-fifo 2/rc2 enable bit8: sub-fifo 3/rc3 enable valid bit must <= 1 , valid bits > 1 will cause error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MODE ,bit4: 0:rcht conversion done bit3: 1:sub-fifo0 almost full 0: rc0 conversion done bit2: 1:sub-fifo1 almost full 0: rc1 conversion done bit1: 1:sub-fifo2 almost full 0: rc2 conversion done bit0: 1:sub-fifo3 almost full 0: rc3 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F90400++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,parity error status register bit"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,parity error status register bit" "0,1"
|
|
group ad:0xF0F90404++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,mask enable bit of parity error"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,1: REG_PARITY_ERR_INT_STAT is updated. 0: REG_PARITY_ERR_INT_STAT is not updated" "0,1"
|
|
group ad:0xF0F90408++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,interrupt enable bit of parity error status register bit"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,0: REG_PARITY_ERR_INT_STAT interrupt is DIsabled 1: REG_PARITY_ERR_INT_STAT interrupt is enabled" "0,1"
|
|
group ad:0xF0F90410++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,fusa correctable error interrupt status"
|
|
bitfld.long 0x00 3. " SRAM_RDATA_COR_ERR ,SRAM rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " DMA1_BW_COR_ERR ,DMA 1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_COR_ERR ,DMA 0 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0F90414++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,fusa correctable error interrupt status enable"
|
|
bitfld.long 0x00 3. " SRAM_RDATA_COR_ERR ,SRAM rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " DMA1_BW_COR_ERR ,DMA 1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_COR_ERR ,DMA 0 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0F90418++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,fusa correctable error interrupt signal enable"
|
|
bitfld.long 0x00 3. " SRAM_RDATA_COR_ERR ,SRAM rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " DMA1_BW_COR_ERR ,DMA 1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_COR_ERR ,DMA 0 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0F90420++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,fusa uncorrectable error interrupt status"
|
|
bitfld.long 0x00 14. " SRAM_RDATA_FATAL_ERR ,SRAM rdata fatal error." "0,1"
|
|
bitfld.long 0x00 13. " SRAM_RDATA_UNC_ERR ,SRAM rdata uncorrctable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,dma 1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA0_EOBC_ERR ,dma 0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "DMA1_EOBA_ERR ,dma 1 eoba error" "0,1"
|
|
bitfld.long 0x00 9. " DMA0_EOBA_ERR ,dma 0 eoba error" "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_FATAL_ERR ,DMA 1 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 7. " DMA1_BW_UNC_ERR ,DMA 1 backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DMA0_BW_FATAL_ERR ,DMA 0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_BW_UNC_ERR ,DMA 0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,APB control signals(pwrite,psel,penable) parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PADDR_UNCOR_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error" "0,1"
|
|
group ad:0xF0F90424++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,fusa uncorrectable error interrupt status enable"
|
|
bitfld.long 0x00 14. " SRAM_RDATA_FATAL_ERR ,SRAM rdata fatal error." "0,1"
|
|
bitfld.long 0x00 13. " SRAM_RDATA_UNC_ERR ,SRAM rdata uncorrctable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,dma 1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA0_EOBC_ERR ,dma 0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "DMA1_EOBA_ERR ,dma 1 eoba error" "0,1"
|
|
bitfld.long 0x00 9. " DMA0_EOBA_ERR ,dma 0 eoba error" "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_FATAL_ERR ,DMA 1 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 7. " DMA1_BW_UNC_ERR ,DMA 1 backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DMA0_BW_FATAL_ERR ,DMA 0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_BW_UNC_ERR ,DMA 0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,APB control signals(pwrite,psel,penable) parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PADDR_UNCOR_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error" "0,1"
|
|
group ad:0xF0F90428++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,fusa uncorrectable error interrupt signal enable"
|
|
bitfld.long 0x00 14. " SRAM_RDATA_FATAL_ERR ,SRAM rdata fatal error." "0,1"
|
|
bitfld.long 0x00 13. " SRAM_RDATA_UNC_ERR ,SRAM rdata uncorrctable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,dma 1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA0_EOBC_ERR ,dma 0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "DMA1_EOBA_ERR ,dma 1 eoba error" "0,1"
|
|
bitfld.long 0x00 9. " DMA0_EOBA_ERR ,dma 0 eoba error" "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_FATAL_ERR ,DMA 1 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 7. " DMA1_BW_UNC_ERR ,DMA 1 backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DMA0_BW_FATAL_ERR ,DMA 0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_BW_UNC_ERR ,DMA 0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,APB control signals(pwrite,psel,penable) parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PADDR_UNCOR_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error" "0,1"
|
|
group ad:0xF0F90430++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF0F90434++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF0F90438++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
group ad:0xF0F9043C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0F90450++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,SRAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF0F90454++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0F90458++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,SRAM rdata monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF0F9045C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,SRAM rdata ECC monitorerror injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0F90460++0x03
|
|
line.long 0x00 "SADC_CONV_RCHT_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,{TS[11:0], 1'b0, AMSEL[6:0], SAROUT[11:0]}"
|
|
group ad:0xF0F90464++0x03
|
|
line.long 0x00 "SADC_CONV_RCHT_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,{20'h0, TS[23:12]}"
|
|
group ad:0xF0F90468++0x03
|
|
line.long 0x00 "SADC_CONV_RC0_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F9046C++0x03
|
|
line.long 0x00 "SADC_CONV_RC0_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F90470++0x03
|
|
line.long 0x00 "SADC_CONV_RC1_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F90474++0x03
|
|
line.long 0x00 "SADC_CONV_RC1_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F90478++0x03
|
|
line.long 0x00 "SADC_CONV_RC2_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F9047C++0x03
|
|
line.long 0x00 "SADC_CONV_RC2_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F90480++0x03
|
|
line.long 0x00 "SADC_CONV_RC3_LOW,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F90484++0x03
|
|
line.long 0x00 "SADC_CONV_RC3_HIGH,sadc conversion data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,"
|
|
group ad:0xF0F90488++0x03
|
|
line.long 0x00 "ATE_TEST,ATE test mode select"
|
|
bitfld.long 0x00 0. " EN ,ate test enable" "0,1"
|
|
group ad:0xF0F9048C++0x03
|
|
line.long 0x00 "ATE_TEST_CFG,ATE test configuration reg"
|
|
bitfld.long 0x00 24.--26. " EXT_AMSEL ,EXT_AMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " SAMCTRL ,SAMCTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " CCN ,CCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CCP ,CCP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--10. 1. "INSEL ,INSEL"
|
|
bitfld.long 0x00 2. " SDSEL ,SDSEL" "0,1"
|
|
bitfld.long 0x00 1. " REFSEL ,REFSEL" "0,1"
|
|
bitfld.long 0x00 0. " DCOC_EN ,DCOC_EN" "0,1"
|
|
group ad:0xF0F90490++0x03
|
|
line.long 0x00 "SADC_DBG_REG_CTRL,sadc debug control register"
|
|
bitfld.long 0x00 1. " CLEAR ,clear debug data. auto clear" "0,1"
|
|
bitfld.long 0x00 0. " LOCK ,lock debug data" "0,1"
|
|
group ad:0xF0F90494++0x03
|
|
line.long 0x00 "SADC_DBG_REG_0,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " HTC_ACK_CNT ,send ack number"
|
|
group ad:0xF0F90498++0x03
|
|
line.long 0x00 "SADC_DBG_REG_1,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " HTC_CNT ,receive hardware trigger number"
|
|
group ad:0xF0F9049C++0x03
|
|
line.long 0x00 "SADC_DBG_REG_2,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " SOC_CNT ,send soc counter"
|
|
group ad:0xF0F904A0++0x03
|
|
line.long 0x00 "SADC_DBG_REG_3,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC0_REC_CNT ,rc0 receive A_ADC data"
|
|
group ad:0xF0F904A4++0x03
|
|
line.long 0x00 "SADC_DBG_REG_4,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC1_REC_CNT ,rc1 receive A_ADC data"
|
|
group ad:0xF0F904A8++0x03
|
|
line.long 0x00 "SADC_DBG_REG_5,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC2_REC_CNT ,rc2 receive A_ADC data"
|
|
group ad:0xF0F904AC++0x03
|
|
line.long 0x00 "SADC_DBG_REG_6,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RC3_REC_CNT ,rc3 receive A_ADC data"
|
|
group ad:0xF0F904B0++0x03
|
|
line.long 0x00 "SADC_DBG_REG_7,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " RCHT_REC_CNT ,rcht receive A_ADC data"
|
|
group ad:0xF0F904B4++0x03
|
|
line.long 0x00 "SADC_DBG_REG_8,sadc debug register"
|
|
hexmask.long.byte 0x00 0.--5. 1. " SLOT_CNT ,sync mode slot counter"
|
|
group ad:0xF0F904B8++0x03
|
|
line.long 0x00 "SADC_DBG_REG_9,sadc debug register"
|
|
hexmask.long 0x00 0.--31. 1. " TOTAL_REC_CNT ,total receive A_ADC data"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "BTM"
|
|
tree "BTM1"
|
|
width 28.
|
|
group ad:0xF0420000++0x03
|
|
line.long 0x00 "COM_CTRL,G0 and G1 timer common control register"
|
|
bitfld.long 0x00 5.--6. " HOLD_CAP_CFG_G1 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G1 on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G1 on read operation to counter value of CNT_G1 - 2'b11: Hold register .." "0,1,2,3"
|
|
bitfld.long 0x00 4. " STOP_SYNC ,-When STOP_SYNC is high, it means that stop event of G1 timer are controlled by the G0 timer register configuration. -When STOP_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
|
|
bitfld.long 0x00 3. " FRC_RLD_SYNC ,-When FRC_RLD_SYNC is high, it means that frc_rld_event of G1 timer are controlled by the G0 timer register configuration. -When FRC_RLD_SYNC is low, it means that above events are controlled by G1 timer register .." "0,1"
|
|
bitfld.long 0x00 2. " START_SYNC ,-When START_SYNC is high, it means that start event of G1 timer are controlled by the G0 timer register configuration. -When START_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. "HOLD_CAP_CFG_G0 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G0 value on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G0 on read operation to counter value of CNT_G1 - 2'b11: Hold register.." "0,1,2,3"
|
|
group ad:0xF0420004++0x03
|
|
line.long 0x00 "CNT_G0_EN,G0 timer enbale control register"
|
|
bitfld.long 0x00 1. " STOP ,When this bit is set, the G0 counter is freezed." "0,1"
|
|
bitfld.long 0x00 0. " ENABLE ,When this bit is set, the G0 starts to count up or count down, depenDIng on the CNT_DIR configuration bit. In one -shot mode, this bit will be automatically cleared by the hardware when G0 timer overflows." "0,1"
|
|
group ad:0xF0420008++0x03
|
|
line.long 0x00 "CNT_G0_CFG,G0 timer configure register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value"
|
|
bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G0 timer 1'b1: reset G0 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G0 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
|
|
group ad:0xF042000C++0x03
|
|
line.long 0x00 "CNT_G0_OVF,G0 timer terminal value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,terminal value"
|
|
group ad:0xF0420010++0x03
|
|
line.long 0x00 "CNT_G0_CMP,G0 timer compare value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,compare value"
|
|
group ad:0xF0420014++0x03
|
|
line.long 0x00 "CNT_G0,G0 counter value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,counter value"
|
|
group ad:0xF0420018++0x03
|
|
line.long 0x00 "HOLD_G0,Counter hold register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
|
|
group ad:0xF0420024++0x03
|
|
line.long 0x00 "CNT_G1_EN,G1 timer enbale control register"
|
|
bitfld.long 0x00 1. " STOP ,when this bit set,the G0 counter was freezed" "0,1"
|
|
bitfld.long 0x00 0. " ENABLE ,when this bit set,the G1 start to count up or count down depend on the CNT_DIR configure bit. in one -shot mode ,this bit will be auto cleared by hardware while G0 timer overflow" "0,1"
|
|
group ad:0xF0420028++0x03
|
|
line.long 0x00 "CNT_G1_CFG,G1 timer configure register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval, , after you update the counter interval,you need to write SI_WR_UPD to 1'b1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value, , after you update the increment value,you need to write INC_WR_UPD to 1'b1"
|
|
bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G1 timer 1'b1: reset G1 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G1 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload,this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
|
|
group ad:0xF042002C++0x03
|
|
line.long 0x00 "CNT_G1_OVF,G1 timer terminal value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,terminal value, after you update the terminal value,you need to write OVF_WR_UPD to 1'b1"
|
|
group ad:0xF0420030++0x03
|
|
line.long 0x00 "CNT_G1_CMP,G1 timer compare value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,compare value, after you update the compare value,you need to write CMP_WR_UPD to 1'b1"
|
|
group ad:0xF0420034++0x03
|
|
line.long 0x00 "CNT_G1,G1 counter value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,G1 counter value"
|
|
group ad:0xF0420038++0x03
|
|
line.long 0x00 "CNT_G1_UPD_FLAG,G1 timer configure value update flag"
|
|
bitfld.long 0x00 3. " INC_WR_UPD ,when this bit set,the INC[7:0] will be update to INC shadow register,this bit will be cleared by hardware" "0,1"
|
|
bitfld.long 0x00 2. " SI_WR_UPD ,when this bit set,the SI[7:0] will be update to counter interval shadow register,this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 1. " CMP_WR_UPD ,when this bit set,the compare value will be update to compare shadow register,this bi will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 0. " OVF_WR_UPD ,when this bit set,terminal value will be update to terminal shadow register,this bit will be auto cleared by hardware" "0,1"
|
|
group ad:0xF042003C++0x03
|
|
line.long 0x00 "HOLD_G1,Counter hold register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
|
|
group ad:0xF0420040++0x03
|
|
line.long 0x00 "INT_STAT,Function interrupt status register"
|
|
bitfld.long 0x00 3. " OE_G1 ,CNT_G1 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,CNT_G0 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,CNT_G1 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,CNT_G0 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0420044++0x03
|
|
line.long 0x00 "INT_STAT_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,status enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,status enable" "0,1"
|
|
group ad:0xF0420048++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,signal enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,signal enable" "0,1"
|
|
group ad:0xF042004C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0420050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,status enable" "0,1"
|
|
group ad:0xF0420054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,signal enable" "0,1"
|
|
group ad:0xF0420058++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error occur when transfer from apb clock domain to xtal24m clock domain,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer outputs lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF042005C++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error status enable" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error status enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error status enable" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error status enable" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error status enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error status enable" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error status enable" "0,1"
|
|
group ad:0xF0420060++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error signal enable" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error signal enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error signal enable" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error signal enable" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error signal enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error signal enable" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error signal enable" "0,1"
|
|
group ad:0xF0420064++0x03
|
|
line.long 0x00 "PWDATA,pwdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,error injection on pwdata"
|
|
group ad:0xF0420068++0x03
|
|
line.long 0x00 "PWCODE,pwcode error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INJ ,error injection on pwcode"
|
|
group ad:0xF042006C++0x03
|
|
line.long 0x00 "IRQ_ERR,Interrupt error injection"
|
|
bitfld.long 0x00 2. " FUSA_UNCOR_INJ ,apb bus uncorrectable error, input DIverse redundant compare error or lockstep compare error" "0,1"
|
|
bitfld.long 0x00 1. " FUSA_COR_INJ ,pwdata correctable interruput error injection" "0,1"
|
|
bitfld.long 0x00 0. " INT_INJ ,compare event or overflow event error injection" "0,1"
|
|
group ad:0xF0420070++0x03
|
|
line.long 0x00 "LSP,Lockstep error injection"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INJ_BIT ,select which bit to inject error when compare the outputs of main core and it's copy core"
|
|
bitfld.long 0x00 1.--3. " INJ_SEL ,lockstep error injection select 3'b000: error injection for apb_bus lockstep (total 42bits lockstep compare signal) 3'b001: error injection for g0 timer lockstep(total 35bits lockstep compare signal) 3'b010: error injection .." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " INJ_EN ,lockstep error injection enable" "0,1"
|
|
group ad:0xF0420074++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,selftest mode enable" "0,1"
|
|
tree.end
|
|
tree "BTM2"
|
|
width 28.
|
|
group ad:0xF0430000++0x03
|
|
line.long 0x00 "COM_CTRL,G0 and G1 timer common control register"
|
|
bitfld.long 0x00 5.--6. " HOLD_CAP_CFG_G1 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G1 on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G1 on read operation to counter value of CNT_G1 - 2'b11: Hold register .." "0,1,2,3"
|
|
bitfld.long 0x00 4. " STOP_SYNC ,-When STOP_SYNC is high, it means that stop event of G1 timer are controlled by the G0 timer register configuration. -When STOP_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
|
|
bitfld.long 0x00 3. " FRC_RLD_SYNC ,-When FRC_RLD_SYNC is high, it means that frc_rld_event of G1 timer are controlled by the G0 timer register configuration. -When FRC_RLD_SYNC is low, it means that above events are controlled by G1 timer register .." "0,1"
|
|
bitfld.long 0x00 2. " START_SYNC ,-When START_SYNC is high, it means that start event of G1 timer are controlled by the G0 timer register configuration. -When START_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. "HOLD_CAP_CFG_G0 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G0 value on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G0 on read operation to counter value of CNT_G1 - 2'b11: Hold register.." "0,1,2,3"
|
|
group ad:0xF0430004++0x03
|
|
line.long 0x00 "CNT_G0_EN,G0 timer enbale control register"
|
|
bitfld.long 0x00 1. " STOP ,When this bit is set, the G0 counter is freezed." "0,1"
|
|
bitfld.long 0x00 0. " ENABLE ,When this bit is set, the G0 starts to count up or count down, depenDIng on the CNT_DIR configuration bit. In one -shot mode, this bit will be automatically cleared by the hardware when G0 timer overflows." "0,1"
|
|
group ad:0xF0430008++0x03
|
|
line.long 0x00 "CNT_G0_CFG,G0 timer configure register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value"
|
|
bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G0 timer 1'b1: reset G0 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G0 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
|
|
group ad:0xF043000C++0x03
|
|
line.long 0x00 "CNT_G0_OVF,G0 timer terminal value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,terminal value"
|
|
group ad:0xF0430010++0x03
|
|
line.long 0x00 "CNT_G0_CMP,G0 timer compare value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,compare value"
|
|
group ad:0xF0430014++0x03
|
|
line.long 0x00 "CNT_G0,G0 counter value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,counter value"
|
|
group ad:0xF0430018++0x03
|
|
line.long 0x00 "HOLD_G0,Counter hold register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
|
|
group ad:0xF0430024++0x03
|
|
line.long 0x00 "CNT_G1_EN,G1 timer enbale control register"
|
|
bitfld.long 0x00 1. " STOP ,when this bit set,the G0 counter was freezed" "0,1"
|
|
bitfld.long 0x00 0. " ENABLE ,when this bit set,the G1 start to count up or count down depend on the CNT_DIR configure bit. in one -shot mode ,this bit will be auto cleared by hardware while G0 timer overflow" "0,1"
|
|
group ad:0xF0430028++0x03
|
|
line.long 0x00 "CNT_G1_CFG,G1 timer configure register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval, , after you update the counter interval,you need to write SI_WR_UPD to 1'b1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value, , after you update the increment value,you need to write INC_WR_UPD to 1'b1"
|
|
bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G1 timer 1'b1: reset G1 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G1 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload,this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
|
|
group ad:0xF043002C++0x03
|
|
line.long 0x00 "CNT_G1_OVF,G1 timer terminal value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,terminal value, after you update the terminal value,you need to write OVF_WR_UPD to 1'b1"
|
|
group ad:0xF0430030++0x03
|
|
line.long 0x00 "CNT_G1_CMP,G1 timer compare value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,compare value, after you update the compare value,you need to write CMP_WR_UPD to 1'b1"
|
|
group ad:0xF0430034++0x03
|
|
line.long 0x00 "CNT_G1,G1 counter value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,G1 counter value"
|
|
group ad:0xF0430038++0x03
|
|
line.long 0x00 "CNT_G1_UPD_FLAG,G1 timer configure value update flag"
|
|
bitfld.long 0x00 3. " INC_WR_UPD ,when this bit set,the INC[7:0] will be update to INC shadow register,this bit will be cleared by hardware" "0,1"
|
|
bitfld.long 0x00 2. " SI_WR_UPD ,when this bit set,the SI[7:0] will be update to counter interval shadow register,this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 1. " CMP_WR_UPD ,when this bit set,the compare value will be update to compare shadow register,this bi will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 0. " OVF_WR_UPD ,when this bit set,terminal value will be update to terminal shadow register,this bit will be auto cleared by hardware" "0,1"
|
|
group ad:0xF043003C++0x03
|
|
line.long 0x00 "HOLD_G1,Counter hold register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
|
|
group ad:0xF0430040++0x03
|
|
line.long 0x00 "INT_STAT,Function interrupt status register"
|
|
bitfld.long 0x00 3. " OE_G1 ,CNT_G1 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,CNT_G0 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,CNT_G1 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,CNT_G0 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0430044++0x03
|
|
line.long 0x00 "INT_STAT_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,status enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,status enable" "0,1"
|
|
group ad:0xF0430048++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,signal enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,signal enable" "0,1"
|
|
group ad:0xF043004C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0430050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,status enable" "0,1"
|
|
group ad:0xF0430054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,signal enable" "0,1"
|
|
group ad:0xF0430058++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error occur when transfer from apb clock domain to xtal24m clock domain,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error occur,and you can write 1 to clear it" "0,1"
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|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
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bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer outputs lockstep compare error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
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bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error occur,and you can write 1 to clear it" "0,1"
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|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error occur,and you can write 1 to clear it" "0,1"
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|
textline " "
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error occur,and you can write 1 to clear it" "0,1"
|
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bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error occur,and you can write 1 to clear it" "0,1"
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group ad:0xF043005C++0x03
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line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,Function safety uncorrectable error interrupt status enable register"
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bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error status enable" "0,1"
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bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error status enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
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bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error status enable" "0,1"
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bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error status enable" "0,1"
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|
textline " "
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bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error status enable" "0,1"
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bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error status enable" "0,1"
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bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error status enable" "0,1"
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bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error status enable" "0,1"
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textline " "
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bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error status enable" "0,1"
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bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error status enable" "0,1"
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bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error status enable" "0,1"
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bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error status enable" "0,1"
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textline " "
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error status enable" "0,1"
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bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error status enable" "0,1"
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group ad:0xF0430060++0x03
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line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
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bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error signal enable" "0,1"
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bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error signal enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
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bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error signal enable" "0,1"
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|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error signal enable" "0,1"
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textline " "
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bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error signal enable" "0,1"
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bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error signal enable" "0,1"
|
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bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error signal enable" "0,1"
|
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bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error signal enable" "0,1"
|
|
textline " "
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bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error signal enable" "0,1"
|
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bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error signal enable" "0,1"
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bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error signal enable" "0,1"
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bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error signal enable" "0,1"
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textline " "
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error signal enable" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error signal enable" "0,1"
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group ad:0xF0430064++0x03
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line.long 0x00 "PWDATA,pwdata error injection"
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hexmask.long 0x00 0.--31. 1. " INJ ,error injection on pwdata"
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group ad:0xF0430068++0x03
|
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line.long 0x00 "PWCODE,pwcode error injection"
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hexmask.long.byte 0x00 0.--6. 1. " INJ ,error injection on pwcode"
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group ad:0xF043006C++0x03
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line.long 0x00 "IRQ_ERR,Interrupt error injection"
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bitfld.long 0x00 2. " FUSA_UNCOR_INJ ,apb bus uncorrectable error, input DIverse redundant compare error or lockstep compare error" "0,1"
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bitfld.long 0x00 1. " FUSA_COR_INJ ,pwdata correctable interruput error injection" "0,1"
|
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bitfld.long 0x00 0. " INT_INJ ,compare event or overflow event error injection" "0,1"
|
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group ad:0xF0430070++0x03
|
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line.long 0x00 "LSP,Lockstep error injection"
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hexmask.long.byte 0x00 8.--15. 1. " INJ_BIT ,select which bit to inject error when compare the outputs of main core and it's copy core"
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bitfld.long 0x00 1.--3. " INJ_SEL ,lockstep error injection select 3'b000: error injection for apb_bus lockstep (total 42bits lockstep compare signal) 3'b001: error injection for g0 timer lockstep(total 35bits lockstep compare signal) 3'b010: error injection .." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " INJ_EN ,lockstep error injection enable" "0,1"
|
|
group ad:0xF0430074++0x03
|
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line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
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bitfld.long 0x00 0. " EN ,selftest mode enable" "0,1"
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tree.end
|
|
tree "BTM3"
|
|
width 28.
|
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group ad:0xF0440000++0x03
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line.long 0x00 "COM_CTRL,G0 and G1 timer common control register"
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bitfld.long 0x00 5.--6. " HOLD_CAP_CFG_G1 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G1 on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G1 on read operation to counter value of CNT_G1 - 2'b11: Hold register .." "0,1,2,3"
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bitfld.long 0x00 4. " STOP_SYNC ,-When STOP_SYNC is high, it means that stop event of G1 timer are controlled by the G0 timer register configuration. -When STOP_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
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bitfld.long 0x00 3. " FRC_RLD_SYNC ,-When FRC_RLD_SYNC is high, it means that frc_rld_event of G1 timer are controlled by the G0 timer register configuration. -When FRC_RLD_SYNC is low, it means that above events are controlled by G1 timer register .." "0,1"
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bitfld.long 0x00 2. " START_SYNC ,-When START_SYNC is high, it means that start event of G1 timer are controlled by the G0 timer register configuration. -When START_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
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|
textline " "
|
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bitfld.long 0x00 0.--1. "HOLD_CAP_CFG_G0 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G0 value on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G0 on read operation to counter value of CNT_G1 - 2'b11: Hold register.." "0,1,2,3"
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group ad:0xF0440004++0x03
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line.long 0x00 "CNT_G0_EN,G0 timer enbale control register"
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bitfld.long 0x00 1. " STOP ,When this bit is set, the G0 counter is freezed." "0,1"
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bitfld.long 0x00 0. " ENABLE ,When this bit is set, the G0 starts to count up or count down, depenDIng on the CNT_DIR configuration bit. In one -shot mode, this bit will be automatically cleared by the hardware when G0 timer overflows." "0,1"
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group ad:0xF0440008++0x03
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line.long 0x00 "CNT_G0_CFG,G0 timer configure register"
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hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval"
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hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value"
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bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G0 timer 1'b1: reset G0 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G0 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload this bit will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
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bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
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bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
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textline " "
|
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bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
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group ad:0xF044000C++0x03
|
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line.long 0x00 "CNT_G0_OVF,G0 timer terminal value"
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hexmask.long 0x00 0.--31. 1. " VAL ,terminal value"
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group ad:0xF0440010++0x03
|
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line.long 0x00 "CNT_G0_CMP,G0 timer compare value"
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hexmask.long 0x00 0.--31. 1. " VAL ,compare value"
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group ad:0xF0440014++0x03
|
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line.long 0x00 "CNT_G0,G0 counter value"
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hexmask.long 0x00 0.--31. 1. " VAL ,counter value"
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group ad:0xF0440018++0x03
|
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line.long 0x00 "HOLD_G0,Counter hold register"
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hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
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group ad:0xF0440024++0x03
|
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line.long 0x00 "CNT_G1_EN,G1 timer enbale control register"
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bitfld.long 0x00 1. " STOP ,when this bit set,the G0 counter was freezed" "0,1"
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bitfld.long 0x00 0. " ENABLE ,when this bit set,the G1 start to count up or count down depend on the CNT_DIR configure bit. in one -shot mode ,this bit will be auto cleared by hardware while G0 timer overflow" "0,1"
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group ad:0xF0440028++0x03
|
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line.long 0x00 "CNT_G1_CFG,G1 timer configure register"
|
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hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval, , after you update the counter interval,you need to write SI_WR_UPD to 1'b1"
|
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hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value, , after you update the increment value,you need to write INC_WR_UPD to 1'b1"
|
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bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G1 timer 1'b1: reset G1 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G1 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload,this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
|
|
group ad:0xF044002C++0x03
|
|
line.long 0x00 "CNT_G1_OVF,G1 timer terminal value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,terminal value, after you update the terminal value,you need to write OVF_WR_UPD to 1'b1"
|
|
group ad:0xF0440030++0x03
|
|
line.long 0x00 "CNT_G1_CMP,G1 timer compare value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,compare value, after you update the compare value,you need to write CMP_WR_UPD to 1'b1"
|
|
group ad:0xF0440034++0x03
|
|
line.long 0x00 "CNT_G1,G1 counter value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,G1 counter value"
|
|
group ad:0xF0440038++0x03
|
|
line.long 0x00 "CNT_G1_UPD_FLAG,G1 timer configure value update flag"
|
|
bitfld.long 0x00 3. " INC_WR_UPD ,when this bit set,the INC[7:0] will be update to INC shadow register,this bit will be cleared by hardware" "0,1"
|
|
bitfld.long 0x00 2. " SI_WR_UPD ,when this bit set,the SI[7:0] will be update to counter interval shadow register,this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 1. " CMP_WR_UPD ,when this bit set,the compare value will be update to compare shadow register,this bi will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 0. " OVF_WR_UPD ,when this bit set,terminal value will be update to terminal shadow register,this bit will be auto cleared by hardware" "0,1"
|
|
group ad:0xF044003C++0x03
|
|
line.long 0x00 "HOLD_G1,Counter hold register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
|
|
group ad:0xF0440040++0x03
|
|
line.long 0x00 "INT_STAT,Function interrupt status register"
|
|
bitfld.long 0x00 3. " OE_G1 ,CNT_G1 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,CNT_G0 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,CNT_G1 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,CNT_G0 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0440044++0x03
|
|
line.long 0x00 "INT_STAT_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,status enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,status enable" "0,1"
|
|
group ad:0xF0440048++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,signal enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,signal enable" "0,1"
|
|
group ad:0xF044004C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0440050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,status enable" "0,1"
|
|
group ad:0xF0440054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,signal enable" "0,1"
|
|
group ad:0xF0440058++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error occur when transfer from apb clock domain to xtal24m clock domain,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer outputs lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF044005C++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error status enable" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error status enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error status enable" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error status enable" "0,1"
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|
textline " "
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bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error status enable" "0,1"
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|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error status enable" "0,1"
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|
textline " "
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bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error status enable" "0,1"
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|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error status enable" "0,1"
|
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bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error status enable" "0,1"
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|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error status enable" "0,1"
|
|
textline " "
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error status enable" "0,1"
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bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error status enable" "0,1"
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group ad:0xF0440060++0x03
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line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
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bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error signal enable" "0,1"
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|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error signal enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
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bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error signal enable" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error signal enable" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error signal enable" "0,1"
|
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bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error signal enable" "0,1"
|
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bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error signal enable" "0,1"
|
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bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error signal enable" "0,1"
|
|
textline " "
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bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error signal enable" "0,1"
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bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error signal enable" "0,1"
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bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error signal enable" "0,1"
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bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error signal enable" "0,1"
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|
textline " "
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error signal enable" "0,1"
|
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bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error signal enable" "0,1"
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group ad:0xF0440064++0x03
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line.long 0x00 "PWDATA,pwdata error injection"
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hexmask.long 0x00 0.--31. 1. " INJ ,error injection on pwdata"
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group ad:0xF0440068++0x03
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line.long 0x00 "PWCODE,pwcode error injection"
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hexmask.long.byte 0x00 0.--6. 1. " INJ ,error injection on pwcode"
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group ad:0xF044006C++0x03
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line.long 0x00 "IRQ_ERR,Interrupt error injection"
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bitfld.long 0x00 2. " FUSA_UNCOR_INJ ,apb bus uncorrectable error, input DIverse redundant compare error or lockstep compare error" "0,1"
|
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bitfld.long 0x00 1. " FUSA_COR_INJ ,pwdata correctable interruput error injection" "0,1"
|
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bitfld.long 0x00 0. " INT_INJ ,compare event or overflow event error injection" "0,1"
|
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group ad:0xF0440070++0x03
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line.long 0x00 "LSP,Lockstep error injection"
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hexmask.long.byte 0x00 8.--15. 1. " INJ_BIT ,select which bit to inject error when compare the outputs of main core and it's copy core"
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bitfld.long 0x00 1.--3. " INJ_SEL ,lockstep error injection select 3'b000: error injection for apb_bus lockstep (total 42bits lockstep compare signal) 3'b001: error injection for g0 timer lockstep(total 35bits lockstep compare signal) 3'b010: error injection .." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " INJ_EN ,lockstep error injection enable" "0,1"
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group ad:0xF0440074++0x03
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line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
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bitfld.long 0x00 0. " EN ,selftest mode enable" "0,1"
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tree.end
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tree "BTM4"
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width 28.
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group ad:0xF0450000++0x03
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line.long 0x00 "COM_CTRL,G0 and G1 timer common control register"
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bitfld.long 0x00 5.--6. " HOLD_CAP_CFG_G1 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G1 on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G1 on read operation to counter value of CNT_G1 - 2'b11: Hold register .." "0,1,2,3"
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bitfld.long 0x00 4. " STOP_SYNC ,-When STOP_SYNC is high, it means that stop event of G1 timer are controlled by the G0 timer register configuration. -When STOP_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
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bitfld.long 0x00 3. " FRC_RLD_SYNC ,-When FRC_RLD_SYNC is high, it means that frc_rld_event of G1 timer are controlled by the G0 timer register configuration. -When FRC_RLD_SYNC is low, it means that above events are controlled by G1 timer register .." "0,1"
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bitfld.long 0x00 2. " START_SYNC ,-When START_SYNC is high, it means that start event of G1 timer are controlled by the G0 timer register configuration. -When START_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
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textline " "
|
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bitfld.long 0x00 0.--1. "HOLD_CAP_CFG_G0 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G0 value on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G0 on read operation to counter value of CNT_G1 - 2'b11: Hold register.." "0,1,2,3"
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group ad:0xF0450004++0x03
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line.long 0x00 "CNT_G0_EN,G0 timer enbale control register"
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bitfld.long 0x00 1. " STOP ,When this bit is set, the G0 counter is freezed." "0,1"
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bitfld.long 0x00 0. " ENABLE ,When this bit is set, the G0 starts to count up or count down, depenDIng on the CNT_DIR configuration bit. In one -shot mode, this bit will be automatically cleared by the hardware when G0 timer overflows." "0,1"
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group ad:0xF0450008++0x03
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line.long 0x00 "CNT_G0_CFG,G0 timer configure register"
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hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval"
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hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value"
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bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G0 timer 1'b1: reset G0 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G0 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload this bit will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
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bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
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bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
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textline " "
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bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
|
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group ad:0xF045000C++0x03
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line.long 0x00 "CNT_G0_OVF,G0 timer terminal value"
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hexmask.long 0x00 0.--31. 1. " VAL ,terminal value"
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group ad:0xF0450010++0x03
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line.long 0x00 "CNT_G0_CMP,G0 timer compare value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,compare value"
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group ad:0xF0450014++0x03
|
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line.long 0x00 "CNT_G0,G0 counter value"
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hexmask.long 0x00 0.--31. 1. " VAL ,counter value"
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group ad:0xF0450018++0x03
|
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line.long 0x00 "HOLD_G0,Counter hold register"
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hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
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group ad:0xF0450024++0x03
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line.long 0x00 "CNT_G1_EN,G1 timer enbale control register"
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bitfld.long 0x00 1. " STOP ,when this bit set,the G0 counter was freezed" "0,1"
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bitfld.long 0x00 0. " ENABLE ,when this bit set,the G1 start to count up or count down depend on the CNT_DIR configure bit. in one -shot mode ,this bit will be auto cleared by hardware while G0 timer overflow" "0,1"
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group ad:0xF0450028++0x03
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line.long 0x00 "CNT_G1_CFG,G1 timer configure register"
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hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval, , after you update the counter interval,you need to write SI_WR_UPD to 1'b1"
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hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value, , after you update the increment value,you need to write INC_WR_UPD to 1'b1"
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bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G1 timer 1'b1: reset G1 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
|
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bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G1 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload,this bit will be auto cleared by hardware" "0,1"
|
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bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
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bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
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bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
|
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group ad:0xF045002C++0x03
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line.long 0x00 "CNT_G1_OVF,G1 timer terminal value"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,terminal value, after you update the terminal value,you need to write OVF_WR_UPD to 1'b1"
|
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group ad:0xF0450030++0x03
|
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line.long 0x00 "CNT_G1_CMP,G1 timer compare value"
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hexmask.long 0x00 0.--31. 1. " VAL ,compare value, after you update the compare value,you need to write CMP_WR_UPD to 1'b1"
|
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group ad:0xF0450034++0x03
|
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line.long 0x00 "CNT_G1,G1 counter value"
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hexmask.long 0x00 0.--31. 1. " VAL ,G1 counter value"
|
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group ad:0xF0450038++0x03
|
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line.long 0x00 "CNT_G1_UPD_FLAG,G1 timer configure value update flag"
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bitfld.long 0x00 3. " INC_WR_UPD ,when this bit set,the INC[7:0] will be update to INC shadow register,this bit will be cleared by hardware" "0,1"
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|
bitfld.long 0x00 2. " SI_WR_UPD ,when this bit set,the SI[7:0] will be update to counter interval shadow register,this bit will be auto cleared by hardware" "0,1"
|
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bitfld.long 0x00 1. " CMP_WR_UPD ,when this bit set,the compare value will be update to compare shadow register,this bi will be auto cleared by hardware" "0,1"
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|
bitfld.long 0x00 0. " OVF_WR_UPD ,when this bit set,terminal value will be update to terminal shadow register,this bit will be auto cleared by hardware" "0,1"
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|
group ad:0xF045003C++0x03
|
|
line.long 0x00 "HOLD_G1,Counter hold register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
|
|
group ad:0xF0450040++0x03
|
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line.long 0x00 "INT_STAT,Function interrupt status register"
|
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bitfld.long 0x00 3. " OE_G1 ,CNT_G1 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,CNT_G0 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,CNT_G1 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,CNT_G0 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0450044++0x03
|
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line.long 0x00 "INT_STAT_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,status enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,status enable" "0,1"
|
|
group ad:0xF0450048++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,signal enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,signal enable" "0,1"
|
|
group ad:0xF045004C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0450050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,status enable" "0,1"
|
|
group ad:0xF0450054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,signal enable" "0,1"
|
|
group ad:0xF0450058++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error occur when transfer from apb clock domain to xtal24m clock domain,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer outputs lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF045005C++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error status enable" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error status enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error status enable" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error status enable" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error status enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error status enable" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error status enable" "0,1"
|
|
group ad:0xF0450060++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error signal enable" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error signal enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error signal enable" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error signal enable" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error signal enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error signal enable" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error signal enable" "0,1"
|
|
group ad:0xF0450064++0x03
|
|
line.long 0x00 "PWDATA,pwdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,error injection on pwdata"
|
|
group ad:0xF0450068++0x03
|
|
line.long 0x00 "PWCODE,pwcode error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INJ ,error injection on pwcode"
|
|
group ad:0xF045006C++0x03
|
|
line.long 0x00 "IRQ_ERR,Interrupt error injection"
|
|
bitfld.long 0x00 2. " FUSA_UNCOR_INJ ,apb bus uncorrectable error, input DIverse redundant compare error or lockstep compare error" "0,1"
|
|
bitfld.long 0x00 1. " FUSA_COR_INJ ,pwdata correctable interruput error injection" "0,1"
|
|
bitfld.long 0x00 0. " INT_INJ ,compare event or overflow event error injection" "0,1"
|
|
group ad:0xF0450070++0x03
|
|
line.long 0x00 "LSP,Lockstep error injection"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INJ_BIT ,select which bit to inject error when compare the outputs of main core and it's copy core"
|
|
bitfld.long 0x00 1.--3. " INJ_SEL ,lockstep error injection select 3'b000: error injection for apb_bus lockstep (total 42bits lockstep compare signal) 3'b001: error injection for g0 timer lockstep(total 35bits lockstep compare signal) 3'b010: error injection .." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " INJ_EN ,lockstep error injection enable" "0,1"
|
|
group ad:0xF0450074++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,selftest mode enable" "0,1"
|
|
tree.end
|
|
tree "BTM5"
|
|
width 28.
|
|
group ad:0xF0460000++0x03
|
|
line.long 0x00 "COM_CTRL,G0 and G1 timer common control register"
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|
bitfld.long 0x00 5.--6. " HOLD_CAP_CFG_G1 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G1 on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G1 on read operation to counter value of CNT_G1 - 2'b11: Hold register .." "0,1,2,3"
|
|
bitfld.long 0x00 4. " STOP_SYNC ,-When STOP_SYNC is high, it means that stop event of G1 timer are controlled by the G0 timer register configuration. -When STOP_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
|
|
bitfld.long 0x00 3. " FRC_RLD_SYNC ,-When FRC_RLD_SYNC is high, it means that frc_rld_event of G1 timer are controlled by the G0 timer register configuration. -When FRC_RLD_SYNC is low, it means that above events are controlled by G1 timer register .." "0,1"
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|
bitfld.long 0x00 2. " START_SYNC ,-When START_SYNC is high, it means that start event of G1 timer are controlled by the G0 timer register configuration. -When START_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. "HOLD_CAP_CFG_G0 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G0 value on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G0 on read operation to counter value of CNT_G1 - 2'b11: Hold register.." "0,1,2,3"
|
|
group ad:0xF0460004++0x03
|
|
line.long 0x00 "CNT_G0_EN,G0 timer enbale control register"
|
|
bitfld.long 0x00 1. " STOP ,When this bit is set, the G0 counter is freezed." "0,1"
|
|
bitfld.long 0x00 0. " ENABLE ,When this bit is set, the G0 starts to count up or count down, depenDIng on the CNT_DIR configuration bit. In one -shot mode, this bit will be automatically cleared by the hardware when G0 timer overflows." "0,1"
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|
group ad:0xF0460008++0x03
|
|
line.long 0x00 "CNT_G0_CFG,G0 timer configure register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value"
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|
bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G0 timer 1'b1: reset G0 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G0 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
|
|
group ad:0xF046000C++0x03
|
|
line.long 0x00 "CNT_G0_OVF,G0 timer terminal value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,terminal value"
|
|
group ad:0xF0460010++0x03
|
|
line.long 0x00 "CNT_G0_CMP,G0 timer compare value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,compare value"
|
|
group ad:0xF0460014++0x03
|
|
line.long 0x00 "CNT_G0,G0 counter value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,counter value"
|
|
group ad:0xF0460018++0x03
|
|
line.long 0x00 "HOLD_G0,Counter hold register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
|
|
group ad:0xF0460024++0x03
|
|
line.long 0x00 "CNT_G1_EN,G1 timer enbale control register"
|
|
bitfld.long 0x00 1. " STOP ,when this bit set,the G0 counter was freezed" "0,1"
|
|
bitfld.long 0x00 0. " ENABLE ,when this bit set,the G1 start to count up or count down depend on the CNT_DIR configure bit. in one -shot mode ,this bit will be auto cleared by hardware while G0 timer overflow" "0,1"
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|
group ad:0xF0460028++0x03
|
|
line.long 0x00 "CNT_G1_CFG,G1 timer configure register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval, , after you update the counter interval,you need to write SI_WR_UPD to 1'b1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value, , after you update the increment value,you need to write INC_WR_UPD to 1'b1"
|
|
bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G1 timer 1'b1: reset G1 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G1 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload,this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
|
|
bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
|
|
group ad:0xF046002C++0x03
|
|
line.long 0x00 "CNT_G1_OVF,G1 timer terminal value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,terminal value, after you update the terminal value,you need to write OVF_WR_UPD to 1'b1"
|
|
group ad:0xF0460030++0x03
|
|
line.long 0x00 "CNT_G1_CMP,G1 timer compare value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,compare value, after you update the compare value,you need to write CMP_WR_UPD to 1'b1"
|
|
group ad:0xF0460034++0x03
|
|
line.long 0x00 "CNT_G1,G1 counter value"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,G1 counter value"
|
|
group ad:0xF0460038++0x03
|
|
line.long 0x00 "CNT_G1_UPD_FLAG,G1 timer configure value update flag"
|
|
bitfld.long 0x00 3. " INC_WR_UPD ,when this bit set,the INC[7:0] will be update to INC shadow register,this bit will be cleared by hardware" "0,1"
|
|
bitfld.long 0x00 2. " SI_WR_UPD ,when this bit set,the SI[7:0] will be update to counter interval shadow register,this bit will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 1. " CMP_WR_UPD ,when this bit set,the compare value will be update to compare shadow register,this bi will be auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 0. " OVF_WR_UPD ,when this bit set,terminal value will be update to terminal shadow register,this bit will be auto cleared by hardware" "0,1"
|
|
group ad:0xF046003C++0x03
|
|
line.long 0x00 "HOLD_G1,Counter hold register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
|
|
group ad:0xF0460040++0x03
|
|
line.long 0x00 "INT_STAT,Function interrupt status register"
|
|
bitfld.long 0x00 3. " OE_G1 ,CNT_G1 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,CNT_G0 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,CNT_G1 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,CNT_G0 timer compare event occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0460044++0x03
|
|
line.long 0x00 "INT_STAT_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,status enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,status enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,status enable" "0,1"
|
|
group ad:0xF0460048++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 3. " OE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 2. " OE_G0 ,signal enable" "0,1"
|
|
bitfld.long 0x00 1. " CE_G1 ,signal enable" "0,1"
|
|
bitfld.long 0x00 0. " CE_G0 ,signal enable" "0,1"
|
|
group ad:0xF046004C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0460050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,status enable" "0,1"
|
|
group ad:0xF0460054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,signal enable" "0,1"
|
|
group ad:0xF0460058++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error occur when transfer from apb clock domain to xtal24m clock domain,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer outputs lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF046005C++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error status enable" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error status enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error status enable" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error status enable" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error status enable" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error status enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error status enable" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error status enable" "0,1"
|
|
group ad:0xF0460060++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error signal enable" "0,1"
|
|
bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error signal enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
|
|
bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error signal enable" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error signal enable" "0,1"
|
|
bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error signal enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error signal enable" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error signal enable" "0,1"
|
|
group ad:0xF0460064++0x03
|
|
line.long 0x00 "PWDATA,pwdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,error injection on pwdata"
|
|
group ad:0xF0460068++0x03
|
|
line.long 0x00 "PWCODE,pwcode error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INJ ,error injection on pwcode"
|
|
group ad:0xF046006C++0x03
|
|
line.long 0x00 "IRQ_ERR,Interrupt error injection"
|
|
bitfld.long 0x00 2. " FUSA_UNCOR_INJ ,apb bus uncorrectable error, input DIverse redundant compare error or lockstep compare error" "0,1"
|
|
bitfld.long 0x00 1. " FUSA_COR_INJ ,pwdata correctable interruput error injection" "0,1"
|
|
bitfld.long 0x00 0. " INT_INJ ,compare event or overflow event error injection" "0,1"
|
|
group ad:0xF0460070++0x03
|
|
line.long 0x00 "LSP,Lockstep error injection"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INJ_BIT ,select which bit to inject error when compare the outputs of main core and it's copy core"
|
|
bitfld.long 0x00 1.--3. " INJ_SEL ,lockstep error injection select 3'b000: error injection for apb_bus lockstep (total 42bits lockstep compare signal) 3'b001: error injection for g0 timer lockstep(total 35bits lockstep compare signal) 3'b010: error injection .." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " INJ_EN ,lockstep error injection enable" "0,1"
|
|
group ad:0xF0460074++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,selftest mode enable" "0,1"
|
|
tree.end
|
|
tree "BTM6"
|
|
width 28.
|
|
group ad:0xF0470000++0x03
|
|
line.long 0x00 "COM_CTRL,G0 and G1 timer common control register"
|
|
bitfld.long 0x00 5.--6. " HOLD_CAP_CFG_G1 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G1 on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G1 on read operation to counter value of CNT_G1 - 2'b11: Hold register .." "0,1,2,3"
|
|
bitfld.long 0x00 4. " STOP_SYNC ,-When STOP_SYNC is high, it means that stop event of G1 timer are controlled by the G0 timer register configuration. -When STOP_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
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|
bitfld.long 0x00 3. " FRC_RLD_SYNC ,-When FRC_RLD_SYNC is high, it means that frc_rld_event of G1 timer are controlled by the G0 timer register configuration. -When FRC_RLD_SYNC is low, it means that above events are controlled by G1 timer register .." "0,1"
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bitfld.long 0x00 2. " START_SYNC ,-When START_SYNC is high, it means that start event of G1 timer are controlled by the G0 timer register configuration. -When START_SYNC is low, it means that above events are controlled by G1 timer register configuration." "0,1"
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textline " "
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bitfld.long 0x00 0.--1. "HOLD_CAP_CFG_G0 ,- 2'b00: Hold register not updated. - 2'b01: Hold register update to CNT_G0 value on read operation to counter value of CNT_G0 - 2'b10: Hold register update to CNT_G0 on read operation to counter value of CNT_G1 - 2'b11: Hold register.." "0,1,2,3"
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group ad:0xF0470004++0x03
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line.long 0x00 "CNT_G0_EN,G0 timer enbale control register"
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bitfld.long 0x00 1. " STOP ,When this bit is set, the G0 counter is freezed." "0,1"
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bitfld.long 0x00 0. " ENABLE ,When this bit is set, the G0 starts to count up or count down, depenDIng on the CNT_DIR configuration bit. In one -shot mode, this bit will be automatically cleared by the hardware when G0 timer overflows." "0,1"
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group ad:0xF0470008++0x03
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line.long 0x00 "CNT_G0_CFG,G0 timer configure register"
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hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval"
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hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value"
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bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G0 timer 1'b1: reset G0 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G0 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
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textline " "
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bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload this bit will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
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bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
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bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
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textline " "
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bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
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group ad:0xF047000C++0x03
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line.long 0x00 "CNT_G0_OVF,G0 timer terminal value"
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hexmask.long 0x00 0.--31. 1. " VAL ,terminal value"
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group ad:0xF0470010++0x03
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line.long 0x00 "CNT_G0_CMP,G0 timer compare value"
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hexmask.long 0x00 0.--31. 1. " VAL ,compare value"
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group ad:0xF0470014++0x03
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line.long 0x00 "CNT_G0,G0 counter value"
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hexmask.long 0x00 0.--31. 1. " VAL ,counter value"
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group ad:0xF0470018++0x03
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line.long 0x00 "HOLD_G0,Counter hold register"
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hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
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group ad:0xF0470024++0x03
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line.long 0x00 "CNT_G1_EN,G1 timer enbale control register"
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bitfld.long 0x00 1. " STOP ,when this bit set,the G0 counter was freezed" "0,1"
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bitfld.long 0x00 0. " ENABLE ,when this bit set,the G1 start to count up or count down depend on the CNT_DIR configure bit. in one -shot mode ,this bit will be auto cleared by hardware while G0 timer overflow" "0,1"
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group ad:0xF0470028++0x03
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line.long 0x00 "CNT_G1_CFG,G1 timer configure register"
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hexmask.long.byte 0x00 24.--31. 1. " SI_VAL ,counter interval, , after you update the counter interval,you need to write SI_WR_UPD to 1'b1"
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hexmask.long.byte 0x00 16.--23. 1. " INC_VAL ,incremental value, , after you update the increment value,you need to write INC_WR_UPD to 1'b1"
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bitfld.long 0x00 6. " SOFT_RST ,1'b0: no effect with G1 timer 1'b1: reset G1 timer to 0,after reset this bit will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 5. " FRC_RLD_RST_CNT_EN ,1'b0: no effect with G1 timer when force reload occur 1'b1: reset cnt to 0 when force reload occur" "0,1"
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textline " "
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bitfld.long 0x00 4. "FRC_RLD_EN ,1'b0: force reload DIsable 1'b1: force reload enable,after force reload,this bit will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 3. " TERM_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
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bitfld.long 0x00 2. " CMP_USE_MODE ,1'b0: DIrect used 1'b1: shadow used" "0,1"
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bitfld.long 0x00 1. " CNT_DIR ,1'b0: count up 1'b1: count down" "0,1"
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textline " "
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bitfld.long 0x00 0. "CNT_MODE ,1'b0: one_shot mode 1'b1: continuous mode" "0,1"
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group ad:0xF047002C++0x03
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line.long 0x00 "CNT_G1_OVF,G1 timer terminal value"
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hexmask.long 0x00 0.--31. 1. " VAL ,terminal value, after you update the terminal value,you need to write OVF_WR_UPD to 1'b1"
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group ad:0xF0470030++0x03
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line.long 0x00 "CNT_G1_CMP,G1 timer compare value"
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hexmask.long 0x00 0.--31. 1. " VAL ,compare value, after you update the compare value,you need to write CMP_WR_UPD to 1'b1"
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group ad:0xF0470034++0x03
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line.long 0x00 "CNT_G1,G1 counter value"
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hexmask.long 0x00 0.--31. 1. " VAL ,G1 counter value"
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group ad:0xF0470038++0x03
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line.long 0x00 "CNT_G1_UPD_FLAG,G1 timer configure value update flag"
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bitfld.long 0x00 3. " INC_WR_UPD ,when this bit set,the INC[7:0] will be update to INC shadow register,this bit will be cleared by hardware" "0,1"
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bitfld.long 0x00 2. " SI_WR_UPD ,when this bit set,the SI[7:0] will be update to counter interval shadow register,this bit will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 1. " CMP_WR_UPD ,when this bit set,the compare value will be update to compare shadow register,this bi will be auto cleared by hardware" "0,1"
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bitfld.long 0x00 0. " OVF_WR_UPD ,when this bit set,terminal value will be update to terminal shadow register,this bit will be auto cleared by hardware" "0,1"
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group ad:0xF047003C++0x03
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line.long 0x00 "HOLD_G1,Counter hold register"
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hexmask.long 0x00 0.--31. 1. " CNT ,HOLD_CAP_CFG: 2'b00:Hold register not updated. 2'b01:Hold register update on read operation to counter value of CNT_G0 2'b10:Hold register update on read operation to counter value of CNT_G1 2'b11:Hold register update on read .."
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group ad:0xF0470040++0x03
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line.long 0x00 "INT_STAT,Function interrupt status register"
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bitfld.long 0x00 3. " OE_G1 ,CNT_G1 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 2. " OE_G0 ,CNT_G0 timer overflow or underflow event occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 1. " CE_G1 ,CNT_G1 timer compare event occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 0. " CE_G0 ,CNT_G0 timer compare event occur,and you can write 1 to clear it" "0,1"
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group ad:0xF0470044++0x03
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line.long 0x00 "INT_STAT_EN,Function interrupt status enable register"
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bitfld.long 0x00 3. " OE_G1 ,status enable" "0,1"
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bitfld.long 0x00 2. " OE_G0 ,status enable" "0,1"
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bitfld.long 0x00 1. " CE_G1 ,status enable" "0,1"
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bitfld.long 0x00 0. " CE_G0 ,status enable" "0,1"
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group ad:0xF0470048++0x03
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line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
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bitfld.long 0x00 3. " OE_G1 ,signal enable" "0,1"
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bitfld.long 0x00 2. " OE_G0 ,signal enable" "0,1"
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bitfld.long 0x00 1. " CE_G1 ,signal enable" "0,1"
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bitfld.long 0x00 0. " CE_G0 ,signal enable" "0,1"
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|
group ad:0xF047004C++0x03
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|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,Function safety correctable error interrupt status register"
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|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error occur,and you can write 1 to clear it" "0,1"
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group ad:0xF0470050++0x03
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line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,Function safety correctable error interrupt status enable register"
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bitfld.long 0x00 0. " PWDATA_COR_ERR ,status enable" "0,1"
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group ad:0xF0470054++0x03
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line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
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bitfld.long 0x00 0. " PWDATA_COR_ERR ,signal enable" "0,1"
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group ad:0xF0470058++0x03
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line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,Function safety uncorrectable error interrupt status register"
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bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error occur when transfer from apb clock domain to xtal24m clock domain,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error occur,and you can write 1 to clear it" "0,1"
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textline " "
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bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer outputs lockstep compare error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error occur,and you can write 1 to clear it" "0,1"
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textline " "
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bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error occur,and you can write 1 to clear it" "0,1"
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textline " "
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error occur,and you can write 1 to clear it" "0,1"
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bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error occur,and you can write 1 to clear it" "0,1"
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group ad:0xF047005C++0x03
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line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,Function safety uncorrectable error interrupt status enable register"
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bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error status enable" "0,1"
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bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error status enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
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bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error status enable" "0,1"
|
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bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error status enable" "0,1"
|
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textline " "
|
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bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error status enable" "0,1"
|
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bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error status enable" "0,1"
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bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error status enable" "0,1"
|
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bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error status enable" "0,1"
|
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textline " "
|
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bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error status enable" "0,1"
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bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error status enable" "0,1"
|
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bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error status enable" "0,1"
|
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bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error status enable" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error status enable" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error status enable" "0,1"
|
|
group ad:0xF0470060++0x03
|
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line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
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bitfld.long 0x00 13. " G1_CNT_PAR_ERR ,G1 timer counter from xtal24m clock domain to apb clock domain parity error signal enable" "0,1"
|
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bitfld.long 0x00 12. " CFG_VAL_PAR_ERR ,configure value of G1 timer such as si_val[7:0], inc_val[7:0], ovf_val[31:0], cmp_val[31:0] parity error signal enable when transfer from apb clock domain to xtal24m clock domain" "0,1"
|
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bitfld.long 0x00 11. " ASYNC_2XTAL24M_PAR_ERR ,apb clock domain to xtal24m clock domain async redundant parity error signal enable" "0,1"
|
|
bitfld.long 0x00 10. " ASYNC_2APB_PAR_ERR ,xtal24m clock domain to apb clock domain aysnc reduadant parity error signal enable" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 9. "LSP_G0_ERR ,G0 timer lockstep compare error signal enable" "0,1"
|
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bitfld.long 0x00 8. " LSP_XTAL24M_ERR ,XTAL24Mhz lockstep compare error signal enable" "0,1"
|
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bitfld.long 0x00 7. " LSP_APB_SLV_CMP_ERR ,apb bus lockstep compare error signal enable" "0,1"
|
|
bitfld.long 0x00 6. " LSP_IRQ_CMP_ERR ,IRQ lockstep compare error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LSP_G1_ERR ,G1 timer configure register lockstep compare error signal enable" "0,1"
|
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bitfld.long 0x00 4. " INPUT_ERR ,input redundant compare error signal enable" "0,1"
|
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bitfld.long 0x00 3. " P_CTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable) parity error signal enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error signal enable" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCOR_ERR ,Pwdata uncorrectable error signal enable" "0,1"
|
|
group ad:0xF0470064++0x03
|
|
line.long 0x00 "PWDATA,pwdata error injection"
|
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hexmask.long 0x00 0.--31. 1. " INJ ,error injection on pwdata"
|
|
group ad:0xF0470068++0x03
|
|
line.long 0x00 "PWCODE,pwcode error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INJ ,error injection on pwcode"
|
|
group ad:0xF047006C++0x03
|
|
line.long 0x00 "IRQ_ERR,Interrupt error injection"
|
|
bitfld.long 0x00 2. " FUSA_UNCOR_INJ ,apb bus uncorrectable error, input DIverse redundant compare error or lockstep compare error" "0,1"
|
|
bitfld.long 0x00 1. " FUSA_COR_INJ ,pwdata correctable interruput error injection" "0,1"
|
|
bitfld.long 0x00 0. " INT_INJ ,compare event or overflow event error injection" "0,1"
|
|
group ad:0xF0470070++0x03
|
|
line.long 0x00 "LSP,Lockstep error injection"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INJ_BIT ,select which bit to inject error when compare the outputs of main core and it's copy core"
|
|
bitfld.long 0x00 1.--3. " INJ_SEL ,lockstep error injection select 3'b000: error injection for apb_bus lockstep (total 42bits lockstep compare signal) 3'b001: error injection for g0 timer lockstep(total 35bits lockstep compare signal) 3'b010: error injection .." "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 0. " INJ_EN ,lockstep error injection enable" "0,1"
|
|
group ad:0xF0470074++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,selftest mode enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "CKGEN"
|
|
tree "CKGEN_SF"
|
|
width 22.
|
|
group ad:0xF06A0000++0x03
|
|
line.long 0x00 "DOM_PER0_0,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0004++0x03
|
|
line.long 0x00 "DOM_PER1_0,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0008++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_0,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
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|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF06A000C++0x03
|
|
line.long 0x00 "DOM_PER0_1,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0010++0x03
|
|
line.long 0x00 "DOM_PER1_1,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0014++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_1,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF06A0018++0x03
|
|
line.long 0x00 "DOM_PER0_2,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A001C++0x03
|
|
line.long 0x00 "DOM_PER1_2,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0020++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_2,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF06A0024++0x03
|
|
line.long 0x00 "DOM_PER0_3,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0028++0x03
|
|
line.long 0x00 "DOM_PER1_3,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A002C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_3,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF06A0030++0x03
|
|
line.long 0x00 "DOM_PER0_4,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0034++0x03
|
|
line.long 0x00 "DOM_PER1_4,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0038++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_4,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF06A003C++0x03
|
|
line.long 0x00 "DOM_PER0_5,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0040++0x03
|
|
line.long 0x00 "DOM_PER1_5,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF06A0044++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_5,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF06A0048++0x03
|
|
line.long 0x00 "DOM_PER0_6,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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group ad:0xF06A004C++0x03
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line.long 0x00 "DOM_PER1_6,This register is used for to control domain4~7 secure and priviledge access permission."
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bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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group ad:0xF06A0050++0x03
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line.long 0x00 "DOM_PER_LOCK_6,This register is used to lock domain access permission setting."
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bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
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bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
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bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
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bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
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textline " "
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bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
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bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
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bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
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bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
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group ad:0xF06A0054++0x03
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line.long 0x00 "DOM_PER0_7,This register is used for to control domain0~3 secure and priviledge access permission."
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bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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group ad:0xF06A0058++0x03
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line.long 0x00 "DOM_PER1_7,This register is used for to control domain4~7 secure and priviledge access permission."
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bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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group ad:0xF06A005C++0x03
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line.long 0x00 "DOM_PER_LOCK_7,This register is used to lock domain access permission setting."
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bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
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bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
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bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
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bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
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textline " "
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bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
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bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
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bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
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bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
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group ad:0xF06A0200++0x03
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line.long 0x00 "CKGEN_GLB_CTL_RS,CKGEN GLOBAL CONTROL REGISTER RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A0204++0x03
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line.long 0x00 "CKGEN_GLB_CTL,CKGEN GLOBAL CONTROL REGISTER"
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bitfld.long 0x00 28.--31. " CLK_24M_DIV_C_NUM ,clock 24m DIvider c DIvide number DIvided clock frequency is 24M/(clk_24m_DIv_c_num+1)/4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 18.--27. 1. " CLK_24M_DIV_B_NUM ,clock 24m DIvider b DIvide number DIvided clock frequency is 24M/(clk_24m_DIv_b_num+1)/2"
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hexmask.long.word 0x00 3.--12. 1. " clk_24m_DIv_a_num ,clock 24m DIvider a DIvide number DIvided clock frequency is 24M/(clk_24m_DIv_a_num+1)/2"
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bitfld.long 0x00 2. " CLK_24M_DIV_C_DIS ,clock 24m DIvider c which is used for pcg/bcg/ccg clock active monitor golden clock DIsable. 1. clock 24m DIvider DIsable. 0. clock 24m DIvider enable." "0,1"
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textline " "
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bitfld.long 0x00 1. "CLK_24M_DIV_B_DIS ,clock 24m DIvider b which is used for frequency monitor golden clock DIsable. 1. clock 24m DIvider DIsable. 0. clock 24m DIvider enable." "0,1"
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bitfld.long 0x00 0. " CLK_24M_DIV_A_DIS ,clock 24m DIvider a which is used for frequency monitor golden clock DIsable. 1. clock 24m DIvider DIsable. 0. clock 24m DIvider enable." "0,1"
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group ad:0xF06A0300++0x03
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line.long 0x00 "CKGEN_SUP_DOM,CKGEN SUPER DOMAIN REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock the entire register" "0,1"
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bitfld.long 0x00 5.--6. " PPROT ,pprot for super doman" "0,1,2,3"
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bitfld.long 0x00 4. " SEC_EN ,check pprot enable" "0,1"
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bitfld.long 0x00 0.--3. " DID ,super domain domain id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A0400++0x03
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line.long 0x00 "CKGEN_RES_RS,CKGEN RESERVE REGISTER RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A0404++0x03
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line.long 0x00 "CKGEN_RES,CKGEN RESERVE REGISTER"
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hexmask.long 0x00 0.--31. 1. " RES ,bit[31:2]: reserve register for future use bit[1]: sp cpu/axi/apb clock ratio select 0: 4/2/1 1: 2/2/1 bit[0]: sf cpu/axi/apb clock ratio select 0: 4/2/1 1: 2/2/1"
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group ad:0xF06A0500++0x03
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line.long 0x00 "CKGEN_MISC_RS,CKGEN MISC REGISTER RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A0504++0x03
|
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line.long 0x00 "CKGEN_MISC,CKGEN MISC REGISTER"
|
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hexmask.long 0x00 0.--31. 1. " MISC ,bit[31:1]: reserved bit[0]: enable for permission error as apbslverr"
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group ad:0xF06A0508++0x03
|
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line.long 0x00 "CKGEN_MISC_MON,CKGEN MISC MONITOR REGISTER"
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hexmask.long 0x00 0.--31. 1. " MON ,ckgen misc monitor: bit[21:18]: swm o bit[17]: swm ack bit[16:13]: swm i bit12: swm req bit11: rsv bit10: slp complete bit 9: hib complete bit8: run complete bit7: rtc status bit6: slp status bit5: hib status bit4: run status bit[3.."
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group ad:0xF06A1000++0x03
|
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
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group ad:0xF06A1004++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
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textline " "
|
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1008++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A100C++0x03
|
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
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group ad:0xF06A1010++0x03
|
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A1014++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1018++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A101C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A1020++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A1024++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1028++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A102C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A1030++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A1034++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1038++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
|
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A103C++0x03
|
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1040++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A1044++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1048++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A104C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1050++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1054++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1058++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF06A105C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1060++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1064++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1068++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A106C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1070++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1074++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1078++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A107C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1080++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1084++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1088++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A108C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1090++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1094++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1098++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A109C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A10A0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A10A4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A10A8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A10AC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A10B0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A10B4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A10B8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A10BC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A10C0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A10C4++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A10C8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A10CC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A10D0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A10D4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A10D8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A10DC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A10E0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A10E4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A10E8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A10EC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A10F0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A10F4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A10F8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF06A10FC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1100++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A1104++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1108++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A110C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1110++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A1114++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1118++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A111C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1120++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1124++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1128++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A112C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1130++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1134++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1138++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A113C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1140++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1144++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1148++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A114C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1150++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1154++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1158++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A115C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1160++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1164++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1168++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A116C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1170++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1174++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1178++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A117C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1180++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1184++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1188++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A118C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1190++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1194++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1198++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A119C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A11A0++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A11A4++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A11A8++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A11AC++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A11B0++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A11B4++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A11B8++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A11BC++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A11C0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A11C4++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A11C8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A11CC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A11D0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A11D4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A11D8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A11DC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A11E0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A11E4++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A11E8++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A11EC++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A11F0++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A11F4++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A11F8++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A11FC++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A1200++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A1204++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1208++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A120C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A1210++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A1214++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1218++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
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|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A121C++0x03
|
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1220++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1224++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1228++0x03
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|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A122C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1230++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1234++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1238++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A123C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1240++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1244++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1248++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A124C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1250++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1254++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1258++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A125C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1260++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1264++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1268++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A126C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1270++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1274++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1278++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A127C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1280++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1284++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1288++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A128C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1290++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1294++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1298++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A129C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A12A0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A12A4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A12A8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A12AC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A12B0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A12B4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A12B8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A12BC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A12C0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A12C4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A12C8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF06A12CC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A12D0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A12D4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A12D8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF06A12DC++0x03
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|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A12E0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A12E4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A12E8++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A12EC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A12F0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A12F4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A12F8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A12FC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1300++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1304++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1308++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A130C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1310++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1314++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1318++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A131C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1320++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1324++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1328++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A132C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1330++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1334++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1338++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A133C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1340++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1344++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1348++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A134C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1350++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1354++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A1358++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A135C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1360++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1364++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
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|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1368++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
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|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A136C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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|
group ad:0xF06A1370++0x03
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|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A1374++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1378++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A137C++0x03
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|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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|
group ad:0xF06A1380++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A1384++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A1388++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A138C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A1390++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A1394++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A1398++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A139C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A13A0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A13A4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A13A8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A13AC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A13B0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A13B4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
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|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A13B8++0x03
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|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF06A13BC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A13C0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A13C4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF06A13C8++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF06A13CC++0x03
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|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A13D0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A13D4++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF06A13D8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A13DC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A13E0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A13E4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A13E8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A13EC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A13F0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A13F4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A13F8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A13FC++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2000++0x03
|
|
line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A2004++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2008++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A200C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A2010++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2014++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2018++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A201C++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2020++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2024++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2028++0x03
|
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A202C++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
|
bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2030++0x03
|
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
|
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
|
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2034++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A2038++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A203C++0x03
|
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2040++0x03
|
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A2044++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
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group ad:0xF06A2048++0x03
|
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
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group ad:0xF06A204C++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A2050++0x03
|
|
line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A2054++0x03
|
|
line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
|
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2058++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A205C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A2060++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2064++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2068++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A206C++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2070++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2074++0x03
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2078++0x03
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A207C++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2080++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2084++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A2088++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A208C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2090++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2094++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2098++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A209C++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A20A0++0x03
|
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A20A4++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
|
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A20A8++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A20AC++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A20B0++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A20B4++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A20B8++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A20BC++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A20C0++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A20C4++0x03
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A20C8++0x03
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A20CC++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A20D0++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A20D4++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A20D8++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A20DC++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A20E0++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A20E4++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A20E8++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A20EC++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A20F0++0x03
|
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A20F4++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
|
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A20F8++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A20FC++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A2100++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2104++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2108++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A210C++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2110++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2114++0x03
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2118++0x03
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A211C++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2120++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2124++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A2128++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A212C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2130++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2134++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2138++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A213C++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2140++0x03
|
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF06A2144++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2148++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A214C++0x03
|
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF06A2150++0x03
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|
line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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|
hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2154++0x03
|
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2158++0x03
|
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A215C++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF06A2160++0x03
|
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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|
group ad:0xF06A2164++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A2168++0x03
|
|
line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF06A216C++0x03
|
|
line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2170++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF06A2174++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF06A2178++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A217C++0x03
|
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF06A2180++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A2184++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
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group ad:0xF06A2188++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A218C++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A3000++0x03
|
|
line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A3004++0x03
|
|
line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A3008++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A300C++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A3010++0x03
|
|
line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A3014++0x03
|
|
line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A3018++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A301C++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A3020++0x03
|
|
line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A3024++0x03
|
|
line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A3028++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A302C++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A3030++0x03
|
|
line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A3034++0x03
|
|
line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A3038++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A303C++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A3040++0x03
|
|
line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A3044++0x03
|
|
line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF06A3048++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A304C++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF06A4000++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4004++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4008++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A400C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4010++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4014++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4018++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A401C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4020++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4024++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4028++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A402C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4030++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4034++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4038++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A403C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4040++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4044++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4048++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A404C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4050++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4054++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4058++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A405C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4060++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4064++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4068++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A406C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4070++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4074++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4078++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A407C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4080++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4084++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4088++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A408C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4090++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A4094++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A4098++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A409C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5000++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5004++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5008++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A500C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5010++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5014++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5018++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A501C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5020++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5024++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5028++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A502C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5030++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5034++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5038++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A503C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5040++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5044++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5048++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A504C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5050++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5054++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5058++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A505C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5060++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5064++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5068++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A506C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5070++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5074++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5078++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A507C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5080++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5084++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5088++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A508C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5090++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A5094++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A5098++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A509C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6000++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6004++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6008++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A600C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6010++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6014++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6018++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A601C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6020++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6024++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6028++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A602C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6030++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6034++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6038++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A603C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6040++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6044++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6048++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A604C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6050++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6054++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6058++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A605C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6060++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6064++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6068++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A606C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6070++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6074++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6078++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A607C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6080++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6084++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6088++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A608C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6090++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A6094++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A6098++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A609C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A7000++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A7004++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A7008++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A700C++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A7010++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A7014++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A7018++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A701C++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A7020++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A7024++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A7028++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A702C++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A7030++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A7034++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A7038++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A703C++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A7040++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A7044++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A7500++0x03
|
|
line.long 0x00 "XTAL_RS,CKGEN XTAL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A7504++0x03
|
|
line.long 0x00 "XTAL_CTL,CKGEN XTAL CONTROL REGISTER"
|
|
bitfld.long 0x00 3. " ignore_xtal ,ignore xtal. 1: xtal ignore 0: involve xtal" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06A7508++0x03
|
|
line.long 0x00 "XTAL_MON_CTL,CKGEN XTAL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " xtal_clk_active ,xtal24m clock active, as fs_24m clock output inDIcator" "0,1"
|
|
bitfld.long 0x00 30. " rc24m_clk_active ,rc24m clock active, as fs_24m clock output inDIcator" "0,1"
|
|
bitfld.long 0x00 29. " xtal_clk_rdy ,xtal24m clock ready inDIcator" "0,1"
|
|
bitfld.long 0x00 28. " rc24m_clk_rdy ,rc24m clock ready inDIcator" "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--23. 1. "TOUT_VAL ,timeout value between power on/enable to pll clock ready. this can only be changed after mon_en change to 0."
|
|
bitfld.long 0x00 1. " MON_EN_STA ,mon_en status. set mon_en, then check mon_en_sta to make sure mon_en setting is active." "0,1"
|
|
bitfld.long 0x00 0. " MON_EN ,xtal ready check enable from ckgen DIsable xtal to enable xtal. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF06A8000++0x03
|
|
line.long 0x00 "DBG_MON_RS,CKGEN DEBUG AND MONITOR RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06A8004++0x03
|
|
line.long 0x00 "DBG_MON_CLK_SRC,CKGEN DEBUG AND MONITOR CLOCK SOURCE SELECT REGISTER"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EXT_CLK_SRC_SEL ,ext clock source select, accorDIng to ext clock monitor index"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CORE_CLK_SRC_SEL ,core clock source select, accorDIng to core slice index"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BUS_CLK_SRC_SEL ,bus clock source select, accorDIng to bus slice index"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IP_CLK_SRC_SEL ,ip clock source select, accorDIng to ip slice index"
|
|
group ad:0xF06A8008++0x03
|
|
line.long 0x00 "DBG_MON_CTL,CKGEN DEBUG MONITOR CONTROL REGISTER"
|
|
bitfld.long 0x00 3.--4. " CLK_SEL ,debug and monitor and cqm clock source select. 2'b00: ip slice clock output 2'b01: bus slice clock output 2'b10: core slice clock output 2'b11: ext clock input" "0,1,2,3"
|
|
bitfld.long 0x00 2. " CQM_GATING_EN ,cqm gating enable 1: not gated 0: gated" "0,1"
|
|
bitfld.long 0x00 1. " MON_GATING_EN ,monitor gating enable 1: not gated 0: gated" "0,1"
|
|
bitfld.long 0x00 0. " DBG_GATING_EN ,dbg gating enable 1: not gated 0: gated" "0,1"
|
|
group ad:0xF06A800C++0x03
|
|
line.long 0x00 "DBG_CTL,CKGEN DEBUG CONTROL REGISTER"
|
|
bitfld.long 0x00 0.--3. " DIV_NUM ,debug clock output to pad DIvider number debug clock output frequency equals to: clock source/(DIV_NUM+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group ad:0xF06A8010++0x03
|
|
line.long 0x00 "MON_CTL,CKGEN MONITOR CONTROL REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " FREQ_MON ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " FREQ_MON_UPD ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 2. " ACTIVE_LOSS_DIS ,active monitor clock loss DIsable. 1: DIsable 0: enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "MON_CLK_SRC_SEL ,reference clock source select. 0: from clk_mon_a 1: from clk_mon_b" "0,1"
|
|
bitfld.long 0x00 0. " MON_EN ,frequency monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF06A8014++0x03
|
|
line.long 0x00 "MON_CHK_THRD,MONITOR CHECK THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,high threshold. violation happends when frequency counter larger than High register"
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|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when frequency counter less than Low register"
|
|
group ad:0xF06A8020++0x03
|
|
line.long 0x00 "LOW_SPD_CHK_CTL,CKGEN 24M AND 32K CHECK REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " FREQ_MON ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * 32K"
|
|
bitfld.long 0x00 15. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 14. " FREQ_MON_UPD ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
hexmask.long.byte 0x00 8.--13. 1. " 32K_SRC_SEL ,32k clock source select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 2.--7. 1. "24M_SRC_SEL ,24m clock source select"
|
|
bitfld.long 0x00 1. " MON_EN ,frequency monitor enable 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " CLK_LOSS_DIS ,24m loss check DIsable 1: DIsable 0: enable" "0,1"
|
|
group ad:0xF06A8024++0x03
|
|
line.long 0x00 "LOW_SPD_CHK_THRD,CKGEN 24M AND 32K CHECK THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,high threshold. violation happends when frequency counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when frequency counter less than Low register"
|
|
group ad:0xF06A8040++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
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hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF06A8044++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
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|
group ad:0xF06A8048++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF06A804C++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF06A8050++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF06A8054++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF06A8058++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF06AA000++0x03
|
|
line.long 0x00 "CKGEN_FUSA_RS,CKGEN FUSA RELATED REGISTER RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06AA004++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 23. " PADDR_INT_CLR ,paddr uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 22. " PUSER_INT_CLR ,puser uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 21. " PCTRL1_INT_CLR ,pctrl1 uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 20. " PCTRL0_INT_CLR ,pctrl0 uncorrectable error interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "PWDAT_C_INT_CLR ,pwdata correctable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " PWDAT_U_INT_CLR ,pwdata uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " PWDAT_F_INT_CLR ,pwdata fatal error interrupt clear" "0,1"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. "PUSER_INT_STA ,puser uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 11. " PWDAT_C_INT_STA ,pwdata correctable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status." "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. " PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF06AA008++0x03
|
|
line.long 0x00 "APB_LKSTEP_INT,APB LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 19. " SYNC_ERR_INT_CLR ,sync error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " RESP_ERR_INT_CLR ,response parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " REQ_ERR_INT_CLR ,request parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 16. " CMP_ERR_INT_CLR ,lockstep compare interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "SYNC_ERR_INT_STA ,sync error status" "0,1"
|
|
bitfld.long 0x00 10. " RESP_ERR_INT_STA ,response parity error status" "0,1"
|
|
bitfld.long 0x00 9. " REQ_ERR_INT_STA ,request parity error status" "0,1"
|
|
bitfld.long 0x00 8. " CMP_ERR_INT_STA ,lockstep compare error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SYNC_ERR_INT_EN ,apb sync error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " RESP_ERR_INT_EN ,apb response parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " REQ_ERR_INT_EN ,apb request parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_ERR_INT_EN ,lockstep compare interrupt enable" "0,1"
|
|
group ad:0xF06AA00C++0x03
|
|
line.long 0x00 "WDT_LKSTEP_INT,WDT LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 17. " SYNC_ERR_INT_CLR ,sync error interrupt clear" "0,1"
|
|
bitfld.long 0x00 16. " CMP_ERR_INT_CLR ,lockstep compare interrupt clear" "0,1"
|
|
bitfld.long 0x00 9. " SYNC_ERR_INT_STA ,sync error status" "0,1"
|
|
bitfld.long 0x00 8. " CMP_ERR_INT_STA ,lockstep compare error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SYNC_ERR_INT_EN ,wdt sync error interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_ERR_INT_EN ,lockstep compare interrupt enable" "0,1"
|
|
group ad:0xF06AA100++0x03
|
|
line.long 0x00 "CKGEN_FUSA_INT,CKGEN INTERNAL FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 19. " LKSTEP_CMP_ERR_CLR ,rstgen core lockstep compare error clear" "0,1"
|
|
bitfld.long 0x00 18. " SYNC_ERR_CLR ,internal sync check error clear" "0,1"
|
|
bitfld.long 0x00 17. " SWM_TRANS_ERR_CLR ,swm transfer error clear" "0,1"
|
|
bitfld.long 0x00 16. " SWM_CHK_ERR_CLR ,swm one hot check error clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LKSTEP_CMP_ERR_STA ,rstgen core lockstep compare error status" "0,1"
|
|
bitfld.long 0x00 10. " SYNC_ERR_STA ,internal sync check error status" "0,1"
|
|
bitfld.long 0x00 9. " SWM_TRANS_ERR_STA ,swm transfer error status" "0,1"
|
|
bitfld.long 0x00 8. " SWM_CHK_ERR_STA ,swm one hot check error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "LKSTEP_CMP_ERR_EN ,rstgen core lockstep compare error enable" "0,1"
|
|
bitfld.long 0x00 2. " SYNC_ERR_EN ,internal sync check error enable" "0,1"
|
|
bitfld.long 0x00 1. " SWM_TRANS_ERR_EN ,swm transfer error enable" "0,1"
|
|
bitfld.long 0x00 0. " SWM_CHK_ERR_EN ,swm one hot check error enable" "0,1"
|
|
group ad:0xF06AA200++0x03
|
|
line.long 0x00 "CKGEN_INJ_EN,CKGEN ERROR INJECTION ENABLE"
|
|
hexmask.long.word 0x00 0.--15. 1. " INJ_EN ,error injection enable bit[0]: irq error injection enable. bit[1]: ckgen lkstep error injection enable. bit[2]: aapb lkstep error injection enable bit[3]: aapb req ded error injection enable. bit[4]: aapb output error injection.."
|
|
group ad:0xF06AA204++0x03
|
|
line.long 0x00 "CKGEN_INJ_BIT,CKGEN ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 29.--31. " IRQ_INJ ,irq inj: bit0: inj for unc_irq bit1: inj for cor_irq bit2: inj for ckgen_irq" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ERR_INJ_BIT ,error injection bit bit[3:0]: aapb resp ded error injection bit. bit[20:8]: ckgen lkstep error injection bit. bit[28:21]: ckgen dout error injection bit."
|
|
group ad:0xF06AA208++0x03
|
|
line.long 0x00 "CKGEN_INJ_BIT_1,CKGEN ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_BIT ,error injection bit bit[7:0]: aapb lkstep injection bit. bit[11:8]: aapb req ded error injection bit. bit[15:12]: aapb output error injection bit."
|
|
group ad:0xF06AA20C++0x03
|
|
line.long 0x00 "CKGEN_INJ_BIT_2,CKGEN ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_BIT ,error injection bit"
|
|
group ad:0xF06AA300++0x03
|
|
line.long 0x00 "IP_CLK_COR_EN_0,IP SLICE FREQUENCY CHECK CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,ip slice frequency check correctable error enable"
|
|
group ad:0xF06AA304++0x03
|
|
line.long 0x00 "IP_CLK_UNC_EN_0,IP SLICE FREQUENCY CHECK UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " int_en ,ip slice frequency check uncorrectable error enable"
|
|
group ad:0xF06AA308++0x03
|
|
line.long 0x00 "IP_CLK_INT_STA_0,IP SLICE FREQUENCY CHECK ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
group ad:0xF06AA30C++0x03
|
|
line.long 0x00 "IP_CLK_COR_EN_1,IP SLICE FREQUENCY CHECK CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,ip slice frequency check correctable error enable"
|
|
group ad:0xF06AA310++0x03
|
|
line.long 0x00 "IP_CLK_UNC_EN_1,IP SLICE FREQUENCY CHECK UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " int_en ,ip slice frequency check uncorrectable error enable"
|
|
group ad:0xF06AA314++0x03
|
|
line.long 0x00 "IP_CLK_INT_STA_1,IP SLICE FREQUENCY CHECK ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
group ad:0xF06AA400++0x03
|
|
line.long 0x00 "BUS_CLK_COR_EN_0,BUS SLICE FREQUENCY CHECK CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,bus slice frequency check correctable error enable"
|
|
group ad:0xF06AA404++0x03
|
|
line.long 0x00 "BUS_CLK_UNC_EN_0,BUS SLICE UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,bus slice frequency check uncorrectable error enable"
|
|
group ad:0xF06AA408++0x03
|
|
line.long 0x00 "BUS_CLK_INT_STA_0,BUS SLICE FREQUENCY CHECK ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
group ad:0xF06AA500++0x03
|
|
line.long 0x00 "CORE_CLK_COR_EN_0,CORE SLICE CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,core slice frequency check correctable error enable"
|
|
group ad:0xF06AA504++0x03
|
|
line.long 0x00 "CORE_CLK_UNC_EN_0,CORE SLICE FREQUENCY CHECK UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,core slice frequency check uncorrectable error enable"
|
|
group ad:0xF06AA508++0x03
|
|
line.long 0x00 "CORE_CLK_INT_STA_0,CORE SLICE FREQUENCY CHECK ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,core slice frequency check uncorrectable error status" "0,1"
|
|
group ad:0xF06AA600++0x03
|
|
line.long 0x00 "PCG_COR_EN_0,PCG ACTIVE MONITOR CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,pcg active monitor check correctable error enable"
|
|
group ad:0xF06AA604++0x03
|
|
line.long 0x00 "PCG_UNC_EN_0,PCG ACTIVE MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,pcg active monitor uncorrectable error enable"
|
|
group ad:0xF06AA608++0x03
|
|
line.long 0x00 "PCG_INT_STA_0,PCG ACTIVE MONITOR ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,active monitor uncorrectable error status" "0,1"
|
|
group ad:0xF06AA700++0x03
|
|
line.long 0x00 "BCG_COR_EN_0,BCG ACTIVE MONITOR CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,bcg active monitor check correctable error enable"
|
|
group ad:0xF06AA704++0x03
|
|
line.long 0x00 "BCG_UNC_EN_0,BCG ACTIVE MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,bcg active monitor uncorrectable error enable"
|
|
group ad:0xF06AA708++0x03
|
|
line.long 0x00 "BCG_INT_STA_0,BCG ACTIVE MONITOR ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,active monitor uncorrectable error status" "0,1"
|
|
group ad:0xF06AA800++0x03
|
|
line.long 0x00 "CCG_COR_EN_0,CCG ACTIVE MONITOR CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,ccg active monitor check correctable error enable"
|
|
group ad:0xF06AA804++0x03
|
|
line.long 0x00 "CCG_UNC_EN_0,CCG ACTIVE MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,ccg active monitor uncorrectable error enable"
|
|
group ad:0xF06AA808++0x03
|
|
line.long 0x00 "CCG_INT_STA_0,CCG ACTIVE MONITOR ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,active monitor uncorrectable error status" "0,1"
|
|
group ad:0xF06AA904++0x03
|
|
line.long 0x00 "PLL_UNC_EN,PLL MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INT_EN ,pll monitor uncorrectable error enable. bit[7:3]: reserved. bit[2:0]: pll"
|
|
group ad:0xF06AA908++0x03
|
|
line.long 0x00 "PLL_INT_STA,PLL MONITOR ERROR STATUS REGISTER"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,pll monitor timeout error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,pll monitor timeout error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,pll monitor timeout error status" "0,1"
|
|
group ad:0xF06AAA04++0x03
|
|
line.long 0x00 "XTAL_UNC_EN,XTAL MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INT_EN ,xtal monitor uncorrectable error enable. bit[7:1]: reserved. bit[0]: enable"
|
|
group ad:0xF06AAA08++0x03
|
|
line.long 0x00 "XTAL_INT_STA,XTAL MONITOR ERROR STATUS REGISTER"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,xtal monitor timeout error status" "0,1"
|
|
group ad:0xF06AAB00++0x03
|
|
line.long 0x00 "MON_COR_EN,CKGEN MONITOR CORRECTABLE ERROR ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " INT_EN ,ckgen monitor correctable error enable" "0,1"
|
|
group ad:0xF06AAB04++0x03
|
|
line.long 0x00 "MON_UNC_EN,CKGEN MONITOR UNCORRECTABLE ERROR ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " INT_EN ,ckgen monitor uncorrectable error enable" "0,1"
|
|
group ad:0xF06AAB08++0x03
|
|
line.long 0x00 "MON_INT_STA,CKGEN MONITOR INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 0. " INT_STA ,ckgen monitor interrupt status write it to 0 to clear it" "0,1"
|
|
group ad:0xF06AAC00++0x03
|
|
line.long 0x00 "LOW_SPD_COR_EN,CKGEN LOW SPEED CHECK CORRECTABLE ERROR ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " INT_EN ,ckgen low speed monitor correctable error enable" "0,1"
|
|
group ad:0xF06AAC04++0x03
|
|
line.long 0x00 "LOW_SPD_UNC_EN,CKGEN LOW SPEED CHECK UNCORRECTABLE ERROR ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " INT_EN ,ckgen low speed monitor uncorrectable error enable" "0,1"
|
|
group ad:0xF06AAC08++0x03
|
|
line.long 0x00 "LOW_SPD_INT_STA,CKGEN LOW SPEED CHECK INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 0. " INT_STA ,ckgen low speed monitor interrupt status write it to 0 to clear it" "0,1"
|
|
group ad:0xF06AAD00++0x03
|
|
line.long 0x00 "CQM_COR_EN,CQM CORRECTABLE ERROR ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,cqm correctable error enable"
|
|
group ad:0xF06AAD04++0x03
|
|
line.long 0x00 "CQM_UNC_EN,CQM UNCORRECTABLE ERROR ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,cqm uncorrectable error enable"
|
|
group ad:0xF06AAD08++0x03
|
|
line.long 0x00 "CQM_DUTY_INT_STA,CQM DUTY ERROR INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,cqm_x duty error status" "0,1"
|
|
group ad:0xF06AAD0C++0x03
|
|
line.long 0x00 "CQM_JITTER_INT_STA,CQM JITTER ERROR INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,cqm_x jitter error status" "0,1"
|
|
group ad:0xF06AB000++0x03
|
|
line.long 0x00 "CKGEN_FUNC_INT_RS,This register is used for assign rule space for rstgen function interrupt register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06AB004++0x03
|
|
line.long 0x00 "CKGEN_FUNC_INT,CKGEN FUNC INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " ACCESS_PER_ERR_CLR ,access permission check error clear,must be set to 0 after clear function interrupt" "0,1"
|
|
bitfld.long 0x00 8. " ACCESS_PER_ERR_STA ,access permission check error status" "0,1"
|
|
bitfld.long 0x00 0. " ACCESS_PER_ERR_EN ,access permission check error enable" "0,1"
|
|
tree.end
|
|
tree "CKGEN_AP"
|
|
width 22.
|
|
group ad:0xF30C0000++0x03
|
|
line.long 0x00 "DOM_PER0_0,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0004++0x03
|
|
line.long 0x00 "DOM_PER1_0,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0008++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_0,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30C000C++0x03
|
|
line.long 0x00 "DOM_PER0_1,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0010++0x03
|
|
line.long 0x00 "DOM_PER1_1,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0014++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_1,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30C0018++0x03
|
|
line.long 0x00 "DOM_PER0_2,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C001C++0x03
|
|
line.long 0x00 "DOM_PER1_2,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0020++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_2,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30C0024++0x03
|
|
line.long 0x00 "DOM_PER0_3,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0028++0x03
|
|
line.long 0x00 "DOM_PER1_3,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C002C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_3,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30C0030++0x03
|
|
line.long 0x00 "DOM_PER0_4,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0034++0x03
|
|
line.long 0x00 "DOM_PER1_4,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0038++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_4,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30C003C++0x03
|
|
line.long 0x00 "DOM_PER0_5,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0040++0x03
|
|
line.long 0x00 "DOM_PER1_5,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C0044++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_5,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30C0048++0x03
|
|
line.long 0x00 "DOM_PER0_6,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30C004C++0x03
|
|
line.long 0x00 "DOM_PER1_6,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
textline " "
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bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
textline " "
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|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
textline " "
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|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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group ad:0xF30C0050++0x03
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line.long 0x00 "DOM_PER_LOCK_6,This register is used to lock domain access permission setting."
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bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
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bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
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bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
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bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
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textline " "
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bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
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bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
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bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
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bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
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group ad:0xF30C0054++0x03
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line.long 0x00 "DOM_PER0_7,This register is used for to control domain0~3 secure and priviledge access permission."
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bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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group ad:0xF30C0058++0x03
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line.long 0x00 "DOM_PER1_7,This register is used for to control domain4~7 secure and priviledge access permission."
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bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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group ad:0xF30C005C++0x03
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line.long 0x00 "DOM_PER_LOCK_7,This register is used to lock domain access permission setting."
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bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
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bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
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bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
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bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
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textline " "
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bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
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bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
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bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
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bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
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group ad:0xF30C0200++0x03
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line.long 0x00 "CKGEN_GLB_CTL_RS,CKGEN GLOBAL CONTROL REGISTER RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C0204++0x03
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line.long 0x00 "CKGEN_GLB_CTL,CKGEN GLOBAL CONTROL REGISTER"
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bitfld.long 0x00 28.--31. " CLK_24M_DIV_C_NUM ,clock 24m DIvider c DIvide number DIvided clock frequency is 24M/(clk_24m_DIv_c_num+1)/4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 18.--27. 1. " CLK_24M_DIV_B_NUM ,clock 24m DIvider b DIvide number DIvided clock frequency is 24M/(clk_24m_DIv_b_num+1)/2"
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hexmask.long.word 0x00 3.--12. 1. " clk_24m_DIv_a_num ,clock 24m DIvider a DIvide number DIvided clock frequency is 24M/(clk_24m_DIv_a_num+1)/2"
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bitfld.long 0x00 2. " CLK_24M_DIV_C_DIS ,clock 24m DIvider c which is used for pcg/bcg/ccg clock active monitor golden clock DIsable. 1. clock 24m DIvider DIsable. 0. clock 24m DIvider enable." "0,1"
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textline " "
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bitfld.long 0x00 1. "CLK_24M_DIV_B_DIS ,clock 24m DIvider b which is used for frequency monitor golden clock DIsable. 1. clock 24m DIvider DIsable. 0. clock 24m DIvider enable." "0,1"
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bitfld.long 0x00 0. " CLK_24M_DIV_A_DIS ,clock 24m DIvider a which is used for frequency monitor golden clock DIsable. 1. clock 24m DIvider DIsable. 0. clock 24m DIvider enable." "0,1"
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group ad:0xF30C0300++0x03
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line.long 0x00 "CKGEN_SUP_DOM,CKGEN SUPER DOMAIN REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock the entire register" "0,1"
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bitfld.long 0x00 5.--6. " PPROT ,pprot for super doman" "0,1,2,3"
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bitfld.long 0x00 4. " SEC_EN ,check pprot enable" "0,1"
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bitfld.long 0x00 0.--3. " DID ,super domain domain id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C0400++0x03
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line.long 0x00 "CKGEN_RES_RS,CKGEN RESERVE REGISTER RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C0404++0x03
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line.long 0x00 "CKGEN_RES,CKGEN RESERVE REGISTER"
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hexmask.long 0x00 0.--31. 1. " RES ,bit[31:2]: reserve register for future use bit[1]: sp cpu/axi/apb clock ratio select 0: 4/2/1 1: 2/2/1 bit[0]: sf cpu/axi/apb clock ratio select 0: 4/2/1 1: 2/2/1"
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group ad:0xF30C0500++0x03
|
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line.long 0x00 "CKGEN_MISC_RS,CKGEN MISC REGISTER RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C0504++0x03
|
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line.long 0x00 "CKGEN_MISC,CKGEN MISC REGISTER"
|
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hexmask.long 0x00 0.--31. 1. " MISC ,bit[31:1]: reserved bit[0]: enable for permission error as apbslverr"
|
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group ad:0xF30C0508++0x03
|
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line.long 0x00 "CKGEN_MISC_MON,CKGEN MISC MONITOR REGISTER"
|
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hexmask.long 0x00 0.--31. 1. " MON ,ckgen misc monitor: bit[21:18]: swm o bit[17]: swm ack bit[16:13]: swm i bit12: swm req bit11: rsv bit10: slp complete bit 9: hib complete bit8: run complete bit7: rtc status bit6: slp status bit5: hib status bit4: run status bit[3.."
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group ad:0xF30C1000++0x03
|
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
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group ad:0xF30C1004++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
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textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
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group ad:0xF30C1008++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C100C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1010++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1014++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C1018++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
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|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C101C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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|
group ad:0xF30C1020++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C1024++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C1028++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C102C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1030++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1034++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C1038++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C103C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1040++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1044++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1048++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C104C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1050++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1054++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1058++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C105C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1060++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1064++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
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|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C1068++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
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|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C106C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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|
group ad:0xF30C1070++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C1074++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1078++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C107C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1080++0x03
|
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C1084++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1088++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C108C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1090++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1094++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1098++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C109C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C10A0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C10A4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C10A8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C10AC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C10B0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C10B4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C10B8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C10BC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C10C0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C10C4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C10C8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C10CC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C10D0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C10D4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C10D8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C10DC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C10E0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C10E4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C10E8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C10EC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C10F0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C10F4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C10F8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C10FC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1100++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1104++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C1108++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C110C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1110++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1114++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1118++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C111C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1120++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1124++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1128++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C112C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1130++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1134++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1138++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C113C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1140++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1144++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1148++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C114C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C1150++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C1154++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1158++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C115C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C1160++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C1164++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1168++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C116C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C1170++0x03
|
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C1174++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C1178++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C117C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1180++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1184++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1188++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C118C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1190++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1194++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1198++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C119C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C11A0++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C11A4++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C11A8++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C11AC++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C11B0++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C11B4++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C11B8++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C11BC++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C11C0++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C11C4++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C11C8++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C11CC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C11D0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C11D4++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C11D8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C11DC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C11E0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C11E4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C11E8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C11EC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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|
group ad:0xF30C11F0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C11F4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C11F8++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C11FC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1200++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1204++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C1208++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C120C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1210++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1214++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1218++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C121C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1220++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1224++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1228++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C122C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1230++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1234++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
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|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C1238++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
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|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C123C++0x03
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|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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|
group ad:0xF30C1240++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C1244++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1248++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C124C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1250++0x03
|
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C1254++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1258++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C125C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1260++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1264++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1268++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C126C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1270++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1274++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1278++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C127C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1280++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C1284++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
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|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1288++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
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|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C128C++0x03
|
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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|
group ad:0xF30C1290++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C1294++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1298++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C129C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C12A0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C12A4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C12A8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C12AC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C12B0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C12B4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C12B8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C12BC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C12C0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C12C4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C12C8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C12CC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C12D0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C12D4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C12D8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C12DC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C12E0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C12E4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C12E8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C12EC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C12F0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C12F4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C12F8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C12FC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1300++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1304++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1308++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C130C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1310++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1314++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1318++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C131C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C1320++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C1324++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1328++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C132C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C1330++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C1334++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1338++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C133C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C1340++0x03
|
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C1344++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C1348++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C134C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1350++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1354++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C1358++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C135C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C1360++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C1364++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1368++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C136C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C1370++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C1374++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1378++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C137C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C1380++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C1384++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1388++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C138C++0x03
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line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C1390++0x03
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line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C1394++0x03
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C1398++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C139C++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C13A0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C13A4++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C13A8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C13AC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C13B0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C13B4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C13B8++0x03
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|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
textline " "
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|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C13BC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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|
group ad:0xF30C13C0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
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|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C13C4++0x03
|
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line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
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|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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|
textline " "
|
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C13C8++0x03
|
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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|
group ad:0xF30C13CC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C13D0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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|
group ad:0xF30C13D4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C13D8++0x03
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line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C13DC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C13E0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C13E4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C13E8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C13EC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C13F0++0x03
|
|
line.long 0x00 "IP_SLICE_RS,CKGEN IP SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C13F4++0x03
|
|
line.long 0x00 "IP_SLICE_CTL,CKGEN IP SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIv_num ,ip slice DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF30C13F8++0x03
|
|
line.long 0x00 "IP_SLICE_MON_CTL,CKGEN IP SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C13FC++0x03
|
|
line.long 0x00 "IP_SLICE_MON_THRD,CKGEN IP SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C2000++0x03
|
|
line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C2004++0x03
|
|
line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2008++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C200C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C2010++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2014++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2018++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C201C++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2020++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2024++0x03
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2028++0x03
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C202C++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2030++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2034++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C2038++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C203C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2040++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2044++0x03
|
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2048++0x03
|
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C204C++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2050++0x03
|
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C2054++0x03
|
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
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textline " "
|
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2058++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C205C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C2060++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2064++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2068++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C206C++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2070++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2074++0x03
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2078++0x03
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C207C++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2080++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2084++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C2088++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C208C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2090++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2094++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2098++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C209C++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C20A0++0x03
|
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C20A4++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C20A8++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C20AC++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C20B0++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C20B4++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C20B8++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C20BC++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C20C0++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C20C4++0x03
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C20C8++0x03
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C20CC++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C20D0++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C20D4++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C20D8++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C20DC++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C20E0++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C20E4++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C20E8++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C20EC++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C20F0++0x03
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C20F4++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C20F8++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C20FC++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C2100++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2104++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2108++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C210C++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2110++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2114++0x03
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2118++0x03
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C211C++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2120++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2124++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C2128++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C212C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2130++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2134++0x03
|
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
|
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2138++0x03
|
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
|
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C213C++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
|
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2140++0x03
|
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C2144++0x03
|
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2148++0x03
|
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C214C++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
|
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C2150++0x03
|
|
line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
|
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2154++0x03
|
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2158++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C215C++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2160++0x03
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2164++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2168++0x03
|
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line.long 0x00 "BUS_SLICE_RS,CKGEN BUS SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C216C++0x03
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line.long 0x00 "BUS_SLICE_CTL,CKGEN BUS SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of pre_en after .." "0,1"
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bitfld.long 0x00 28. " DIV_CHG_BUSY ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "POST_MUX_D0_ACTIVE ,post glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 26. " PRE_MUX_D0_ACTIVE ,pre glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIV_NUM ,bus slice pre DIvider number. ip slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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textline " "
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bitfld.long 0x00 6. "DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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bitfld.long 0x00 5. " main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--3. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4 as sync_DIv input bit3: select ck_in3 as clk_out0, otherwise clk_out0 is from clk_out_m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2170++0x03
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line.long 0x00 "BUS_SLICE_SYNC_CTL,CKGEN BUS SLICE SYNC DIVIDER CONTROL REGISTER"
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bitfld.long 0x00 31. " DIv_q_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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bitfld.long 0x00 30. " DIv_p_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 29. " DIv_n_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active.." "0,1"
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bitfld.long 0x00 28. " DIv_m_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 12.--15. "DIV_Q_NUM ,q DIvider DIvide number. clk_out_q frequency should be: sync_DIv input frequency/(DIv_q_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DIV_P_NUM ,p DIvider DIvide number. clk_out_p frequency should be: sync_DIv input frequency/(DIv_p_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DIV_N_NUM ,n DIvider DIvide number. clk_out_n frequency should be: sync_DIv input frequency/(DIv_n_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " DIv_m_num ,m DIvider DIvide number. clk_out_m frequency should be: sync_DIv input frequency/(DIv_m_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF30C2174++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_0,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER"
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bitfld.long 0x00 11. " freq_mon_3_upd ,clk_out_3 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 10. " freq_mon_2_upd ,clk_out_2 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 9. " freq_mon_1_upd ,clk_out_1 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 8. " freq_mon_0_upd ,clk_out_0 frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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textline " "
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bitfld.long 0x00 5. "MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 3. " slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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textline " "
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bitfld.long 0x00 1. "active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C2178++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_1,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 1"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_1 ,clk_out_1 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_0 ,clk_out_0 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C217C++0x03
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line.long 0x00 "BUS_SLICE_MON_CTL_2,CKGEN BUS SLICE CLOCK MONITOR CONTROL REIGSTER 2"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon_3 ,clk_out_3 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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hexmask.long.word 0x00 0.--15. 1. " freq_mon_2 ,clk_out_2 recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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group ad:0xF30C2180++0x03
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line.long 0x00 "BUS_SLICE_MON_0_THRD,CKGEN IP SLICE CLOCK OUT 0 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2184++0x03
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line.long 0x00 "BUS_SLICE_MON_1_THRD,CKGEN IP SLICE CLOCK OUT 1 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C2188++0x03
|
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line.long 0x00 "BUS_SLICE_MON_2_THRD,CKGEN IP SLICE CLOCK OUT 2 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C218C++0x03
|
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line.long 0x00 "BUS_SLICE_MON_3_THRD,CKGEN IP SLICE CLOCK OUT 3 MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C3000++0x03
|
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line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C3004++0x03
|
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line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C3008++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
|
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C300C++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C3010++0x03
|
|
line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C3014++0x03
|
|
line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
|
|
bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
|
|
bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
|
|
bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
|
|
bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
|
|
bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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|
group ad:0xF30C3018++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
|
|
bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
|
|
bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
|
|
bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C301C++0x03
|
|
line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
|
|
group ad:0xF30C3020++0x03
|
|
line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C3024++0x03
|
|
line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C3028++0x03
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line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C302C++0x03
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line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C3030++0x03
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line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C3034++0x03
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line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C3038++0x03
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line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C303C++0x03
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line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C3040++0x03
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line.long 0x00 "CORE_SLICE_RS,CKGEN CORE SLICE CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C3044++0x03
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line.long 0x00 "CORE_SLICE_CTL,CKGEN CORE SLICE CONTROL REGISTER"
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bitfld.long 0x00 31. " HW_CG_EN_STATUS ,hw gating enable status. 1. hw clock gating not active. 0. hw clock gating active, hw turn off slice clock." "0,1"
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bitfld.long 0x00 30. " MAIN_EN_STATUS ,main_en status. since main_en is from pclk domain it need to sync to ck_in4, this bit is used to inDIcate main_en is synchronized to ck_in4. make sure this bit is the same value of main_en after program to main_en.." "0,1"
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bitfld.long 0x00 29. " PRE_EN_STATUS ,pre_en status. since pre_en is from pclk domain it need to sync to ck_in0 to ck_in3 mux, this bit is used to inDIcate pre_en is synchronized to ck_in0 to ck_in3 mux. make sure this bit is the same value of main_en after .." "0,1"
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bitfld.long 0x00 28. " DIv_chg_busy ,since DIv_num can be updated on-the-fly, this bit used to inDIcate the new DIv_num is active or not. 1. DIvider change busy, the new DIv_num is not active 0. DIvider change idle, the new DIv_num is active" "0,1"
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textline " "
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bitfld.long 0x00 27. "MUX_D0_ACTIVE ,glitch free mux d0 active inDIcate 1: d0 active 0: d1 active" "0,1"
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bitfld.long 0x00 8.--12. " DIv_num ,core slice DIvider number. core slice output frequency should be: frequency of selected clock source / (DIv_num+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. " HW_DIS_EN ,all lef cg turn off, then slice automatically gated off enable. 1: enable 0: DIable" "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug output clock gating enable. 1. debug enable 0. debug DIsable" "0,1"
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textline " "
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bitfld.long 0x00 5. "main_en ,gating enable for ck_in4 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 4. " pre_en ,gating enable for ck_in0 to ck_in3 mux 1. clock active 0. clock gated" "0,1"
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bitfld.long 0x00 0.--2. " clk_src_sel ,clock source select. bit[1:0]: select from ck_in0 to ck_in3 bit2: select ck_in4" "0,1,2,3,4,5,6,7"
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group ad:0xF30C3048++0x03
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line.long 0x00 "CORE_SLICE_MON_CTL,CKGEN CORE SLICE CLOCK MONITOR CONTROL REIGSTER"
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hexmask.long.word 0x00 16.--31. 1. " freq_mon ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
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bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
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bitfld.long 0x00 8. " freq_mon_upd ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
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bitfld.long 0x00 4. " hib_exp ,hibernate mode expect status 1: expect to be on 0: expect to be off" "0,1"
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textline " "
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bitfld.long 0x00 3. "slp_exp ,sleep mode expect status 1: expect to be on 0: expect to be off" "0,1"
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bitfld.long 0x00 2. " mon_clk_src_sel ,frequency monitor clock source select. need to config before mon_en set to 1 0: clk_mon_a 1: clk_mon_b" "0,1"
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bitfld.long 0x00 1. " active_DIsable ,clock active detection error DIsable, the detection result will recorded in active_status register bit, but error will not reported 1. DIsable 0. enable" "0,1"
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bitfld.long 0x00 0. " mon_en ,frequency monitor enable, it will enable clock active monitor and frequency monitor 1. enable 0. DIsable" "0,1"
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group ad:0xF30C304C++0x03
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line.long 0x00 "CORE_SLICE_MON_THRD,CKGEN CORE SLICE CLOCK MONITOR THRESHOLD REGISTER"
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hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,clock frequency check high threshold"
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hexmask.long.word 0x00 0.--15. 1. " low_thrd ,clock frequency check low threshold"
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group ad:0xF30C4000++0x03
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line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C4004++0x03
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line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
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bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
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bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
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bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
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textline " "
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bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
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bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
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group ad:0xF30C4008++0x03
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line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C400C++0x03
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line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
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bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
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bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
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bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
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textline " "
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bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
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bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
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group ad:0xF30C4010++0x03
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line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C4014++0x03
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line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
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bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
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bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
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bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
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textline " "
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bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
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bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
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group ad:0xF30C4018++0x03
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line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C401C++0x03
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line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
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bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
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bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
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bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
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textline " "
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bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
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bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
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group ad:0xF30C4020++0x03
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line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30C4024++0x03
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line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
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bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
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bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
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bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
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bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
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textline " "
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bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
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bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4028++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C402C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4030++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C4034++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4038++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C403C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4040++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C4044++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4048++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C404C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4050++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C4054++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4058++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C405C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4060++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C4064++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4068++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C406C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4070++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C4074++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4078++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C407C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4080++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C4084++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4088++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C408C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4090++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C4094++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C4098++0x03
|
|
line.long 0x00 "PCG_RS,CKGEN PCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C409C++0x03
|
|
line.long 0x00 "PCG_CTL,CKGEN PCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5000++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5004++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5008++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C500C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5010++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5014++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5018++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C501C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5020++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5024++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5028++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C502C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5030++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5034++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5038++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C503C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5040++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5044++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5048++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C504C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5050++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5054++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5058++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C505C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5060++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5064++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5068++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C506C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5070++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5074++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5078++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C507C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5080++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5084++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5088++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C508C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5090++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C5094++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C5098++0x03
|
|
line.long 0x00 "BCG_RS,CKGEN BCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C509C++0x03
|
|
line.long 0x00 "BCG_CTL,CKGEN BCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode bcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6000++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6004++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6008++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C600C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6010++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6014++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6018++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C601C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6020++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6024++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6028++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C602C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6030++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6034++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6038++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C603C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6040++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6044++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6048++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C604C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6050++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6054++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6058++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C605C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6060++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6064++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6068++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C606C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6070++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6074++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6078++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C607C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6080++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6084++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6088++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C608C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6090++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C6094++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C6098++0x03
|
|
line.long 0x00 "CCG_RS,CKGEN CCG CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C609C++0x03
|
|
line.long 0x00 "CCG_CTL,CKGEN CCG CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " LP_MASK ,lower power mask bit. 1: this cg status is ignored under low power handshake 0: this cg status is considerd into low power handshake. Only when all cg status with lp_mask 0 are DIsabled under low power, the corresponDIng module .." "0,1"
|
|
bitfld.long 0x00 6. " DBG_EN ,debug clock enable" "0,1"
|
|
bitfld.long 0x00 5. " CG_GATED ,cg gated status 1: gated 0: active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE_MON_STA ,active monitor status 1: clock active 0: clock gated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "ACTIVE_MON_EN ,active monitor enable" "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,slp mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hib mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode ccg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C7000++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C7004++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C7008++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C700C++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C7010++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C7014++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C7018++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C701C++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C7020++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C7024++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C7028++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C702C++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C7030++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C7034++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C7038++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C703C++0x03
|
|
line.long 0x00 "PLL_RS,CKGEN PLL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C7040++0x03
|
|
line.long 0x00 "PLL_CTL,CKGEN PLL CONTROL REGISTER"
|
|
bitfld.long 0x00 6. " PD_SLP_MODE ,slp mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 5. " PD_HIB_MODE ,hib mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 4. " PD_RUN_MODE ,run mode power down 0: power on 1: power down" "0,1"
|
|
bitfld.long 0x00 3. " ignore_pll ,ignore pll 1: ignore 0: involve pll" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CLK_SLP_MODE ,slp mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " CLK_HIB_MODE ,hib mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " CLK_RUN_MODE ,run mode pll clock on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C7044++0x03
|
|
line.long 0x00 "PLL_MON_CTL,CKGEN PLL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " pll_clk_rdy ,pll clock ready inDIcator" "0,1"
|
|
hexmask.long.word 0x00 8.--23. 1. " TOUT_VAL ,timeout value between power on/enable to pll clock ready. tout_val can be changed on-the-fly, but it is reconmended to change it after set mon_en to 1'b0."
|
|
bitfld.long 0x00 0. " MON_EN ,PLL ready check enable when pll from DIsable to enable or from power down to power on by ckgen. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C7500++0x03
|
|
line.long 0x00 "XTAL_RS,CKGEN XTAL CONTROL RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C7504++0x03
|
|
line.long 0x00 "XTAL_CTL,CKGEN XTAL CONTROL REGISTER"
|
|
bitfld.long 0x00 3. " ignore_xtal ,ignore xtal. 1: xtal ignore 0: involve xtal" "0,1"
|
|
bitfld.long 0x00 2. " slp_mode ,slp mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " hib_mode ,hib mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " run_mode ,run mode pcg on/off setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30C7508++0x03
|
|
line.long 0x00 "XTAL_MON_CTL,CKGEN XTAL MONITOR CONTROL REIGSTER"
|
|
bitfld.long 0x00 31. " xtal_clk_active ,xtal24m clock active, as fs_24m clock output inDIcator" "0,1"
|
|
bitfld.long 0x00 30. " rc24m_clk_active ,rc24m clock active, as fs_24m clock output inDIcator" "0,1"
|
|
bitfld.long 0x00 29. " xtal_clk_rdy ,xtal24m clock ready inDIcator" "0,1"
|
|
bitfld.long 0x00 28. " rc24m_clk_rdy ,rc24m clock ready inDIcator" "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--23. 1. "TOUT_VAL ,timeout value between power on/enable to pll clock ready. this can only be changed after mon_en change to 0."
|
|
bitfld.long 0x00 1. " MON_EN_STA ,mon_en status. set mon_en, then check mon_en_sta to make sure mon_en setting is active." "0,1"
|
|
bitfld.long 0x00 0. " MON_EN ,xtal ready check enable from ckgen DIsable xtal to enable xtal. 1. enable 0. DIsable" "0,1"
|
|
group ad:0xF30C8000++0x03
|
|
line.long 0x00 "DBG_MON_RS,CKGEN DEBUG AND MONITOR RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30C8004++0x03
|
|
line.long 0x00 "DBG_MON_CLK_SRC,CKGEN DEBUG AND MONITOR CLOCK SOURCE SELECT REGISTER"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EXT_CLK_SRC_SEL ,ext clock source select, accorDIng to ext clock monitor index"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CORE_CLK_SRC_SEL ,core clock source select, accorDIng to core slice index"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BUS_CLK_SRC_SEL ,bus clock source select, accorDIng to bus slice index"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IP_CLK_SRC_SEL ,ip clock source select, accorDIng to ip slice index"
|
|
group ad:0xF30C8008++0x03
|
|
line.long 0x00 "DBG_MON_CTL,CKGEN DEBUG MONITOR CONTROL REGISTER"
|
|
bitfld.long 0x00 3.--4. " CLK_SEL ,debug and monitor and cqm clock source select. 2'b00: ip slice clock output 2'b01: bus slice clock output 2'b10: core slice clock output 2'b11: ext clock input" "0,1,2,3"
|
|
bitfld.long 0x00 2. " CQM_GATING_EN ,cqm gating enable 1: not gated 0: gated" "0,1"
|
|
bitfld.long 0x00 1. " MON_GATING_EN ,monitor gating enable 1: not gated 0: gated" "0,1"
|
|
bitfld.long 0x00 0. " DBG_GATING_EN ,dbg gating enable 1: not gated 0: gated" "0,1"
|
|
group ad:0xF30C800C++0x03
|
|
line.long 0x00 "DBG_CTL,CKGEN DEBUG CONTROL REGISTER"
|
|
bitfld.long 0x00 0.--3. " DIV_NUM ,debug clock output to pad DIvider number debug clock output frequency equals to: clock source/(DIV_NUM+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30C8010++0x03
|
|
line.long 0x00 "MON_CTL,CKGEN MONITOR CONTROL REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " FREQ_MON ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * (24M/(clk_24m_DIv_num+1)/2)"
|
|
bitfld.long 0x00 9. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 8. " FREQ_MON_UPD ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 2. " ACTIVE_LOSS_DIS ,active monitor clock loss DIsable. 1: DIsable 0: enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "MON_CLK_SRC_SEL ,reference clock source select. 0: from clk_mon_a 1: from clk_mon_b" "0,1"
|
|
bitfld.long 0x00 0. " MON_EN ,frequency monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF30C8014++0x03
|
|
line.long 0x00 "MON_CHK_THRD,MONITOR CHECK THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,high threshold. violation happends when frequency counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when frequency counter less than Low register"
|
|
group ad:0xF30C8020++0x03
|
|
line.long 0x00 "LOW_SPD_CHK_CTL,CKGEN 24M AND 32K CHECK REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " FREQ_MON ,recorded frequency, can be cleared by software by programming it to all 0, the frequency is freq_mon * 32K"
|
|
bitfld.long 0x00 15. " MON_EN_STA ,mon_en status, check this bit to confirm after write mon_en register bit" "0,1"
|
|
bitfld.long 0x00 14. " FREQ_MON_UPD ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
hexmask.long.byte 0x00 8.--13. 1. " 32K_SRC_SEL ,32k clock source select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 2.--7. 1. "24M_SRC_SEL ,24m clock source select"
|
|
bitfld.long 0x00 1. " MON_EN ,frequency monitor enable 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " CLK_LOSS_DIS ,24m loss check DIsable 1: DIsable 0: enable" "0,1"
|
|
group ad:0xF30C8024++0x03
|
|
line.long 0x00 "LOW_SPD_CHK_THRD,CKGEN 24M AND 32K CHECK THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,high threshold. violation happends when frequency counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when frequency counter less than Low register"
|
|
group ad:0xF30C8040++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF30C8044++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF30C8048++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF30C804C++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF30C8050++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF30C8054++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF30C8058++0x03
|
|
line.long 0x00 "CQM_CTL,CKGEN QUALITY MONITOR CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 9.--14. 1. " DUTY_RATE ,duty error rate. duty error will happen when duty DIfference is larger than (duty_rate/64), jitter_rate 0 is used for test"
|
|
hexmask.long.byte 0x00 3.--8. 1. " JITTER_RATE ,jitter error rate. jitter error will happen when adjacent jitter is larger than (jitter_rate/64), jitter_rate 0 is used for test"
|
|
bitfld.long 0x00 1.--2. " SRC_SEL ,delay source select for each data analyzer 00: 2 delay cells 01: 4 delay cells 10: 6 delay cells 11: 8 delay cells" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MON_EN ,cqm monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF30CA000++0x03
|
|
line.long 0x00 "CKGEN_FUSA_RS,CKGEN FUSA RELATED REGISTER RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30CA004++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 23. " PADDR_INT_CLR ,paddr uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 22. " PUSER_INT_CLR ,puser uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 21. " PCTRL1_INT_CLR ,pctrl1 uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 20. " PCTRL0_INT_CLR ,pctrl0 uncorrectable error interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "PWDAT_C_INT_CLR ,pwdata correctable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " PWDAT_U_INT_CLR ,pwdata uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " PWDAT_F_INT_CLR ,pwdata fatal error interrupt clear" "0,1"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. "PUSER_INT_STA ,puser uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 11. " PWDAT_C_INT_STA ,pwdata correctable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status." "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. " PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF30CA008++0x03
|
|
line.long 0x00 "APB_LKSTEP_INT,APB LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 19. " SYNC_ERR_INT_CLR ,sync error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " RESP_ERR_INT_CLR ,response parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " REQ_ERR_INT_CLR ,request parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 16. " CMP_ERR_INT_CLR ,lockstep compare interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "SYNC_ERR_INT_STA ,sync error status" "0,1"
|
|
bitfld.long 0x00 10. " RESP_ERR_INT_STA ,response parity error status" "0,1"
|
|
bitfld.long 0x00 9. " REQ_ERR_INT_STA ,request parity error status" "0,1"
|
|
bitfld.long 0x00 8. " CMP_ERR_INT_STA ,lockstep compare error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SYNC_ERR_INT_EN ,apb sync error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " RESP_ERR_INT_EN ,apb response parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " REQ_ERR_INT_EN ,apb request parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_ERR_INT_EN ,lockstep compare interrupt enable" "0,1"
|
|
group ad:0xF30CA00C++0x03
|
|
line.long 0x00 "WDT_LKSTEP_INT,WDT LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 17. " SYNC_ERR_INT_CLR ,sync error interrupt clear" "0,1"
|
|
bitfld.long 0x00 16. " CMP_ERR_INT_CLR ,lockstep compare interrupt clear" "0,1"
|
|
bitfld.long 0x00 9. " SYNC_ERR_INT_STA ,sync error status" "0,1"
|
|
bitfld.long 0x00 8. " CMP_ERR_INT_STA ,lockstep compare error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SYNC_ERR_INT_EN ,wdt sync error interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_ERR_INT_EN ,lockstep compare interrupt enable" "0,1"
|
|
group ad:0xF30CA100++0x03
|
|
line.long 0x00 "CKGEN_FUSA_INT,CKGEN INTERNAL FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 19. " LKSTEP_CMP_ERR_CLR ,rstgen core lockstep compare error clear" "0,1"
|
|
bitfld.long 0x00 18. " SYNC_ERR_CLR ,internal sync check error clear" "0,1"
|
|
bitfld.long 0x00 17. " SWM_TRANS_ERR_CLR ,swm transfer error clear" "0,1"
|
|
bitfld.long 0x00 16. " SWM_CHK_ERR_CLR ,swm one hot check error clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LKSTEP_CMP_ERR_STA ,rstgen core lockstep compare error status" "0,1"
|
|
bitfld.long 0x00 10. " SYNC_ERR_STA ,internal sync check error status" "0,1"
|
|
bitfld.long 0x00 9. " SWM_TRANS_ERR_STA ,swm transfer error status" "0,1"
|
|
bitfld.long 0x00 8. " SWM_CHK_ERR_STA ,swm one hot check error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "LKSTEP_CMP_ERR_EN ,rstgen core lockstep compare error enable" "0,1"
|
|
bitfld.long 0x00 2. " SYNC_ERR_EN ,internal sync check error enable" "0,1"
|
|
bitfld.long 0x00 1. " SWM_TRANS_ERR_EN ,swm transfer error enable" "0,1"
|
|
bitfld.long 0x00 0. " SWM_CHK_ERR_EN ,swm one hot check error enable" "0,1"
|
|
group ad:0xF30CA200++0x03
|
|
line.long 0x00 "CKGEN_INJ_EN,CKGEN ERROR INJECTION ENABLE"
|
|
hexmask.long.word 0x00 0.--15. 1. " INJ_EN ,error injection enable bit[0]: irq error injection enable. bit[1]: ckgen lkstep error injection enable. bit[2]: aapb lkstep error injection enable bit[3]: aapb req ded error injection enable. bit[4]: aapb output error injection.."
|
|
group ad:0xF30CA204++0x03
|
|
line.long 0x00 "CKGEN_INJ_BIT,CKGEN ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 29.--31. " IRQ_INJ ,irq inj: bit0: inj for unc_irq bit1: inj for cor_irq bit2: inj for ckgen_irq" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ERR_INJ_BIT ,error injection bit bit[3:0]: aapb resp ded error injection bit. bit[20:8]: ckgen lkstep error injection bit. bit[28:21]: ckgen dout error injection bit."
|
|
group ad:0xF30CA208++0x03
|
|
line.long 0x00 "CKGEN_INJ_BIT_1,CKGEN ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_BIT ,error injection bit bit[7:0]: aapb lkstep injection bit. bit[11:8]: aapb req ded error injection bit. bit[15:12]: aapb output error injection bit."
|
|
group ad:0xF30CA20C++0x03
|
|
line.long 0x00 "CKGEN_INJ_BIT_2,CKGEN ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_BIT ,error injection bit"
|
|
group ad:0xF30CA300++0x03
|
|
line.long 0x00 "IP_CLK_COR_EN_0,IP SLICE FREQUENCY CHECK CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,ip slice frequency check correctable error enable"
|
|
group ad:0xF30CA304++0x03
|
|
line.long 0x00 "IP_CLK_UNC_EN_0,IP SLICE FREQUENCY CHECK UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " int_en ,ip slice frequency check uncorrectable error enable"
|
|
group ad:0xF30CA308++0x03
|
|
line.long 0x00 "IP_CLK_INT_STA_0,IP SLICE FREQUENCY CHECK ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
group ad:0xF30CA30C++0x03
|
|
line.long 0x00 "IP_CLK_COR_EN_1,IP SLICE FREQUENCY CHECK CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,ip slice frequency check correctable error enable"
|
|
group ad:0xF30CA310++0x03
|
|
line.long 0x00 "IP_CLK_UNC_EN_1,IP SLICE FREQUENCY CHECK UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " int_en ,ip slice frequency check uncorrectable error enable"
|
|
group ad:0xF30CA314++0x03
|
|
line.long 0x00 "IP_CLK_INT_STA_1,IP SLICE FREQUENCY CHECK ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,ip slice frequency check uncorrectable error status" "0,1"
|
|
group ad:0xF30CA400++0x03
|
|
line.long 0x00 "BUS_CLK_COR_EN_0,BUS SLICE FREQUENCY CHECK CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,bus slice frequency check correctable error enable"
|
|
group ad:0xF30CA404++0x03
|
|
line.long 0x00 "BUS_CLK_UNC_EN_0,BUS SLICE UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,bus slice frequency check uncorrectable error enable"
|
|
group ad:0xF30CA408++0x03
|
|
line.long 0x00 "BUS_CLK_INT_STA_0,BUS SLICE FREQUENCY CHECK ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,bus slice frequency check uncorrectable error status" "0,1"
|
|
group ad:0xF30CA500++0x03
|
|
line.long 0x00 "CORE_CLK_COR_EN_0,CORE SLICE CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,core slice frequency check correctable error enable"
|
|
group ad:0xF30CA504++0x03
|
|
line.long 0x00 "CORE_CLK_UNC_EN_0,CORE SLICE FREQUENCY CHECK UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,core slice frequency check uncorrectable error enable"
|
|
group ad:0xF30CA508++0x03
|
|
line.long 0x00 "CORE_CLK_INT_STA_0,CORE SLICE FREQUENCY CHECK ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,core slice frequency check uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,core slice frequency check uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,core slice frequency check uncorrectable error status" "0,1"
|
|
group ad:0xF30CA600++0x03
|
|
line.long 0x00 "PCG_COR_EN_0,PCG ACTIVE MONITOR CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,pcg active monitor check correctable error enable"
|
|
group ad:0xF30CA604++0x03
|
|
line.long 0x00 "PCG_UNC_EN_0,PCG ACTIVE MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,pcg active monitor uncorrectable error enable"
|
|
group ad:0xF30CA608++0x03
|
|
line.long 0x00 "PCG_INT_STA_0,PCG ACTIVE MONITOR ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,active monitor uncorrectable error status" "0,1"
|
|
group ad:0xF30CA700++0x03
|
|
line.long 0x00 "BCG_COR_EN_0,BCG ACTIVE MONITOR CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,bcg active monitor check correctable error enable"
|
|
group ad:0xF30CA704++0x03
|
|
line.long 0x00 "BCG_UNC_EN_0,BCG ACTIVE MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,bcg active monitor uncorrectable error enable"
|
|
group ad:0xF30CA708++0x03
|
|
line.long 0x00 "BCG_INT_STA_0,BCG ACTIVE MONITOR ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,active monitor uncorrectable error status" "0,1"
|
|
group ad:0xF30CA800++0x03
|
|
line.long 0x00 "CCG_COR_EN_0,CCG ACTIVE MONITOR CORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,ccg active monitor check correctable error enable"
|
|
group ad:0xF30CA804++0x03
|
|
line.long 0x00 "CCG_UNC_EN_0,CCG ACTIVE MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,ccg active monitor uncorrectable error enable"
|
|
group ad:0xF30CA808++0x03
|
|
line.long 0x00 "CCG_INT_STA_0,CCG ACTIVE MONITOR ERROR STATUS"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,active monitor uncorrectable error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,active monitor uncorrectable error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,active monitor uncorrectable error status" "0,1"
|
|
group ad:0xF30CA904++0x03
|
|
line.long 0x00 "PLL_UNC_EN,PLL MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INT_EN ,pll monitor uncorrectable error enable. bit[7:3]: reserved. bit[2:0]: pll"
|
|
group ad:0xF30CA908++0x03
|
|
line.long 0x00 "PLL_INT_STA,PLL MONITOR ERROR STATUS REGISTER"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,pll monitor timeout error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,pll monitor timeout error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,pll monitor timeout error status" "0,1"
|
|
group ad:0xF30CAA04++0x03
|
|
line.long 0x00 "XTAL_UNC_EN,XTAL MONITOR UNCORRECTABLE ERROR ENABLE"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INT_EN ,xtal monitor uncorrectable error enable. bit[7:1]: reserved. bit[0]: enable"
|
|
group ad:0xF30CAA08++0x03
|
|
line.long 0x00 "XTAL_INT_STA,XTAL MONITOR ERROR STATUS REGISTER"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,xtal monitor timeout error status" "0,1"
|
|
group ad:0xF30CAB00++0x03
|
|
line.long 0x00 "MON_COR_EN,CKGEN MONITOR CORRECTABLE ERROR ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " INT_EN ,ckgen monitor correctable error enable" "0,1"
|
|
group ad:0xF30CAB04++0x03
|
|
line.long 0x00 "MON_UNC_EN,CKGEN MONITOR UNCORRECTABLE ERROR ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " INT_EN ,ckgen monitor uncorrectable error enable" "0,1"
|
|
group ad:0xF30CAB08++0x03
|
|
line.long 0x00 "MON_INT_STA,CKGEN MONITOR INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 0. " INT_STA ,ckgen monitor interrupt status write it to 0 to clear it" "0,1"
|
|
group ad:0xF30CAC00++0x03
|
|
line.long 0x00 "LOW_SPD_COR_EN,CKGEN LOW SPEED CHECK CORRECTABLE ERROR ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " INT_EN ,ckgen low speed monitor correctable error enable" "0,1"
|
|
group ad:0xF30CAC04++0x03
|
|
line.long 0x00 "LOW_SPD_UNC_EN,CKGEN LOW SPEED CHECK UNCORRECTABLE ERROR ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " INT_EN ,ckgen low speed monitor uncorrectable error enable" "0,1"
|
|
group ad:0xF30CAC08++0x03
|
|
line.long 0x00 "LOW_SPD_INT_STA,CKGEN LOW SPEED CHECK INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 0. " INT_STA ,ckgen low speed monitor interrupt status write it to 0 to clear it" "0,1"
|
|
group ad:0xF30CAD00++0x03
|
|
line.long 0x00 "CQM_COR_EN,CQM CORRECTABLE ERROR ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,cqm correctable error enable"
|
|
group ad:0xF30CAD04++0x03
|
|
line.long 0x00 "CQM_UNC_EN,CQM UNCORRECTABLE ERROR ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,cqm uncorrectable error enable"
|
|
group ad:0xF30CAD08++0x03
|
|
line.long 0x00 "CQM_DUTY_INT_STA,CQM DUTY ERROR INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,cqm_x duty error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,cqm_x duty error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,cqm_x duty error status" "0,1"
|
|
group ad:0xF30CAD0C++0x03
|
|
line.long 0x00 "CQM_JITTER_INT_STA,CQM JITTER ERROR INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 31. " INT_STA_31 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 30. " INT_STA_30 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 29. " INT_STA_29 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 28. " INT_STA_28 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "INT_STA_27 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 26. " INT_STA_26 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 25. " INT_STA_25 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 24. " INT_STA_24 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "INT_STA_23 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 22. " INT_STA_22 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 21. " INT_STA_21 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 20. " INT_STA_20 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "INT_STA_19 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 18. " INT_STA_18 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 17. " INT_STA_17 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 16. " INT_STA_16 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "INT_STA_15 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 14. " INT_STA_14 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 13. " INT_STA_13 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 12. " INT_STA_12 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "INT_STA_11 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 10. " INT_STA_10 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 9. " INT_STA_9 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 8. " INT_STA_8 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "INT_STA_7 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 6. " INT_STA_6 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 5. " INT_STA_5 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 4. " INT_STA_4 ,cqm_x jitter error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "INT_STA_3 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 2. " INT_STA_2 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 1. " INT_STA_1 ,cqm_x jitter error status" "0,1"
|
|
bitfld.long 0x00 0. " INT_STA_0 ,cqm_x jitter error status" "0,1"
|
|
group ad:0xF30CB000++0x03
|
|
line.long 0x00 "CKGEN_FUNC_INT_RS,This register is used for assign rule space for rstgen function interrupt register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30CB004++0x03
|
|
line.long 0x00 "CKGEN_FUNC_INT,CKGEN FUNC INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " ACCESS_PER_ERR_CLR ,access permission check error clear,must be set to 0 after clear function interrupt" "0,1"
|
|
bitfld.long 0x00 8. " ACCESS_PER_ERR_STA ,access permission check error status" "0,1"
|
|
bitfld.long 0x00 0. " ACCESS_PER_ERR_EN ,access permission check error enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "CANFD"
|
|
tree "CANFD1"
|
|
width 28.
|
|
group ad:0xF0580000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0580004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0580008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0580010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0580014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0580018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF058001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0580020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0580024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0580028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF058002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0580030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0580034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0580038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0580044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0580048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF058004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0580050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0580880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05808FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF058097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0580AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0580AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0580AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0580AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0580AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0580AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0580AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0580AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0580B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0580B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0580B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0580B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0580B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0580B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0580B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0580B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0580B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0580B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0580B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0580B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0580B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0580B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0580B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0580B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0580B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0580B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0580B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0580B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0580B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0580B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0580B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0580B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0580B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0580B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0580C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
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|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
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|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
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|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0580C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
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|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0580C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0583000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0583004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0583008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF058300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0583010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0583014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0583018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0583024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0583028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF058302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0583030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0583034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0583038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF058303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0583040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0583044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0583048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF058304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD2"
|
|
width 28.
|
|
group ad:0xF0590000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0590004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0590008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0590010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0590014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0590018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF059001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0590020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0590024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0590028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF059002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0590030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0590034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0590038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0590044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0590048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF059004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0590050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0590880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05908FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF059097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0590AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0590AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0590AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0590AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0590AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0590AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0590AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0590AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0590B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0590B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0590B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0590B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0590B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0590B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0590B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0590B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0590B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0590B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0590B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0590B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0590B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0590B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0590B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0590B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0590B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0590B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0590B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0590B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0590B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0590B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0590B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0590B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0590B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0590B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0590C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0590C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0590C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0593000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0593004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0593008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF059300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0593010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0593014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0593018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0593024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0593028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF059302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0593030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0593034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0593038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF059303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0593040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0593044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0593048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF059304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD3"
|
|
width 28.
|
|
group ad:0xF05A0000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF05A0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF05A0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF05A0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF05A0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF05A0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF05A001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF05A0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF05A0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF05A0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF05A002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF05A0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF05A0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF05A0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF05A0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF05A0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF05A004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF05A0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF05A0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05A0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF05A0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF05A0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF05A0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF05A0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF05A0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF05A0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF05A0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF05A0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF05A0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF05A0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF05A0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF05A0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF05A0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05A0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05A0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF05A0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05A0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05A0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF05A0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF05A0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05A0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05A0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF05A0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF05A0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05A0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05A0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF05A0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF05A0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05A0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05A0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF05A0B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF05A0B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05A0B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05A0C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF05A0C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF05A0C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF05A3000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF05A3004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF05A3008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF05A300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF05A3010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF05A3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF05A3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF05A3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF05A3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF05A302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF05A3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF05A3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF05A3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF05A303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF05A3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF05A3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF05A3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF05A304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
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|
tree.end
|
|
tree "CANFD4"
|
|
width 28.
|
|
group ad:0xF05B0000++0x03
|
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line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF05B0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF05B0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF05B0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF05B0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF05B0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF05B001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF05B0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF05B0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF05B0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF05B002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF05B0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF05B0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF05B0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF05B0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF05B0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF05B004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF05B0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF05B0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF05B0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF05B0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF05B0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF05B0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF05B0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF05B0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF05B0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF05B0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF05B0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF05B0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF05B0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF05B0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF05B0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF05B0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05B0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05B0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF05B0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05B0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05B0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF05B0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF05B0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05B0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05B0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF05B0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF05B0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05B0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05B0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF05B0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF05B0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05B0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05B0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF05B0B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF05B0B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF05B0B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF05B0C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF05B0C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF05B0C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF05B3000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF05B3004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF05B3008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF05B300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF05B3010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF05B3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF05B3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF05B3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF05B3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF05B302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF05B3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF05B3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF05B3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF05B303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF05B3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF05B3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF05B3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF05B304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD5"
|
|
width 28.
|
|
group ad:0xF0AD0000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0AD0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0AD0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0AD0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0AD0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0AD0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0AD001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0AD0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0AD0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0AD0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0AD002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0AD0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0AD0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0AD0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0AD0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0AD0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0AD004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0AD0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0AD0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AD0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0AD0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0AD0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0AD0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0AD0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0AD0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0AD0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0AD0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0AD0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0AD0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0AD0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0AD0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0AD0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0AD0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AD0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AD0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0AD0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AD0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AD0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AD0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AD0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AD0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AD0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AD0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AD0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AD0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AD0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AD0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AD0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AD0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AD0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AD0B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AD0B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AD0B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AD0C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0AD0C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0AD0C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0AD3000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0AD3004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0AD3008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0AD300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0AD3010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0AD3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0AD3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0AD3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0AD3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0AD302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0AD3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0AD3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0AD3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0AD303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0AD3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0AD3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0AD3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0AD304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD6"
|
|
width 28.
|
|
group ad:0xF0EB0000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0EB0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0EB0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0EB0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0EB0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0EB0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0EB001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0EB0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0EB0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0EB0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0EB002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0EB0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0EB0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0EB0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0EB0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0EB0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0EB004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0EB0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EB0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EB0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0EB0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0EB0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0EB0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EB0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0EB0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0EB0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EB0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0EB0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0EB0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0EB0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0EB0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0EB0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0EB0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EB0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EB0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0EB0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EB0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EB0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EB0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EB0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EB0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EB0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EB0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EB0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EB0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EB0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EB0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EB0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EB0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EB0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EB0B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EB0B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EB0B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EB0C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0EB0C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0EB0C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0EB3000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0EB3004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0EB3008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0EB300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0EB3010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EB3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EB3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0EB3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0EB3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EB302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0EB3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0EB3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0EB3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0EB303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0EB3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0EB3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0EB3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0EB304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD7"
|
|
width 28.
|
|
group ad:0xF0AE0000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0AE0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0AE0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0AE0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0AE0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0AE0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0AE001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0AE0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0AE0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0AE0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0AE002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0AE0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0AE0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0AE0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0AE0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0AE0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0AE004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0AE0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0AE0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AE0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0AE0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0AE0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0AE0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0AE0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0AE0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0AE0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0AE0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0AE0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0AE0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0AE0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0AE0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0AE0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0AE0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AE0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AE0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0AE0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AE0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AE0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AE0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AE0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AE0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AE0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AE0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AE0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AE0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AE0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AE0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AE0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AE0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AE0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AE0B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AE0B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AE0B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AE0C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0AE0C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0AE0C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0AE3000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0AE3004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0AE3008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0AE300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0AE3010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0AE3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0AE3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0AE3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0AE3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0AE302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0AE3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0AE3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0AE3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0AE303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0AE3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0AE3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0AE3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0AE304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD8"
|
|
width 28.
|
|
group ad:0xF0EC0000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0EC0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0EC0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0EC0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0EC0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0EC0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0EC001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0EC0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0EC0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0EC0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0EC002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0EC0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0EC0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0EC0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0EC0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0EC0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0EC004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0EC0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EC0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EC0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0EC0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0EC0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0EC0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EC0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0EC0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0EC0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EC0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0EC0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0EC0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0EC0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0EC0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0EC0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0EC0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EC0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EC0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0EC0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EC0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EC0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EC0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EC0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EC0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EC0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EC0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EC0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EC0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EC0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EC0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EC0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EC0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EC0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EC0B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EC0B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EC0B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EC0C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0EC0C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0EC0C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0EC3000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0EC3004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0EC3008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0EC300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0EC3010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EC3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EC3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0EC3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0EC3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EC302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0EC3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0EC3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0EC3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0EC303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0EC3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0EC3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0EC3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0EC304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD9"
|
|
width 28.
|
|
group ad:0xF0AF0000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0AF0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0AF0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0AF0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0AF0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0AF0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0AF001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0AF0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0AF0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0AF0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0AF002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0AF0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0AF0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0AF0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0AF0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0AF0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0AF004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0AF0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0AF0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0AF0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0AF0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0AF0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0AF0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0AF0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0AF0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0AF0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0AF0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0AF0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0AF0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0AF0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0AF0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0AF0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0AF0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AF0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AF0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0AF0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AF0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AF0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AF0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AF0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AF0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AF0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AF0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AF0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AF0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AF0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AF0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AF0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AF0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AF0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0AF0B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0AF0B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0AF0B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0AF0C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0AF0C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0AF0C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0AF3000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0AF3004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0AF3008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0AF300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0AF3010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0AF3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0AF3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0AF3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0AF3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0AF302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0AF3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0AF3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0AF3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0AF303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0AF3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0AF3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0AF3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0AF304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD10"
|
|
width 28.
|
|
group ad:0xF0ED0000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0ED0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0ED0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0ED0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0ED0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0ED0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0ED001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0ED0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0ED0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0ED0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0ED002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0ED0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0ED0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0ED0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0ED0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0ED0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0ED004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0ED0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0ED0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0ED0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0ED0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0ED0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0ED0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0ED0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0ED0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0ED0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0ED0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0ED0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0ED0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0ED0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0ED0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0ED0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0ED0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0ED0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0ED0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0ED0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0ED0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0ED0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0ED0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0ED0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0ED0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0ED0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0ED0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0ED0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0ED0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0ED0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0ED0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0ED0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0ED0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0ED0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0ED0B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0ED0B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0ED0B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0ED0C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0ED0C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0ED0C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0ED3000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0ED3004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0ED3008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0ED300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0ED3010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0ED3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0ED3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0ED3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0ED3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0ED302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0ED3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0ED3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0ED3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0ED303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0ED3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0ED3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0ED3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0ED304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD11"
|
|
width 28.
|
|
group ad:0xF0B00000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0B00004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B00008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0B00010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0B00014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0B00018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0B0001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0B00020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0B00024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0B00028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0B0002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0B00030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0B00034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0B00038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0B00044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0B00048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0B0004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0B00050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B00880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B008FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B0097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B00AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0B00AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0B00AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0B00AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B00AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0B00AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0B00AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B00AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0B00B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0B00B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0B00B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0B00B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0B00B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0B00B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B00B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B00B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0B00B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B00B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B00B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B00B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B00B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B00B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B00B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B00B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B00B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B00B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B00B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B00B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B00B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B00B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B00B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B00B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B00B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B00B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B00C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0B00C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B00C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0B03000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0B03004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0B03008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0B0300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0B03010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B03014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B03018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0B03024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0B03028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B0302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0B03030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B03034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0B03038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0B0303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0B03040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0B03044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0B03048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B0304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD12"
|
|
width 28.
|
|
group ad:0xF0EE0000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0EE0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0EE0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0EE0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0EE0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0EE0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0EE001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0EE0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0EE0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0EE0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0EE002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0EE0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0EE0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0EE0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0EE0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0EE0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0EE004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0EE0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EE0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EE0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0EE0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0EE0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0EE0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EE0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0EE0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0EE0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EE0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0EE0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0EE0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0EE0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0EE0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0EE0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0EE0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EE0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EE0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0EE0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EE0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EE0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EE0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EE0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EE0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EE0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EE0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EE0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EE0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EE0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EE0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EE0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EE0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EE0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
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bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
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group ad:0xF0EE0B74++0x03
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line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
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bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
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|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
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group ad:0xF0EE0B78++0x03
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line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
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hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
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hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
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hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
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hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
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group ad:0xF0EE0B7C++0x03
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line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
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hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
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hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
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hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
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hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
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group ad:0xF0EE0C00++0x03
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line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
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bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
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bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
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bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
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textline " "
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bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
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bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
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bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
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bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
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textline " "
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bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
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bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
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bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
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bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
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textline " "
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bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
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hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
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group ad:0xF0EE0C04++0x03
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line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
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bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
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hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
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bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
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bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
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|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
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bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
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bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
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group ad:0xF0EE0C08++0x03
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line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
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bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
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hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
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bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
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group ad:0xF0EE3000++0x03
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line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
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bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
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group ad:0xF0EE3004++0x03
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line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
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hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
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|
group ad:0xF0EE3008++0x03
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line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
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|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
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|
group ad:0xF0EE300C++0x03
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line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
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bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
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bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
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|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
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|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
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textline " "
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bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
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bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
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bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
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bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
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|
textline " "
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bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
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|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
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|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
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|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
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bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
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bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
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|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
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|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
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|
textline " "
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bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
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|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
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|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
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|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
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|
textline " "
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bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
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|
group ad:0xF0EE3010++0x03
|
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line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
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bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
textline " "
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bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
textline " "
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bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
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bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
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bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EE3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EE3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0EE3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0EE3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EE302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0EE3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0EE3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0EE3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0EE303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0EE3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0EE3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0EE3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0EE304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD13"
|
|
width 28.
|
|
group ad:0xF0B10000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0B10004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B10008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0B10010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0B10014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0B10018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0B1001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0B10020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0B10024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0B10028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0B1002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0B10030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0B10034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0B10038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0B10044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0B10048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0B1004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0B10050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B10880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B108FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B1097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B10AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0B10AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0B10AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0B10AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B10AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0B10AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0B10AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B10AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0B10B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0B10B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0B10B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0B10B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0B10B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0B10B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B10B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B10B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0B10B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B10B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B10B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B10B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B10B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B10B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B10B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B10B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B10B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B10B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B10B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B10B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B10B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B10B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B10B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B10B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B10B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B10B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B10C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0B10C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B10C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0B13000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0B13004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0B13008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0B1300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0B13010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B13014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B13018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0B13024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0B13028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B1302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0B13030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B13034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0B13038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0B1303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0B13040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0B13044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0B13048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B1304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD14"
|
|
width 28.
|
|
group ad:0xF0EF0000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0EF0004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0EF0008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0EF0010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0EF0014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0EF0018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0EF001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0EF0020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0EF0024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0EF0028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0EF002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0EF0030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0EF0034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0EF0038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0EF0044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0EF0048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0EF004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0EF0050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EF0880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF08FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0EF0AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0EF0AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0EF0AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0EF0AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EF0AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0EF0AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0EF0AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0EF0AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0EF0B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0EF0B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0EF0B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0EF0B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0EF0B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0EF0B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EF0B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EF0B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0EF0B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EF0B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EF0B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EF0B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EF0B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EF0B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EF0B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EF0B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EF0B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EF0B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EF0B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EF0B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EF0B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EF0B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EF0B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0EF0B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0EF0B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0EF0B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0EF0C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0EF0C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0EF0C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0EF3000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0EF3004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0EF3008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0EF300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0EF3010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EF3014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EF3018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0EF3024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0EF3028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0EF302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0EF3030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0EF3034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0EF3038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0EF303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0EF3040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0EF3044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0EF3048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0EF304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD15"
|
|
width 28.
|
|
group ad:0xF0B20000++0x03
|
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line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0B20004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B20008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0B20010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0B20014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0B20018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0B2001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0B20020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0B20024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0B20028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0B2002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0B20030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0B20034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0B20038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0B20044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0B20048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0B2004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0B20050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B20880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B208FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B2097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B20AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0B20AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0B20AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0B20AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B20AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0B20AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0B20AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B20AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0B20B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0B20B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0B20B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0B20B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0B20B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0B20B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B20B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B20B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0B20B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B20B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B20B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B20B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B20B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B20B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B20B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B20B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B20B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B20B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B20B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B20B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B20B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B20B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B20B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B20B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B20B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B20B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B20C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0B20C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B20C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0B23000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0B23004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0B23008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0B2300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0B23010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B23014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B23018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0B23024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0B23028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B2302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0B23030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B23034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0B23038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0B2303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0B23040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0B23044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0B23048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B2304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD16"
|
|
width 28.
|
|
group ad:0xF0F00000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0F00004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F00008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0F00010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0F00014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0F00018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0F0001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0F00020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0F00024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0F00028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0F0002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0F00030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0F00034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0F00038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0F00044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0F00048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0F0004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0F00050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F00880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F008FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F0097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F00AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0F00AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0F00AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0F00AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F00AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0F00AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0F00AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F00AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0F00B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0F00B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0F00B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0F00B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0F00B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F00B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F00B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F00B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0F00B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F00B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F00B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F00B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F00B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F00B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F00B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F00B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F00B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F00B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F00B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
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hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
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bitfld.long 0x00 22. " SRR ,SRR" "0,1"
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bitfld.long 0x00 21. " IDE ,IDE" "0,1"
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bitfld.long 0x00 20. " RTR ,RTR" "0,1"
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textline " "
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bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
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group ad:0xF0F00B64++0x03
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line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
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bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
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hexmask.long 0x00 0.--28. 1. " ID ,ID"
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group ad:0xF0F00B68++0x03
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line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
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hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
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hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
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hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
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hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
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group ad:0xF0F00B6C++0x03
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line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
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hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
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hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
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hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
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hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
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group ad:0xF0F00B70++0x03
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line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
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hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
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bitfld.long 0x00 22. " SRR ,SRR" "0,1"
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bitfld.long 0x00 21. " IDE ,IDE" "0,1"
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bitfld.long 0x00 20. " RTR ,RTR" "0,1"
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textline " "
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bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
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group ad:0xF0F00B74++0x03
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line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
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bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
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hexmask.long 0x00 0.--28. 1. " ID ,ID"
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group ad:0xF0F00B78++0x03
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line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
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hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
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hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
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hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
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hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
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group ad:0xF0F00B7C++0x03
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line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
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hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
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hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
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hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
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hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
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group ad:0xF0F00C00++0x03
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line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
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bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
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bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
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bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
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textline " "
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bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
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bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
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bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
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bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
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textline " "
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bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
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bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
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bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
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bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
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textline " "
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bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
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hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
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group ad:0xF0F00C04++0x03
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line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
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bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
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hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
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bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
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bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
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bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
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bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
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bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
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group ad:0xF0F00C08++0x03
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line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
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bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
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hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
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bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
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group ad:0xF0F03000++0x03
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line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
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bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
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group ad:0xF0F03004++0x03
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line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
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hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
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group ad:0xF0F03008++0x03
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line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
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hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
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group ad:0xF0F0300C++0x03
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line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
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bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
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bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
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bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
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bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
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textline " "
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bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
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bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
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bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
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bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
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textline " "
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bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
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bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
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bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
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bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
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textline " "
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bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
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bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
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bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
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bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
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textline " "
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bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
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bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
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bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
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bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
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textline " "
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bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
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group ad:0xF0F03010++0x03
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line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
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bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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group ad:0xF0F03014++0x03
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line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
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bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
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bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
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textline " "
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bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
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group ad:0xF0F03018++0x03
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line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
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bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
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bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
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bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
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group ad:0xF0F03024++0x03
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line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
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bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
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group ad:0xF0F03028++0x03
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line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
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bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F0302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0F03030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F03034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0F03038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0F0303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0F03040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0F03044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0F03048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F0304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD17"
|
|
width 28.
|
|
group ad:0xF0B30000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0B30004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B30008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0B30010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0B30014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0B30018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0B3001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0B30020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0B30024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0B30028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0B3002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0B30030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0B30034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0B30038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0B30044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0B30048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0B3004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0B30050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B30880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B308FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B3097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B30AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0B30AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0B30AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0B30AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B30AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0B30AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0B30AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B30AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0B30B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0B30B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0B30B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0B30B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0B30B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0B30B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B30B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B30B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0B30B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B30B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B30B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B30B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B30B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B30B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B30B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B30B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B30B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B30B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B30B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B30B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B30B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B30B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B30B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B30B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B30B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B30B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B30C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0B30C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B30C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0B33000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0B33004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0B33008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0B3300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0B33010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B33014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B33018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0B33024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0B33028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B3302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0B33030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B33034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0B33038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0B3303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0B33040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0B33044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0B33048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B3304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CABFD18"
|
|
width 28.
|
|
group ad:0xF0F10000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0F10004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F10008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0F10010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0F10014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0F10018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0F1001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0F10020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0F10024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0F10028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0F1002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0F10030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0F10034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0F10038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0F10044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0F10048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0F1004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0F10050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F10880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F108FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F1097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F10AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0F10AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0F10AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0F10AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F10AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0F10AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0F10AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F10AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0F10B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0F10B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0F10B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0F10B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0F10B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F10B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F10B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F10B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0F10B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F10B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F10B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F10B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F10B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F10B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F10B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F10B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F10B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F10B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F10B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F10B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F10B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F10B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F10B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F10B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F10B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F10B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F10C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0F10C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F10C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0F13000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0F13004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0F13008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0F1300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0F13010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F13014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F13018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0F13024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0F13028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F1302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0F13030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F13034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0F13038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0F1303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0F13040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0F13044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0F13048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F1304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD19"
|
|
width 28.
|
|
group ad:0xF0B40000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0B40004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B40008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0B40010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0B40014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0B40018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0B4001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0B40020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0B40024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0B40028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0B4002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0B40030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0B40034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0B40038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0B40044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0B40048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0B4004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0B40050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B40880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B408FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B4097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B40AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0B40AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0B40AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0B40AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B40AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0B40AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0B40AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B40AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0B40B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0B40B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0B40B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0B40B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0B40B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0B40B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B40B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B40B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0B40B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B40B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B40B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B40B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B40B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B40B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B40B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B40B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B40B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B40B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B40B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B40B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B40B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B40B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B40B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B40B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B40B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B40B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B40C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0B40C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B40C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0B43000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0B43004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0B43008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0B4300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0B43010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B43014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B43018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0B43024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0B43028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B4302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0B43030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B43034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0B43038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0B4303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0B43040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0B43044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0B43048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B4304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD20"
|
|
width 28.
|
|
group ad:0xF0F20000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0F20004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F20008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0F20010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0F20014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0F20018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0F2001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0F20020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0F20024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0F20028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0F2002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0F20030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0F20034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0F20038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0F20044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0F20048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0F2004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0F20050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F20880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F208FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F2097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F20AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0F20AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0F20AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0F20AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F20AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0F20AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0F20AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F20AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0F20B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0F20B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0F20B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0F20B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0F20B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F20B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F20B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F20B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0F20B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F20B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F20B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F20B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F20B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F20B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F20B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F20B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F20B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F20B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F20B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F20B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F20B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F20B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F20B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F20B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F20B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F20B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F20C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0F20C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F20C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0F23000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0F23004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0F23008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0F2300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0F23010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F23014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F23018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0F23024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0F23028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F2302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0F23030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F23034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0F23038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0F2303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0F23040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0F23044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0F23048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F2304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD21"
|
|
width 28.
|
|
group ad:0xF0B50000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0B50004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B50008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0B50010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0B50014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0B50018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0B5001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0B50020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0B50024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0B50028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0B5002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0B50030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0B50034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0B50038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0B50044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0B50048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0B5004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0B50050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B50880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B508FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B5097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B50AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0B50AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0B50AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0B50AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B50AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0B50AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0B50AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B50AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0B50B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0B50B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0B50B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0B50B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0B50B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0B50B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B50B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B50B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0B50B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B50B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B50B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B50B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B50B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B50B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B50B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B50B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B50B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B50B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B50B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B50B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B50B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B50B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B50B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B50B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B50B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B50B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B50C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0B50C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B50C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0B53000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0B53004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0B53008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0B5300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0B53010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
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|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
group ad:0xF0B53014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
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|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B53018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0B53024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0B53028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B5302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
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|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0B53030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
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bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B53034++0x03
|
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line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
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bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
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|
group ad:0xF0B53038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0B5303C++0x03
|
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line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0B53040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0B53044++0x03
|
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line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
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bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0B53048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B5304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
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tree.end
|
|
tree "CANFD22"
|
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width 28.
|
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group ad:0xF0F30000++0x03
|
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line.long 0x00 "CAN_MCR,Module Configuration Register"
|
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bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
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bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0F30004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F30008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0F30010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0F30014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0F30018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0F3001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0F30020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0F30024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0F30028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0F3002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0F30030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0F30034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0F30038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0F30044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0F30048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0F3004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0F30050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F30880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F308FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F3097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F30AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0F30AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0F30AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0F30AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F30AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0F30AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0F30AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F30AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0F30B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0F30B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0F30B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0F30B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0F30B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F30B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F30B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F30B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0F30B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F30B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F30B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F30B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F30B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F30B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F30B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F30B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F30B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F30B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F30B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F30B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F30B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F30B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F30B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F30B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F30B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F30B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F30C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0F30C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F30C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0F33000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0F33004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0F33008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0F3300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
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|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
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|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
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|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0F33010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F33014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F33018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0F33024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0F33028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F3302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0F33030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F33034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0F33038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0F3303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0F33040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0F33044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0F33048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F3304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD23"
|
|
width 28.
|
|
group ad:0xF0B60000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0B60004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B60008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0B60010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0B60014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0B60018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0B6001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0B60020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0B60024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0B60028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0B6002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0B60030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0B60034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0B60038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0B60044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0B60048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0B6004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0B60050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B60880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B608FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B6097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0B60AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0B60AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0B60AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0B60AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B60AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0B60AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0B60AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0B60AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0B60B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0B60B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0B60B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0B60B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0B60B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0B60B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B60B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B60B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0B60B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B60B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B60B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B60B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B60B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B60B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B60B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B60B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B60B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B60B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B60B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B60B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B60B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B60B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B60B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0B60B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0B60B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0B60B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0B60C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0B60C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0B60C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0B63000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0B63004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0B63008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0B6300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0B63010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B63014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B63018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0B63024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0B63028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0B6302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0B63030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B63034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0B63038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0B6303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0B63040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0B63044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0B63048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0B6304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree "CANFD24"
|
|
width 28.
|
|
group ad:0xF0F40000++0x03
|
|
line.long 0x00 "CAN_MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,MDIS" "0,1"
|
|
bitfld.long 0x00 30. " FRZ ,FRZ" "0,1"
|
|
bitfld.long 0x00 29. " RFEN ,RFEN" "0,1"
|
|
bitfld.long 0x00 28. " HALT ,HALT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "NOTRDY ,NOTRDY" "0,1"
|
|
bitfld.long 0x00 26. " WAKMSK ,WAKMSK" "0,1"
|
|
bitfld.long 0x00 25. " SOFTRST ,SOFTRST" "0,1"
|
|
bitfld.long 0x00 24. " FRZACK ,FRZACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SUPV ,SUPV" "0,1"
|
|
bitfld.long 0x00 22. " SLFWAK ,SLFWAK" "0,1"
|
|
bitfld.long 0x00 21. " WRNEN ,WRNEN" "0,1"
|
|
bitfld.long 0x00 20. " LPMACK ,LPMACK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "WAKSRC ,WAKSRC" "0,1"
|
|
bitfld.long 0x00 18. " DOZE ,DOZE" "0,1"
|
|
bitfld.long 0x00 17. " SRXDIS ,SRXDIS" "0,1"
|
|
bitfld.long 0x00 16. " IRMQ ,IRMQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "DMA ,DMA" "0,1"
|
|
bitfld.long 0x00 14. " PNET_EN ,PNET_EN" "0,1"
|
|
bitfld.long 0x00 13. " LPRIOEN ,LPRIOEN" "0,1"
|
|
bitfld.long 0x00 12. " AEN ,AEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FDEN ,FDEN" "0,1"
|
|
bitfld.long 0x00 10. " RSRVD10_10 ,RSRVD10_10" "0,1"
|
|
bitfld.long 0x00 8.--9. " IDAM ,IDAM" "0,1,2,3"
|
|
bitfld.long 0x00 7. " RSRVD7_7 ,RSRVD7_7" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB ,MAXMB"
|
|
group ad:0xF0F40004++0x03
|
|
line.long 0x00 "CAN_CTRL1,Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,PRESDIV"
|
|
bitfld.long 0x00 22.--23. " RJW ,RJW" "0,1,2,3"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,PSEG1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,PSEG2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BOFFMSK ,BOFFMSK" "0,1"
|
|
bitfld.long 0x00 14. " ERRMSK ,ERRMSK" "0,1"
|
|
bitfld.long 0x00 13. " CLKSRC ,CLKSRC" "0,1"
|
|
bitfld.long 0x00 12. " LPB ,LPB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TWRNMSK ,TWRNMSK" "0,1"
|
|
bitfld.long 0x00 10. " RWRNMSK ,RWRNMSK" "0,1"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 7. " SMP ,SMP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "BOFFREC ,BOFFREC" "0,1"
|
|
bitfld.long 0x00 5. " TSYN ,TSYN" "0,1"
|
|
bitfld.long 0x00 4. " LBUF ,LBUF" "0,1"
|
|
bitfld.long 0x00 3. " LOM ,LOM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PROPSEG ,PROPSEG" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F40008++0x03
|
|
line.long 0x00 "CAN_TIMER,Free Running Timer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,TIMER"
|
|
group ad:0xF0F40010++0x03
|
|
line.long 0x00 "CAN_RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " MG ,MG"
|
|
group ad:0xF0F40014++0x03
|
|
line.long 0x00 "CAN_RX14MASK,Rx 14 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX14M ,RX14M"
|
|
group ad:0xF0F40018++0x03
|
|
line.long 0x00 "CAN_RX15MASK,Rx 15 Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " RX15M ,RX15M"
|
|
group ad:0xF0F4001C++0x03
|
|
line.long 0x00 "CAN_ECR,Error Count Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,RXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,TXERRCNT_FAST"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,RXERRCNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,TXERRCNT"
|
|
group ad:0xF0F40020++0x03
|
|
line.long 0x00 "CAN_ESR1,Error and Status 1 Register"
|
|
bitfld.long 0x00 31. " BIT1ERR_FAST ,BIT1ERR_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BIT0ERR_FAST ,BIT0ERR_FAST" "0,1"
|
|
bitfld.long 0x00 29. " RSRVD29_29 ,RSRVD29_29" "0,1"
|
|
bitfld.long 0x00 28. " CRCERR_FAST ,CRCERR_FAST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "FRMERR_FAST ,FRMERR_FAST" "0,1"
|
|
bitfld.long 0x00 26. " STFERR_FAST ,STFERR_FAST" "0,1"
|
|
bitfld.long 0x00 21.--25. " RSRVD25_21 ,RSRVD25_21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " ERROVR ,ERROVR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "ERRINT_FAST ,ERRINT_FAST" "0,1"
|
|
bitfld.long 0x00 18. " BOFFDONEINT ,BOFFDONEINT" "0,1"
|
|
bitfld.long 0x00 17. " SYNCH ,SYNCH" "0,1"
|
|
bitfld.long 0x00 16. " TWRNINT ,TWRNINT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RWRNINT ,RWRNINT" "0,1"
|
|
bitfld.long 0x00 14. " BIT1ERR ,BIT1ERR" "0,1"
|
|
bitfld.long 0x00 13. " BIT0ERR ,BIT0ERR" "0,1"
|
|
bitfld.long 0x00 12. " ACKERR ,ACKERR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRCERR ,CRCERR" "0,1"
|
|
bitfld.long 0x00 10. " FRMERR ,FRMERR" "0,1"
|
|
bitfld.long 0x00 9. " STFERR ,STFERR" "0,1"
|
|
bitfld.long 0x00 8. " TXWRN ,TXWRN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RXWRN ,RXWRN" "0,1"
|
|
bitfld.long 0x00 6. " IDLE ,IDLE" "0,1"
|
|
bitfld.long 0x00 5. " TX ,TX" "0,1"
|
|
bitfld.long 0x00 4. " FLTCONF ,FLTCONF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX ,RX" "0,1"
|
|
bitfld.long 0x00 2. " BOFFINT ,BOFFINT" "0,1"
|
|
bitfld.long 0x00 1. " ERRINT ,ERRINT" "0,1"
|
|
bitfld.long 0x00 0. " WAKINT ,WAKINT" "0,1"
|
|
group ad:0xF0F40024++0x03
|
|
line.long 0x00 "CAN_IMASK2,Interrupt Masks 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32M ,BUF63TO32M"
|
|
group ad:0xF0F40028++0x03
|
|
line.long 0x00 "CAN_IMASK1,Interrupt Masks 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0M ,BUF31TO0M"
|
|
group ad:0xF0F4002C++0x03
|
|
line.long 0x00 "CAN_IFLAG2,Interrupt Flags 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF63TO32I ,BUF63TO32I"
|
|
group ad:0xF0F40030++0x03
|
|
line.long 0x00 "CAN_IFLAG1,Interrupt Flags 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BUF31TO0I ,BUF31TO0I"
|
|
group ad:0xF0F40034++0x03
|
|
line.long 0x00 "CAN_CTRL2,Control 2 Register"
|
|
bitfld.long 0x00 31. " ERRMSK_FAST ,ERRMSK_FAST" "0,1"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,BOFFDONEMSK" "0,1"
|
|
bitfld.long 0x00 29. " ECRWRE ,ECRWRE" "0,1"
|
|
bitfld.long 0x00 28. " WRMFRZ ,WRMFRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. "RFFN ,RFFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " TASD ,TASD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,MRP" "0,1"
|
|
bitfld.long 0x00 17. " RRS ,RRS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "EACEN ,EACEN" "0,1"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,TIMER_SRC" "0,1"
|
|
bitfld.long 0x00 14. " PREXCEN ,PREXCEN" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ISOCANFDEN ,ISOCANFDEN" "0,1"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,EDFLTDIS" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. " RSRVD10_0 ,RSRVD10_0"
|
|
group ad:0xF0F40038++0x03
|
|
line.long 0x00 "CAN_ESR2,Error and Status 2 Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,LPTM"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 14. " VPS ,VPS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "IMB ,IMB" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " RSRVD12_0 ,RSRVD12_0"
|
|
group ad:0xF0F40044++0x03
|
|
line.long 0x00 "CAN_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,MBCRC"
|
|
bitfld.long 0x00 15. " RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,TXCRC"
|
|
group ad:0xF0F40048++0x03
|
|
line.long 0x00 "CAN_RXFGMASK,Rx FIFO Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. " FGM ,FGM"
|
|
group ad:0xF0F4004C++0x03
|
|
line.long 0x00 "CAN_RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " RSRVD31_9 ,RSRVD31_9"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,IDHIT"
|
|
group ad:0xF0F40050++0x03
|
|
line.long 0x00 "CAN_CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,BTF" "0,1"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,EPRESDIV"
|
|
bitfld.long 0x00 16.--20. " ERJW ,ERJW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--15. 1. " EPROPSEG ,EPROPSEG"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. "EPSEG1 ,EPSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,EPSEG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F40880++0x03
|
|
line.long 0x00 "CAN_RXIMR0,Rx InDIvidual Mask Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40884++0x03
|
|
line.long 0x00 "CAN_RXIMR1,Rx InDIvidual Mask Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40888++0x03
|
|
line.long 0x00 "CAN_RXIMR2,Rx InDIvidual Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4088C++0x03
|
|
line.long 0x00 "CAN_RXIMR3,Rx InDIvidual Mask Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40890++0x03
|
|
line.long 0x00 "CAN_RXIMR4,Rx InDIvidual Mask Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40894++0x03
|
|
line.long 0x00 "CAN_RXIMR5,Rx InDIvidual Mask Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40898++0x03
|
|
line.long 0x00 "CAN_RXIMR6,Rx InDIvidual Mask Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4089C++0x03
|
|
line.long 0x00 "CAN_RXIMR7,Rx InDIvidual Mask Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408A0++0x03
|
|
line.long 0x00 "CAN_RXIMR8,Rx InDIvidual Mask Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408A4++0x03
|
|
line.long 0x00 "CAN_RXIMR9,Rx InDIvidual Mask Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408A8++0x03
|
|
line.long 0x00 "CAN_RXIMR10,Rx InDIvidual Mask Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408AC++0x03
|
|
line.long 0x00 "CAN_RXIMR11,Rx InDIvidual Mask Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408B0++0x03
|
|
line.long 0x00 "CAN_RXIMR12,Rx InDIvidual Mask Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408B4++0x03
|
|
line.long 0x00 "CAN_RXIMR13,Rx InDIvidual Mask Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408B8++0x03
|
|
line.long 0x00 "CAN_RXIMR14,Rx InDIvidual Mask Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408BC++0x03
|
|
line.long 0x00 "CAN_RXIMR15,Rx InDIvidual Mask Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408C0++0x03
|
|
line.long 0x00 "CAN_RXIMR16,Rx InDIvidual Mask Register 16"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408C4++0x03
|
|
line.long 0x00 "CAN_RXIMR17,Rx InDIvidual Mask Register 17"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408C8++0x03
|
|
line.long 0x00 "CAN_RXIMR18,Rx InDIvidual Mask Register 18"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408CC++0x03
|
|
line.long 0x00 "CAN_RXIMR19,Rx InDIvidual Mask Register 19"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408D0++0x03
|
|
line.long 0x00 "CAN_RXIMR20,Rx InDIvidual Mask Register 20"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408D4++0x03
|
|
line.long 0x00 "CAN_RXIMR21,Rx InDIvidual Mask Register 21"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408D8++0x03
|
|
line.long 0x00 "CAN_RXIMR22,Rx InDIvidual Mask Register 22"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408DC++0x03
|
|
line.long 0x00 "CAN_RXIMR23,Rx InDIvidual Mask Register 23"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408E0++0x03
|
|
line.long 0x00 "CAN_RXIMR24,Rx InDIvidual Mask Register 24"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408E4++0x03
|
|
line.long 0x00 "CAN_RXIMR25,Rx InDIvidual Mask Register 25"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408E8++0x03
|
|
line.long 0x00 "CAN_RXIMR26,Rx InDIvidual Mask Register 26"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408EC++0x03
|
|
line.long 0x00 "CAN_RXIMR27,Rx InDIvidual Mask Register 27"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408F0++0x03
|
|
line.long 0x00 "CAN_RXIMR28,Rx InDIvidual Mask Register 28"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408F4++0x03
|
|
line.long 0x00 "CAN_RXIMR29,Rx InDIvidual Mask Register 29"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408F8++0x03
|
|
line.long 0x00 "CAN_RXIMR30,Rx InDIvidual Mask Register 30"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F408FC++0x03
|
|
line.long 0x00 "CAN_RXIMR31,Rx InDIvidual Mask Register 31"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40900++0x03
|
|
line.long 0x00 "CAN_RXIMR32,Rx InDIvidual Mask Register 32"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40904++0x03
|
|
line.long 0x00 "CAN_RXIMR33,Rx InDIvidual Mask Register 33"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40908++0x03
|
|
line.long 0x00 "CAN_RXIMR34,Rx InDIvidual Mask Register 34"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4090C++0x03
|
|
line.long 0x00 "CAN_RXIMR35,Rx InDIvidual Mask Register 35"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40910++0x03
|
|
line.long 0x00 "CAN_RXIMR36,Rx InDIvidual Mask Register 36"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40914++0x03
|
|
line.long 0x00 "CAN_RXIMR37,Rx InDIvidual Mask Register 37"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40918++0x03
|
|
line.long 0x00 "CAN_RXIMR38,Rx InDIvidual Mask Register 38"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4091C++0x03
|
|
line.long 0x00 "CAN_RXIMR39,Rx InDIvidual Mask Register 39"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40920++0x03
|
|
line.long 0x00 "CAN_RXIMR40,Rx InDIvidual Mask Register 40"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40924++0x03
|
|
line.long 0x00 "CAN_RXIMR41,Rx InDIvidual Mask Register 41"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40928++0x03
|
|
line.long 0x00 "CAN_RXIMR42,Rx InDIvidual Mask Register 42"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4092C++0x03
|
|
line.long 0x00 "CAN_RXIMR43,Rx InDIvidual Mask Register 43"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40930++0x03
|
|
line.long 0x00 "CAN_RXIMR44,Rx InDIvidual Mask Register 44"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40934++0x03
|
|
line.long 0x00 "CAN_RXIMR45,Rx InDIvidual Mask Register 45"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40938++0x03
|
|
line.long 0x00 "CAN_RXIMR46,Rx InDIvidual Mask Register 46"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4093C++0x03
|
|
line.long 0x00 "CAN_RXIMR47,Rx InDIvidual Mask Register 47"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40940++0x03
|
|
line.long 0x00 "CAN_RXIMR48,Rx InDIvidual Mask Register 48"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40944++0x03
|
|
line.long 0x00 "CAN_RXIMR49,Rx InDIvidual Mask Register 49"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40948++0x03
|
|
line.long 0x00 "CAN_RXIMR50,Rx InDIvidual Mask Register 50"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4094C++0x03
|
|
line.long 0x00 "CAN_RXIMR51,Rx InDIvidual Mask Register 51"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40950++0x03
|
|
line.long 0x00 "CAN_RXIMR52,Rx InDIvidual Mask Register 52"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40954++0x03
|
|
line.long 0x00 "CAN_RXIMR53,Rx InDIvidual Mask Register 53"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40958++0x03
|
|
line.long 0x00 "CAN_RXIMR54,Rx InDIvidual Mask Register 54"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4095C++0x03
|
|
line.long 0x00 "CAN_RXIMR55,Rx InDIvidual Mask Register 55"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40960++0x03
|
|
line.long 0x00 "CAN_RXIMR56,Rx InDIvidual Mask Register 56"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40964++0x03
|
|
line.long 0x00 "CAN_RXIMR57,Rx InDIvidual Mask Register 57"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40968++0x03
|
|
line.long 0x00 "CAN_RXIMR58,Rx InDIvidual Mask Register 58"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4096C++0x03
|
|
line.long 0x00 "CAN_RXIMR59,Rx InDIvidual Mask Register 59"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40970++0x03
|
|
line.long 0x00 "CAN_RXIMR60,Rx InDIvidual Mask Register 60"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40974++0x03
|
|
line.long 0x00 "CAN_RXIMR61,Rx InDIvidual Mask Register 61"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40978++0x03
|
|
line.long 0x00 "CAN_RXIMR62,Rx InDIvidual Mask Register 62"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F4097C++0x03
|
|
line.long 0x00 "CAN_RXIMR63,Rx InDIvidual Mask Register 63"
|
|
hexmask.long 0x00 0.--31. 1. " MI ,MI"
|
|
group ad:0xF0F40AE0++0x03
|
|
line.long 0x00 "CAN_MECR,Memory Error Control Register"
|
|
bitfld.long 0x00 31. " ECRWRDIS ,ECRWRDIS" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. " RSRVD30_20 ,RSRVD30_20"
|
|
bitfld.long 0x00 19. " HANCEI_MSK ,HANCEI_MSK" "0,1"
|
|
bitfld.long 0x00 18. " FANCEI_MSK ,FANCEI_MSK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
bitfld.long 0x00 16. " CEI_MSK ,CEI_MSK" "0,1"
|
|
bitfld.long 0x00 15. " HAERRIE ,HAERRIE" "0,1"
|
|
bitfld.long 0x00 14. " FAERRIE ,FAERRIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "EXTERRIE ,EXTERRIE" "0,1"
|
|
bitfld.long 0x00 10.--12. " RSRVD12_10 ,RSRVD12_10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " RERDIS ,RERDIS" "0,1"
|
|
bitfld.long 0x00 8. " ECCDIS ,ECCDIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "NCEFAFRZ ,NCEFAFRZ" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RSRVD6_0 ,RSRVD6_0"
|
|
group ad:0xF0F40AE4++0x03
|
|
line.long 0x00 "CAN_ERRIAR,Error Injection Address Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " RSRVD31_14 ,RSRVD31_14"
|
|
hexmask.long.word 0x00 2.--13. 1. " INJADDR_H ,INJADDR_H"
|
|
bitfld.long 0x00 0.--1. " INJADDR_L ,INJADDR_L" "0,1,2,3"
|
|
group ad:0xF0F40AE8++0x03
|
|
line.long 0x00 "CAN_ERRIDPR,Error Injection Data Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFLIP ,DFLIP"
|
|
group ad:0xF0F40AEC++0x03
|
|
line.long 0x00 "CAN_ERRIPPR,Error Injection Parity Pattern Register"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " PFLIP3 ,PFLIP3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " PFLIP2 ,PFLIP2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. "RSRVD15_13 ,RSRVD15_13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " PFLIP1 ,PFLIP1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " RSRVD7_5 ,RSRVD7_5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " PFLIP0 ,PFLIP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F40AF0++0x03
|
|
line.long 0x00 "CAN_RERRAR,Error Report Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " RSRVD31_25 ,RSRVD31_25"
|
|
bitfld.long 0x00 24. " NCE ,NCE" "0,1"
|
|
bitfld.long 0x00 19.--23. " RSRVD23_19 ,RSRVD23_19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " SAID ,SAID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "RSRVD15_14 ,RSRVD15_14" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,ERRADDR"
|
|
group ad:0xF0F40AF4++0x03
|
|
line.long 0x00 "CAN_RERRDR,Error Report Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA ,RDATA"
|
|
group ad:0xF0F40AF8++0x03
|
|
line.long 0x00 "CAN_RERRSYNR,Error Report Syndrome Register"
|
|
bitfld.long 0x00 31. " BE3 ,BE3" "0,1"
|
|
bitfld.long 0x00 29.--30. " RSRVD30_29 ,RSRVD30_29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. " SYND3 ,SYND3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " BE2 ,BE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. "RSRVD22_21 ,RSRVD22_21" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. " SYND2 ,SYND2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " BE1 ,BE1" "0,1"
|
|
bitfld.long 0x00 13.--14. " RSRVD14_13 ,RSRVD14_13" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "SYND1 ,SYND1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " BE0 ,BE0" "0,1"
|
|
bitfld.long 0x00 5.--6. " RSRVD6_5 ,RSRVD6_5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " SYND0 ,SYND0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0F40AFC++0x03
|
|
line.long 0x00 "CAN_ERRSR,Error Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 19. " HANCEIF ,HANCEIF" "0,1"
|
|
bitfld.long 0x00 18. " FANCEIF ,FANCEIF" "0,1"
|
|
bitfld.long 0x00 17. " RSRVD17_17 ,RSRVD17_17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "CEIF ,CEIF" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 3. " HANCEIOF ,HANCEIOF" "0,1"
|
|
bitfld.long 0x00 2. " FANCEIOF ,FANCEIOF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RSRVD1_1 ,RSRVD1_1" "0,1"
|
|
bitfld.long 0x00 0. " CEIOF ,CEIOF" "0,1"
|
|
group ad:0xF0F40B00++0x03
|
|
line.long 0x00 "CAN_CTRL1_PN,Pretended Networking Control 1 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF_MSK ,WTOF_MSK" "0,1"
|
|
bitfld.long 0x00 16. " WUMF_MSK ,WUMF_MSK" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,NMATCH"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PLFS ,PLFS" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IDFS ,IDFS" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FCS ,FCS" "0,1,2,3"
|
|
group ad:0xF0F40B04++0x03
|
|
line.long 0x00 "CAN_CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSRVD31_16 ,RSRVD31_16"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,MATCHTO"
|
|
group ad:0xF0F40B08++0x03
|
|
line.long 0x00 "CAN_WU_MTC,Pretended Networking Wake Up Match Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " RSRVD31_18 ,RSRVD31_18"
|
|
bitfld.long 0x00 17. " WTOF ,WTOF" "0,1"
|
|
bitfld.long 0x00 16. " WUMF ,WUMF" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,MCOUNTER"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSRVD7_0 ,RSRVD7_0"
|
|
group ad:0xF0F40B0C++0x03
|
|
line.long 0x00 "CAN_FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " FLT_IDE ,FLT_IDE" "0,1"
|
|
bitfld.long 0x00 29. " FLT_RTR ,FLT_RTR" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,FLT_ID1"
|
|
group ad:0xF0F40B10++0x03
|
|
line.long 0x00 "CAN_FLT_DLC,Pretended Networking DLC Filter Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RSRVD31_20 ,RSRVD31_20"
|
|
bitfld.long 0x00 16.--19. " FLT_DLC_LO ,FLT_DLC_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " RSRVD15_4 ,RSRVD15_4"
|
|
bitfld.long 0x00 0.--3. " FLT_DLC_HI ,FLT_DLC_HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0F40B14++0x03
|
|
line.long 0x00 "CAN_PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F40B18++0x03
|
|
line.long 0x00 "CAN_PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F40B1C++0x03
|
|
line.long 0x00 "CAN_FLT_ID2_IDMASK,Pretended Networking ID Filter 2/ID Mask Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
bitfld.long 0x00 30. " IDE_MSK ,IDE_MSK" "0,1"
|
|
bitfld.long 0x00 29. " RTR_MSK ,RTR_MSK" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. " FLT_ID2_IDMASK ,FLT_ID2_IDMASK"
|
|
group ad:0xF0F40B20++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2/Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F40B24++0x03
|
|
line.long 0x00 "CAN_PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 High Order Bits/Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F40B40++0x03
|
|
line.long 0x00 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F40B44++0x03
|
|
line.long 0x00 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F40B48++0x03
|
|
line.long 0x00 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F40B4C++0x03
|
|
line.long 0x00 "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F40B50++0x03
|
|
line.long 0x00 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F40B54++0x03
|
|
line.long 0x00 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F40B58++0x03
|
|
line.long 0x00 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F40B5C++0x03
|
|
line.long 0x00 "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F40B60++0x03
|
|
line.long 0x00 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F40B64++0x03
|
|
line.long 0x00 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F40B68++0x03
|
|
line.long 0x00 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F40B6C++0x03
|
|
line.long 0x00 "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F40B70++0x03
|
|
line.long 0x00 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3"
|
|
hexmask.long.word 0x00 23.--31. 1. " RSRVD31_23 ,RSRVD31_23"
|
|
bitfld.long 0x00 22. " SRR ,SRR" "0,1"
|
|
bitfld.long 0x00 21. " IDE ,IDE" "0,1"
|
|
bitfld.long 0x00 20. " RTR ,RTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. "DLC ,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSRVD15_0 ,RSRVD15_0"
|
|
group ad:0xF0F40B74++0x03
|
|
line.long 0x00 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3"
|
|
bitfld.long 0x00 29.--31. " RSRVD31_29 ,RSRVD31_29" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,ID"
|
|
group ad:0xF0F40B78++0x03
|
|
line.long 0x00 "CAN_WMB3_D03,Wake Up Message Buffer Register for Data 0-3 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_0 ,Data_byte_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_1 ,Data_byte_1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_2 ,Data_byte_2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_3 ,Data_byte_3"
|
|
group ad:0xF0F40B7C++0x03
|
|
line.long 0x00 "CAN_WMB3_D47,Wake Up Message Buffer Register for Data 4-7 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Data_byte_4 ,Data_byte_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Data_byte_5 ,Data_byte_5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " Data_byte_6 ,Data_byte_6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Data_byte_7 ,Data_byte_7"
|
|
group ad:0xF0F40C00++0x03
|
|
line.long 0x00 "CAN_FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. " FDRATE ,FDRATE" "0,1"
|
|
bitfld.long 0x00 27.--30. " RSRVD30_27 ,RSRVD30_27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " MBDSR3 ,MBDSR3" "0,1,2,3"
|
|
bitfld.long 0x00 24. " RSRVD24_24 ,RSRVD24_24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "MBDSR2 ,MBDSR2" "0,1,2,3"
|
|
bitfld.long 0x00 21. " RSRVD21_21 ,RSRVD21_21" "0,1"
|
|
bitfld.long 0x00 19.--20. " MBDSR1 ,MBDSR1" "0,1,2,3"
|
|
bitfld.long 0x00 18. " RSRVD18_18 ,RSRVD18_18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. "MBDSR0 ,MBDSR0" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TDCEN ,TDCEN" "0,1"
|
|
bitfld.long 0x00 14. " TDCFAIL ,TDCFAIL" "0,1"
|
|
bitfld.long 0x00 13. " RSRVD13_13 ,RSRVD13_13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. "TDCOFF ,TDCOFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " RSRVD7_6 ,RSRVD7_6" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TDCVAL ,TDCVAL"
|
|
group ad:0xF0F40C04++0x03
|
|
line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register"
|
|
bitfld.long 0x00 30.--31. " RSRVD31_30 ,RSRVD31_30" "0,1,2,3"
|
|
hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,FPRESDIV"
|
|
bitfld.long 0x00 19. " RSRVD19_19 ,RSRVD19_19" "0,1"
|
|
bitfld.long 0x00 16.--18. " FRJW ,FRJW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. "RSRVD15_15 ,RSRVD15_15" "0,1"
|
|
bitfld.long 0x00 10.--14. " FPROPSEG ,FPROPSEG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " RSRVD9_8 ,RSRVD9_8" "0,1,2,3"
|
|
bitfld.long 0x00 5.--7. " FPSEG1 ,FPSEG1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "RSRVD4_3 ,RSRVD4_3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " FPSEG2 ,FPSEG2" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0F40C08++0x03
|
|
line.long 0x00 "CAN_FDCRC,CAN FD CRC Register"
|
|
bitfld.long 0x00 31. " RSRVD31_31 ,RSRVD31_31" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,FD_MBCRC"
|
|
bitfld.long 0x00 21.--23. " RSRVD23_21 ,RSRVD23_21" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,FD_TXCRC"
|
|
group ad:0xF0F43000++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_EN,APB monitor error inject enable."
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB monitor error inject enable." "0,1"
|
|
group ad:0xF0F43004++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_ECC,APB monitor error inject ECC."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ_ECC ,APB monitor error inject for ECC."
|
|
group ad:0xF0F43008++0x03
|
|
line.long 0x00 "APB_MONITOR_ERR_INJ_WDATA,APB monitor error inject for WDATA."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_WDATA ,APB monitor error inject for WDATA."
|
|
group ad:0xF0F4300C++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS,Function safty error interupt status."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT ,APB PSLVERR status." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT ,stop_doze_sel redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT ,ipg_debug redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT ,fd_enable_plug redundancy signal error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT ,debounce_time redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT ,Handshake complete convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT ,Handshake request convert uncorrectable error," "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT ,DMA handshake eobc parity error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT ,DMA handshake eoba parity error status." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT ,DMA handshake fatal error status." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT ,DMA handshake corrected error status." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT ,DMA handshake uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT ,reg_parity_ej_en redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT ,selftest_mode redundancy signal error status." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT ,pwdata fatal error status." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT ,pwdata corrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT ,pwdata uncorrected error status." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT ,pctl1 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT ,Pctl0 uncorrected error status." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT ,Puser uncorrected error status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT ,paddr uncorrected error status." "0,1"
|
|
group ad:0xF0F43010++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_STATUS_EN,Safty error interrupt status enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_STAT_EN ,mask enable bit of APB PSLVERR status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of stop_doze_sel redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of ipg_debug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of fd_enable_plug redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of debounce_time redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake complete covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake request covert uncorrectable error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eobc parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_STAT_EN ,mask enable bit of DMA handshake eoba parity error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_STAT_EN ,mask enable bit of DMA handshake fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_STAT_EN ,mask enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_STAT_EN ,mask enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of reg_parity_ej_en redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_STAT_EN ,mask enable bit of selftest_mode redundancy signal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_STAT_EN ,mask enable bit of pwdata fatal error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_STAT_EN ,mask enable bit of pwdata corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_STAT_EN ,mask enable bit of pwdata uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_STAT_EN ,mask enable bit of pctl1 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_STAT_EN ,mask enable bit of pctl0 uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_STAT_EN ,mask enable bit of puser uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_STAT_EN ,mask enable bit of paddr uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F43014++0x03
|
|
line.long 0x00 "SAFTY_ERR_IRQ_SIG_EN,Safty error interrupt signal enable."
|
|
bitfld.long 0x00 21. " APB_PSLVERR_INT_SIG_EN ,Interrupt signal enable bit of APB PSLVERR. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 20. " STOP_DOZE_SEL_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of stop_doze_sel redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 19. " IPG_DEBUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of ipg_debug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 18. " FD_ENABLE_PLUG_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of fd_enable_plug redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DEBOUNCE_TIME_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of debounce_time redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
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|
bitfld.long 0x00 16. " HANDSHAKE_COMP_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake complete covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 15. " HANDSHAKE_REQ_CONVERT_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake request covert uncorrectable error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 14. " HANDSHAKE_EOBC_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eobc parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "HANDSHAKE_EOBA_POL_ERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake eoba parity error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 12. " HANDSHAKE_FATAL_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 11. " HANDSHAKE_CORERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake corrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 10. " HANDSHAKE_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of DMA handshake uncorrected error status. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "REG_PARITY_EJ_EN_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of reg_parity_ej_en redundancy signal error . 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 8. " SELFTEST_MODE_REDUNDANCY_ERR_INT_SIG_EN ,Interrupt signal enable bit of selftest_mode redundancy signal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 6. " PWDATA_FATAL_INT_SIG_EN ,Interrupt signal enable bit of pwdata fatal error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 5. " PWDATA_CORERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata corrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "PWDATA_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pwdata uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 3. " PCTL1_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl1 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 2. " PCTL0_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of pctl0 uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
bitfld.long 0x00 1. " PUSER_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of puser uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PADDR_UNCERR_INT_SIG_EN ,Interrupt signal enable bit of paddr uncorrected error. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F43018++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,Interrupt error inject register."
|
|
bitfld.long 0x00 2. " CANFD_IRQ_EJ ,canfd interrupt error inject." "0,1"
|
|
bitfld.long 0x00 1. " CANFD_UNC_ERR_IRQ_EJ ,CANFD safty error uncorrected interrupt error inject." "0,1"
|
|
bitfld.long 0x00 0. " CANFD_COR_ERR_IRQ_EJ ,CANFD safty error corrected interrupt error inject." "0,1"
|
|
group ad:0xF0F43024++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ_EN,Interrupt error inject enable."
|
|
bitfld.long 0x00 0. " EJ_EN ,Interrupt error inject enable. 1'b0: DIsable 1'b1: enable" "0,1"
|
|
group ad:0xF0F43028++0x03
|
|
line.long 0x00 "DMA_HDSK_ERR_INJ,DMA handshake interface error inject."
|
|
bitfld.long 0x00 13.--16. " DMA_FW_CODE_ERR_INJ ,DMA fded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--11. " DMA_FW_DATA_ERR_INJ ,DMA data{ 1'b0,req,single,eobr} error inject," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--8. " DMA_BW_CODE_ERR_INJ ,DMA rded code error inject." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DMA_BW_DATA_ERR_INJ ,DMA data{ ack, eoba,comp,eobc} error inject," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ERR_INJ_EN ,DMA handshake error inject enable. 1'b0:DIsable. 1'b1:enable." "0,1"
|
|
group ad:0xF0F4302C++0x03
|
|
line.long 0x00 "LOWPOWER_MODE,LOWPOWER_MODE"
|
|
bitfld.long 0x00 1. " LOWPOWER_REG_EN ,Low power enable in regiser mode. 1'b0: DIabale 1'b1:enable, LOWPOWER_REG_EN must be at 1'b1." "0,1"
|
|
bitfld.long 0x00 0. " LOWPOWER_MODE ,Low power mode. 1'b0: Low power interface mode 1'b1: Register mode." "0,1"
|
|
group ad:0xF0F43030++0x03
|
|
line.long 0x00 "CANFD_EJ_EN,CANFD error enject enable."
|
|
bitfld.long 0x00 0. " GLOBAL_EJ_EN ,CANFD global error inject enable. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F43034++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0F43038++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable." "0,1"
|
|
group ad:0xF0F4303C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register ."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable ." "0,1"
|
|
group ad:0xF0F43040++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection."
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0F43044++0x03
|
|
line.long 0x00 "HDSK_CONVERT_ERR_INJ,Handshake convert error inject."
|
|
bitfld.long 0x00 2. " CONVERT_COMP_ERR_INJ ,Handshake complete convert error inject." "0,1"
|
|
bitfld.long 0x00 1. " CONVERT_REQ_ERR_INJ ,Handshake request convert error inject." "0,1"
|
|
bitfld.long 0x00 0. " CONVERT_ERR_INJ_EN ,Handshake convert error inject enable." "0,1"
|
|
group ad:0xF0F43048++0x03
|
|
line.long 0x00 "GLITCH_FILTER_CONFIG,CANFD glitch filter configration for stop and doze feature."
|
|
bitfld.long 0x00 0. " GLITCH_FILTER_BYPASS ,Glitch filter bypass. 1'b0: DIsable. 1'b1: enable." "0,1"
|
|
group ad:0xF0F4304C++0x03
|
|
line.long 0x00 "SOFT_RESET,Canfd soft reset."
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset. Used for reset dma handshake status for canfd, 1'b1: In reset status. 1'b0: In normal status." "0,1"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "DMA"
|
|
tree "DMA_SF0"
|
|
width 27.
|
|
group ad:0xF0500000++0x03
|
|
line.long 0x00 "DMA_CORE_CONFIG,DMA_CORE_CONFIG"
|
|
group ad:0xF0500004++0x03
|
|
line.long 0x00 "GENERIC_TIMER_PRE_DIVIDER,GENERIC_TIMER_PRE_DIVIDER"
|
|
bitfld.long 0x00 31. " LOCK ,'LOCK for GENERIC_TIMER_PRE_DIVIDER register; 1: enable" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMRPD ,'Pre-DIvider count.'"
|
|
group ad:0xF0500008++0x03
|
|
line.long 0x00 "GENERIC_TIMER0,GENERIC_TIMER0"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER0 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer0 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer0 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer0 overflow value.'"
|
|
group ad:0xF050000C++0x03
|
|
line.long 0x00 "GENERIC_TIMER1,GENERIC_TIMER1"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER1 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer1 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer1 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer1 overflow value.'"
|
|
group ad:0xF0500010++0x03
|
|
line.long 0x00 "GENERIC_TIMER2,GENERIC_TIMER2"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER2 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer2 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer2 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer2 overflow value.'"
|
|
group ad:0xF0500014++0x03
|
|
line.long 0x00 "GENERIC_TIMER3,GENERIC_TIMER3"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER3 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer3 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer3 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer3 overflow value.'"
|
|
group ad:0xF0500018++0x03
|
|
line.long 0x00 "CH_ARBITRATION_SCHEME,CH_ARBITRATION_SCHEME"
|
|
bitfld.long 0x00 24. " FIFO_ARBIT_SCHEME ,DMA fifo AXI/AHB rw arbitration scheme 0: ahb higher than axi, 1: axi higher than ahb" "0,1"
|
|
bitfld.long 0x00 16.--17. " AHB_ARBIT_SCHEME ,'AHB channel arbitration 0: Default 1: QoS based 2: Round-Robin 3: QoS + Round-Robin (if QoS is equal then apply RR arbitration)'" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " AXI_R_ARBIT_SCHEME ,'AXI read channel arbitration 0: Default 1: QoS based 2: Round-Robin 3: QoS + Round-Robin (if QoS is equal then apply RR arbitration)'" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " AXI_W_ARBIT_SCHEME ,'AXI write channel arbitration 0: Default 1: QoS based 2: Round-Robin 3: QoS + Round-Robin (if QoS is equal then apply RR arbitration)'" "0,1,2,3"
|
|
group ad:0xF050009C++0x03
|
|
line.long 0x00 "DMA_CTRL,DMA_CTRL"
|
|
bitfld.long 0x00 3. " DMA_LOWPOWER_ACCEPT ,1. DMA low power accepted 0. DMA low power not accepted" "0,1"
|
|
bitfld.long 0x00 1. " DMA_LOWPOWER_REQ ,DMA SW low power request, same with Q-channel req" "0,1"
|
|
bitfld.long 0x00 0. " SOFT_RST ,'dma soft reset'" "0,1"
|
|
group ad:0xF05000A0++0x03
|
|
line.long 0x00 "DMA_ERR_INJ_CTRL,DMA_ERR_INJ_CTRL"
|
|
bitfld.long 0x00 31. " LOCK ,'lock the err injection enable'" "0,1"
|
|
bitfld.long 0x00 4.--5. " INSIG_ERR_INJ ,input signal error injection for qreq" "0,1,2,3"
|
|
bitfld.long 0x00 1.--3. " INT_ERR_INJ ,[3:1] control the interrupt error injection position 3'b010 : inject uncerr interrupt 3'b001: inject corerr dma interrupt. 3'b000: error inject to dma interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,'1. error injection enable . 0" "0,1"
|
|
group ad:0xF05000A4++0x03
|
|
line.long 0x00 "LOCK_STEP_ERR_CTRL,LOCK_STEP_ERR_CTRL"
|
|
hexmask.long 0x00 1.--31. 1. " LOCK_STEP_ERR_INJ_SEL ,lock step err injection bits selctions"
|
|
bitfld.long 0x00 0. " LOCK_STEP_ERR_INJ ,'1. dma lock step err injection" "0,1"
|
|
group ad:0xF05000A8++0x03
|
|
line.long 0x00 "APB_ERR_INJ,APB_ERR_INJ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " WECC_INJ ,'apb wecc err injection'"
|
|
group ad:0xF05000AC++0x03
|
|
line.long 0x00 "APB_WDATA_INJ,APB_WDATA_INJ"
|
|
hexmask.long 0x00 0.--31. 1. " WDATA_INJ ,'apb wdata err injection'"
|
|
group ad:0xF05000B0++0x03
|
|
line.long 0x00 "AXI_RECC_INJ,AXI_RECC_INJ"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RECC_INJ ,'AXI recc err injection'"
|
|
group ad:0xF05000B4++0x03
|
|
line.long 0x00 "AXI_RDATA_INJ,AXI_RDATA_INJ"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA_INJ ,'axi rdata[31:0] err injection'"
|
|
group ad:0xF05000B8++0x03
|
|
line.long 0x00 "AXI_RDATA_INJ_CONT,AXI_RDATA_INJ_CONT"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA_INJ ,'axi rdata[63:32] err injection'"
|
|
group ad:0xF05000BC++0x03
|
|
line.long 0x00 "AHB_RECC_INJ,AHB_RECC_INJ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RECC_INJ ,'ahb recc err injection'"
|
|
group ad:0xF05000C0++0x03
|
|
line.long 0x00 "AHB_RDATA_INJ,AHB_RDATA_INJ"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA_INJ ,'ahb rdata[31:0] err injection'"
|
|
group ad:0xF05000C4++0x03
|
|
line.long 0x00 "LB_DATAERR_MASK,LB_DATAERR_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " LB_DATAERR_MASK ,'Local buffer DATA error enjection'"
|
|
group ad:0xF05000C8++0x03
|
|
line.long 0x00 "LB_CODEERR_MASK,LB_CODEERR_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " LB_CODEERR_MASK ,'Local buffer ERROR enjection mask'"
|
|
group ad:0xF05000CC++0x03
|
|
line.long 0x00 "LBC_ERR_ADDR,lbc ecc error address"
|
|
hexmask.long.word 0x00 16.--25. 1. " LBC_UNC_ERR_ADDR ,read address when uncorrectable err occurs"
|
|
hexmask.long.word 0x00 0.--9. 1. " LBC_COR_ERR_ADDR ,read address when correctable err occurs"
|
|
group ad:0xF05000D0++0x03
|
|
line.long 0x00 "DMA_LOCK_STEP_STAT,DMA_LOCK_STEP_STAT"
|
|
bitfld.long 0x00 10. " MISC_LOCK_STEP_ERR_STAT ,'misc err dma_qaccept_n_ls_err" "0,1"
|
|
bitfld.long 0x00 9. " APB_LOCK_STEP_ERR_STAT ,'apb err'" "0,1"
|
|
bitfld.long 0x00 8. " AHB_LOCK_STEP_ERR_STAT ,'ahb err'" "0,1"
|
|
bitfld.long 0x00 7. " DMA_PER_LOCK_STEP_ERR_STAT ,'dma per err '" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "LBC_LOCK_STEP_ERR_STAT ,'lbc err'" "0,1"
|
|
bitfld.long 0x00 5. " DMA_CH_LOCK_STEP_ERR_STAT ,'dma ch err '" "0,1"
|
|
bitfld.long 0x00 4. " W_LOCK_STEP_ERR_STAT ,'axi w err '" "0,1"
|
|
bitfld.long 0x00 3. " R_LOCK_STEP_ERR_STAT ,'axi r err '" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "B_LOCK_STEP_ERR_STAT ,'axi b err '" "0,1"
|
|
bitfld.long 0x00 1. " AR_LOCK_STEP_ERR_STAT ,'axi ar err '" "0,1"
|
|
bitfld.long 0x00 0. " AW_LOCK_STEP_ERR_STAT ,'axi aw err '" "0,1"
|
|
group ad:0xF05000F0++0x03
|
|
line.long 0x00 "PPBASE_ADDR_CTRL,PPBASE_ADDR_CTRL"
|
|
bitfld.long 0x00 31. " LOCK ,'AHB perpheral base address control" "0,1"
|
|
bitfld.long 0x00 24. " PP_OVERWRITE ,'AHB perpheral base address control" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PPBASE_SIZE ,'AHB perpheral base address control unit is 16MB address space'"
|
|
hexmask.long.word 0x00 0.--15. 1. " PPBASE_ADDR ,'AHB perpheral base address control unit is 64KB'"
|
|
group ad:0xF05000F4++0x03
|
|
line.long 0x00 "LBC_ADDR_CTRL,LBC_ADDR_CTRL"
|
|
bitfld.long 0x00 31. " LOCK ,'LBC base address control" "0,1"
|
|
bitfld.long 0x00 24. " LBC_OVERWRITE ,'LBC base address control" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LBCBASE_SIZE ,'LBC base address control unit is 16MB address space'"
|
|
hexmask.long.word 0x00 0.--15. 1. " LBCBASE_ADDR ,'LBC base address control unit is 64KB'"
|
|
group ad:0xF05000F8++0x03
|
|
line.long 0x00 "FIFO_ERR_ADDR,FIFO_ERR_ADDR"
|
|
hexmask.long.word 0x00 16.--25. 1. " FIFO_UNC_ERR_ADDR ,'channel fifo uncorrectable err occur addr'"
|
|
hexmask.long.word 0x00 0.--9. 1. " FIFO_COR_ERR_ADDR ,'channel fifo correctable error occur addr'"
|
|
group ad:0xF0500100++0x03
|
|
line.long 0x00 "FIFO_RDATA_MASK,FIFO_RDATA_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RDATA_MASK ,'channel fifo rdata err enjection mask 0 ~ 31 bit'"
|
|
group ad:0xF0500104++0x03
|
|
line.long 0x00 "FIFO_RDATA_MASK_CONT,FIFO_RDATA_MASK_CONT"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RDATA_MASK_CONT ,'channel fifo rdata err enjection mask 32 ~ 63 bit'"
|
|
group ad:0xF0500108++0x03
|
|
line.long 0x00 "FIFO_RCODE_MASK,FIFO_RCODE_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RCODE_MASK ,'channel fifo ecc code err enjection mask 0 ~ 31 bit'"
|
|
group ad:0xF050010C++0x03
|
|
line.long 0x00 "FIFO_RCODE_MASK_CONT,FIFO_RCODE_MASK_CONT"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RCODE_MASK_CONT ,'channel fifo ecc code err enjection mask 32 ~ 63 bit'"
|
|
group ad:0xF0500110++0x03
|
|
line.long 0x00 "CH_QACK_STATUS,DMA channel-x accept q channel status"
|
|
hexmask.long 0x00 0.--31. 1. " QACK_STATUS ,channel-x q req accept status"
|
|
group ad:0xF0500120++0x03
|
|
line.long 0x00 "DMA_DBG_STATUS,dma debug information"
|
|
hexmask.long 0x00 0.--31. 1. " DEBUG_STATUS ,debug status {ahb_ch_num[4:0],current_state[2:0],htrans[1:0], hready_m, sync_fifo_full,sync_fifo_empty,cmd_fifo_empty,axi_rgen_ch_num[4:0],ot_full,chx_ready,rready_m, axi_wgen_ch_num[4:0],sync_fifo_empty,wready_m,ot_fifo_empty.."
|
|
group ad:0xF05007E0++0x03
|
|
line.long 0x00 "DMA_INTEN,DMA_INTEN"
|
|
bitfld.long 0x00 31. " DMA_INPUT_SIG_ERR ,'dma input lock step en or selftest mode signal err'" "0,1"
|
|
bitfld.long 0x00 30. " CORE1_MONITOR_ERR ,'dma lock step core mask logic error'" "0,1"
|
|
bitfld.long 0x00 29. " LOCK_STEP_ERR ,'dma lock step compare error'" "0,1"
|
|
bitfld.long 0x00 28. " AXI_RD_MONITOR_FATAL ,'axi data correction monitor fatal err'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HRDATA_FATAL ,'ahb data correction monitor fatal err'" "0,1"
|
|
bitfld.long 0x00 26. " PWDATA_FATAL ,'dma apb wdata correction monitor fatal err interrupt'" "0,1"
|
|
bitfld.long 0x00 25. " HRDATA_CORERR ,'dma ahb e2e correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 24. " RDATA_CORERR ,'dma AXI e2e rdata correctable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "PWDATA_CORERR ,'dma apb e2e pwdata correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 22. " FIFO_COR_ERR ,'FIFO CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 21. " CH_COR_ERR ,'CH CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 20. " FIFO_UNC_ERR ,'FIFO UN CORRECT interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CH_UNC_ERR ,'CH UN CORRECT interrupt'" "0,1"
|
|
bitfld.long 0x00 18. " LBC_COR_ERR ,'LOCAL BUFFER Correct Error interrupt'" "0,1"
|
|
bitfld.long 0x00 17. " LBC_UNC_ERR ,'LOCAL BUFFER UNCorrect Error interrupt'" "0,1"
|
|
bitfld.long 0x00 16. " WREADY_UNCERR ,'dma axi e2e wready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BVALID_UNCERR ,'dma axi e2e bvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 14. " BID_UNCERR ,'dma axi e2e bid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 13. " BCTL_UNCERR ,'dma axi e2e Bctrl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 12. " AWREADY_UNCERR ,'dma axi e2e awready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "ARREADY_UNCERR ,'dma axi e2e arready uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 10. " RCTL_UNCERR ,'dma axi e2e rctl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 9. " RDATA_UNCERR ,'dma axi e2e rdata uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 8. " REOBI_UNCERR ,'dma axi e2e reobi uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RID_UNCERR ,'dma axi e2e rid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 6. " RVALID_UNCERR ,'dma axi e2e rvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 5. " HRESP_UNCERR ,'dma ahb e2e uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 4. " HRDATA_UNCERR ,'dma ahb e2e uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PADDR_UNCERR ,'dma apb e2e paddr uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 2. " PCTL1_UNCERR ,'dma apb e2e pctl1 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 1. " PCTL0_UNCERR ,'dma apb e2e pctl0 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCERR ,'dma apb e2e pwdata uncorrectable err interrupt'" "0,1"
|
|
group ad:0xF05007E4++0x03
|
|
line.long 0x00 "DMA_INTCLR,DMA_INTCLR"
|
|
bitfld.long 0x00 31. " DMA_INPUT_SIG_ERR ,'dma input lock step en or selftest mode signal err'" "0,1"
|
|
bitfld.long 0x00 30. " CORE1_MONITOR_ERR ,'dma lock step core mask logic error'" "0,1"
|
|
bitfld.long 0x00 29. " LOCK_STEP_ERR ,'dma lock step compare error'" "0,1"
|
|
bitfld.long 0x00 28. " AXI_RD_MONITOR_FATAL ,'axi data correction monitor fatal err'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HRDATA_FATAL ,'ahb data correction monitor fatal err'" "0,1"
|
|
bitfld.long 0x00 26. " PWDATA_FATAL ,'dma apb wdata correction monitor fatal err interrupt'" "0,1"
|
|
bitfld.long 0x00 25. " HRDATA_CORERR ,'dma ahb e2e correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 24. " RDATA_CORERR ,'dma AXI e2e rdata correctable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "PWDATA_CORERR ,'dma apb e2e pwdata correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 22. " FIFO_COR_ERR ,'FIFO CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 21. " CH_COR_ERR ,'CH CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 20. " FIFO_UNC_ERR ,'FIFO UN CORRECT interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CH_UNC_ERR ,'CH UN CORRECT interrupt'" "0,1"
|
|
bitfld.long 0x00 18. " LBC_COR_ERR ,'LOCAL BUFFER Correct Error interrupt'" "0,1"
|
|
bitfld.long 0x00 17. " LBC_UNC_ERR ,'LOCAL BUFFER UNCorrect Error interrupt'" "0,1"
|
|
bitfld.long 0x00 16. " WREADY_UNCERR ,'dma axi e2e wready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BVALID_UNCERR ,'dma axi e2e bvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 14. " BID_UNCERR ,'dma axi e2e bid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 13. " BCTL_UNCERR ,'dma axi e2e Bctrl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 12. " AWREADY_UNCERR ,'dma axi e2e awready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "ARREADY_UNCERR ,'dma axi e2e arready uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 10. " RCTL_UNCERR ,'dma axi e2e rctl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 9. " RDATA_UNCERR ,'dma axi e2e rdata uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 8. " REOBI_UNCERR ,'dma axi e2e reobi uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RID_UNCERR ,'dma axi e2e rid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 6. " RVALID_UNCERR ,'dma axi e2e rvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 5. " HRESP_UNCERR ,'dma ahb e2e uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 4. " HRDATA_UNCERR ,'dma ahb e2e uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PADDR_UNCERR ,'dma apb e2e paddr uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 2. " PCTL1_UNCERR ,'dma apb e2e pctl1 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 1. " PCTL0_UNCERR ,'dma apb e2e pctl0 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCERR ,'dma apb e2e pwdata uncorrectable err interrupt'" "0,1"
|
|
group ad:0xF05007E8++0x03
|
|
line.long 0x00 "DMA_INTSTAT,DMA_INTSTAT"
|
|
bitfld.long 0x00 31. " DMA_INPUT_SIG_ERR ,'dma input lock step en or selftest mode signal err'" "0,1"
|
|
bitfld.long 0x00 30. " CORE1_MONITOR_ERR ,'dma lock step core mask logic error'" "0,1"
|
|
bitfld.long 0x00 29. " LOCK_STEP_ERR ,'dma lock step compare error'" "0,1"
|
|
bitfld.long 0x00 28. " AXI_RD_MONITOR_FATAL ,'axi data correction monitor fatal err'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HRDATA_FATAL ,'ahb data correction monitor fatal err'" "0,1"
|
|
bitfld.long 0x00 26. " PWDATA_FATAL ,'dma apb wdata correction monitor fatal err interrupt'" "0,1"
|
|
bitfld.long 0x00 25. " HRDATA_CORERR ,'dma ahb e2e correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 24. " RDATA_CORERR ,'dma AXI e2e rdata correctable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "PWDATA_CORERR ,'dma apb e2e pwdata correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 22. " FIFO_COR_ERR ,'FIFO CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 21. " CH_COR_ERR ,'CH CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 20. " FIFO_UNC_ERR ,'FIFO UN CORRECT interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CH_UNC_ERR ,'CH UN CORRECT interrupt'" "0,1"
|
|
bitfld.long 0x00 18. " LBC_COR_ERR ,'LOCAL BUFFER Correct Error interrupt'" "0,1"
|
|
bitfld.long 0x00 17. " LBC_UNC_ERR ,'LOCAL BUFFER UNCorrect Error interrupt'" "0,1"
|
|
bitfld.long 0x00 16. " WREADY_UNCERR ,'dma axi e2e wready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BVALID_UNCERR ,'dma axi e2e bvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 14. " BID_UNCERR ,'dma axi e2e bid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 13. " BCTL_UNCERR ,'dma axi e2e Bctrl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 12. " AWREADY_UNCERR ,'dma axi e2e awready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "ARREADY_UNCERR ,'dma axi e2e arready uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 10. " RCTL_UNCERR ,'dma axi e2e rctl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 9. " RDATA_UNCERR ,'dma axi e2e rdata uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 8. " REOBI_UNCERR ,'dma axi e2e reobi uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RID_UNCERR ,'dma axi e2e rid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 6. " RVALID_UNCERR ,'dma axi e2e rvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 5. " HRESP_UNCERR ,'dma ahb e2e uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 4. " HRDATA_UNCERR ,'dma ahb e2e uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PADDR_UNCERR ,'dma apb e2e paddr uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 2. " PCTL1_UNCERR ,'dma apb e2e pctl1 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 1. " PCTL0_UNCERR ,'dma apb e2e pctl0 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCERR ,'dma apb e2e pwdata uncorrectable err interrupt'" "0,1"
|
|
group ad:0xF05007F0++0x03
|
|
line.long 0x00 "DMA_CONT_INTEN,DMA_CONT_INTEN"
|
|
bitfld.long 0x00 4. " BUTID_ERR ,'AXI B UTID error'" "0,1"
|
|
bitfld.long 0x00 3. " RUTID_ERR ,'AXI R UTID error'" "0,1"
|
|
bitfld.long 0x00 2. " AHB_ERR ,'dma ahb response error'" "0,1"
|
|
bitfld.long 0x00 1. " AXI_WR_ERR ,'DMA axi write response error'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "AXI_RD_ERR ,'DMA axi read response error'" "0,1"
|
|
group ad:0xF05007F4++0x03
|
|
line.long 0x00 "DMA_CONT_INTCLR,DMA_CONT_INTCLR"
|
|
bitfld.long 0x00 4. " BUTID_ERR ,'AXI B UTID error'" "0,1"
|
|
bitfld.long 0x00 3. " RUTID_ERR ,'AXI R UTID error'" "0,1"
|
|
bitfld.long 0x00 2. " AHB_ERR ,'dma ahb response error'" "0,1"
|
|
bitfld.long 0x00 1. " AXI_WR_ERR ,'DMA axi write response error'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "AXI_RD_ERR ,'DMA axi read response error'" "0,1"
|
|
group ad:0xF05007F8++0x03
|
|
line.long 0x00 "DMA_CONT_INTSTAT,DMA_CONT_INTSTAT"
|
|
bitfld.long 0x00 4. " BUTID_ERR ,'AXI B UTID error'" "0,1"
|
|
bitfld.long 0x00 3. " RUTID_ERR ,'AXI R UTID error'" "0,1"
|
|
bitfld.long 0x00 2. " AHB_ERR ,'dma ahb response error'" "0,1"
|
|
bitfld.long 0x00 1. " AXI_WR_ERR ,'DMA axi write response error'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "AXI_RD_ERR ,'DMA axi read response error'" "0,1"
|
|
tree.end
|
|
tree "DMA_AP"
|
|
width 27.
|
|
group ad:0xF3180000++0x03
|
|
line.long 0x00 "DMA_CORE_CONFIG,DMA_CORE_CONFIG"
|
|
group ad:0xF3180004++0x03
|
|
line.long 0x00 "GENERIC_TIMER_PRE_DIVIDER,GENERIC_TIMER_PRE_DIVIDER"
|
|
bitfld.long 0x00 31. " LOCK ,'LOCK for GENERIC_TIMER_PRE_DIVIDER register; 1: enable" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMRPD ,'Pre-DIvider count.'"
|
|
group ad:0xF3180008++0x03
|
|
line.long 0x00 "GENERIC_TIMER0,GENERIC_TIMER0"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER0 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer0 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer0 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer0 overflow value.'"
|
|
group ad:0xF318000C++0x03
|
|
line.long 0x00 "GENERIC_TIMER1,GENERIC_TIMER1"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER1 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer1 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer1 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer1 overflow value.'"
|
|
group ad:0xF3180010++0x03
|
|
line.long 0x00 "GENERIC_TIMER2,GENERIC_TIMER2"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER2 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer2 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer2 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer2 overflow value.'"
|
|
group ad:0xF3180014++0x03
|
|
line.long 0x00 "GENERIC_TIMER3,GENERIC_TIMER3"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER3 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer3 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer3 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer3 overflow value.'"
|
|
group ad:0xF3180018++0x03
|
|
line.long 0x00 "CH_ARBITRATION_SCHEME,CH_ARBITRATION_SCHEME"
|
|
bitfld.long 0x00 24. " FIFO_ARBIT_SCHEME ,DMA fifo AXI/AHB rw arbitration scheme 0: ahb higher than axi, 1: axi higher than ahb" "0,1"
|
|
bitfld.long 0x00 16.--17. " AHB_ARBIT_SCHEME ,'AHB channel arbitration 0: Default 1: QoS based 2: Round-Robin 3: QoS + Round-Robin (if QoS is equal then apply RR arbitration)'" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " AXI_R_ARBIT_SCHEME ,'AXI read channel arbitration 0: Default 1: QoS based 2: Round-Robin 3: QoS + Round-Robin (if QoS is equal then apply RR arbitration)'" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " AXI_W_ARBIT_SCHEME ,'AXI write channel arbitration 0: Default 1: QoS based 2: Round-Robin 3: QoS + Round-Robin (if QoS is equal then apply RR arbitration)'" "0,1,2,3"
|
|
group ad:0xF318009C++0x03
|
|
line.long 0x00 "DMA_CTRL,DMA_CTRL"
|
|
bitfld.long 0x00 3. " DMA_LOWPOWER_ACCEPT ,1. DMA low power accepted 0. DMA low power not accepted" "0,1"
|
|
bitfld.long 0x00 1. " DMA_LOWPOWER_REQ ,DMA SW low power request, same with Q-channel req" "0,1"
|
|
bitfld.long 0x00 0. " SOFT_RST ,'dma soft reset'" "0,1"
|
|
group ad:0xF31800A0++0x03
|
|
line.long 0x00 "DMA_ERR_INJ_CTRL,DMA_ERR_INJ_CTRL"
|
|
bitfld.long 0x00 31. " LOCK ,'lock the err injection enable'" "0,1"
|
|
bitfld.long 0x00 4.--5. " INSIG_ERR_INJ ,input signal error injection for qreq" "0,1,2,3"
|
|
bitfld.long 0x00 1.--3. " INT_ERR_INJ ,[3:1] control the interrupt error injection position 3'b010 : inject uncerr interrupt 3'b001: inject corerr dma interrupt. 3'b000: error inject to dma interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,'1. error injection enable . 0" "0,1"
|
|
group ad:0xF31800A4++0x03
|
|
line.long 0x00 "LOCK_STEP_ERR_CTRL,LOCK_STEP_ERR_CTRL"
|
|
hexmask.long 0x00 1.--31. 1. " LOCK_STEP_ERR_INJ_SEL ,lock step err injection bits selctions"
|
|
bitfld.long 0x00 0. " LOCK_STEP_ERR_INJ ,'1. dma lock step err injection" "0,1"
|
|
group ad:0xF31800A8++0x03
|
|
line.long 0x00 "APB_ERR_INJ,APB_ERR_INJ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " WECC_INJ ,'apb wecc err injection'"
|
|
group ad:0xF31800AC++0x03
|
|
line.long 0x00 "APB_WDATA_INJ,APB_WDATA_INJ"
|
|
hexmask.long 0x00 0.--31. 1. " WDATA_INJ ,'apb wdata err injection'"
|
|
group ad:0xF31800B0++0x03
|
|
line.long 0x00 "AXI_RECC_INJ,AXI_RECC_INJ"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RECC_INJ ,'AXI recc err injection'"
|
|
group ad:0xF31800B4++0x03
|
|
line.long 0x00 "AXI_RDATA_INJ,AXI_RDATA_INJ"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA_INJ ,'axi rdata[31:0] err injection'"
|
|
group ad:0xF31800B8++0x03
|
|
line.long 0x00 "AXI_RDATA_INJ_CONT,AXI_RDATA_INJ_CONT"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA_INJ ,'axi rdata[63:32] err injection'"
|
|
group ad:0xF31800BC++0x03
|
|
line.long 0x00 "AHB_RECC_INJ,AHB_RECC_INJ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RECC_INJ ,'ahb recc err injection'"
|
|
group ad:0xF31800C0++0x03
|
|
line.long 0x00 "AHB_RDATA_INJ,AHB_RDATA_INJ"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA_INJ ,'ahb rdata[31:0] err injection'"
|
|
group ad:0xF31800C4++0x03
|
|
line.long 0x00 "LB_DATAERR_MASK,LB_DATAERR_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " LB_DATAERR_MASK ,'Local buffer DATA error enjection'"
|
|
group ad:0xF31800C8++0x03
|
|
line.long 0x00 "LB_CODEERR_MASK,LB_CODEERR_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " LB_CODEERR_MASK ,'Local buffer ERROR enjection mask'"
|
|
group ad:0xF31800CC++0x03
|
|
line.long 0x00 "LBC_ERR_ADDR,lbc ecc error address"
|
|
hexmask.long.word 0x00 16.--25. 1. " LBC_UNC_ERR_ADDR ,read address when uncorrectable err occurs"
|
|
hexmask.long.word 0x00 0.--9. 1. " LBC_COR_ERR_ADDR ,read address when correctable err occurs"
|
|
group ad:0xF31800D0++0x03
|
|
line.long 0x00 "DMA_LOCK_STEP_STAT,DMA_LOCK_STEP_STAT"
|
|
bitfld.long 0x00 10. " MISC_LOCK_STEP_ERR_STAT ,'misc err dma_qaccept_n_ls_err" "0,1"
|
|
bitfld.long 0x00 9. " APB_LOCK_STEP_ERR_STAT ,'apb err'" "0,1"
|
|
bitfld.long 0x00 8. " AHB_LOCK_STEP_ERR_STAT ,'ahb err'" "0,1"
|
|
bitfld.long 0x00 7. " DMA_PER_LOCK_STEP_ERR_STAT ,'dma per err '" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "LBC_LOCK_STEP_ERR_STAT ,'lbc err'" "0,1"
|
|
bitfld.long 0x00 5. " DMA_CH_LOCK_STEP_ERR_STAT ,'dma ch err '" "0,1"
|
|
bitfld.long 0x00 4. " W_LOCK_STEP_ERR_STAT ,'axi w err '" "0,1"
|
|
bitfld.long 0x00 3. " R_LOCK_STEP_ERR_STAT ,'axi r err '" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "B_LOCK_STEP_ERR_STAT ,'axi b err '" "0,1"
|
|
bitfld.long 0x00 1. " AR_LOCK_STEP_ERR_STAT ,'axi ar err '" "0,1"
|
|
bitfld.long 0x00 0. " AW_LOCK_STEP_ERR_STAT ,'axi aw err '" "0,1"
|
|
group ad:0xF31800F0++0x03
|
|
line.long 0x00 "PPBASE_ADDR_CTRL,PPBASE_ADDR_CTRL"
|
|
bitfld.long 0x00 31. " LOCK ,'AHB perpheral base address control" "0,1"
|
|
bitfld.long 0x00 24. " PP_OVERWRITE ,'AHB perpheral base address control" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PPBASE_SIZE ,'AHB perpheral base address control unit is 16MB address space'"
|
|
hexmask.long.word 0x00 0.--15. 1. " PPBASE_ADDR ,'AHB perpheral base address control unit is 64KB'"
|
|
group ad:0xF31800F4++0x03
|
|
line.long 0x00 "LBC_ADDR_CTRL,LBC_ADDR_CTRL"
|
|
bitfld.long 0x00 31. " LOCK ,'LBC base address control" "0,1"
|
|
bitfld.long 0x00 24. " LBC_OVERWRITE ,'LBC base address control" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LBCBASE_SIZE ,'LBC base address control unit is 16MB address space'"
|
|
hexmask.long.word 0x00 0.--15. 1. " LBCBASE_ADDR ,'LBC base address control unit is 64KB'"
|
|
group ad:0xF31800F8++0x03
|
|
line.long 0x00 "FIFO_ERR_ADDR,FIFO_ERR_ADDR"
|
|
hexmask.long.word 0x00 16.--25. 1. " FIFO_UNC_ERR_ADDR ,'channel fifo uncorrectable err occur addr'"
|
|
hexmask.long.word 0x00 0.--9. 1. " FIFO_COR_ERR_ADDR ,'channel fifo correctable error occur addr'"
|
|
group ad:0xF3180100++0x03
|
|
line.long 0x00 "FIFO_RDATA_MASK,FIFO_RDATA_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RDATA_MASK ,'channel fifo rdata err enjection mask 0 ~ 31 bit'"
|
|
group ad:0xF3180104++0x03
|
|
line.long 0x00 "FIFO_RDATA_MASK_CONT,FIFO_RDATA_MASK_CONT"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RDATA_MASK_CONT ,'channel fifo rdata err enjection mask 32 ~ 63 bit'"
|
|
group ad:0xF3180108++0x03
|
|
line.long 0x00 "FIFO_RCODE_MASK,FIFO_RCODE_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RCODE_MASK ,'channel fifo ecc code err enjection mask 0 ~ 31 bit'"
|
|
group ad:0xF318010C++0x03
|
|
line.long 0x00 "FIFO_RCODE_MASK_CONT,FIFO_RCODE_MASK_CONT"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RCODE_MASK_CONT ,'channel fifo ecc code err enjection mask 32 ~ 63 bit'"
|
|
group ad:0xF3180110++0x03
|
|
line.long 0x00 "CH_QACK_STATUS,DMA channel-x accept q channel status"
|
|
hexmask.long 0x00 0.--31. 1. " QACK_STATUS ,channel-x q req accept status"
|
|
group ad:0xF3180120++0x03
|
|
line.long 0x00 "DMA_DBG_STATUS,dma debug information"
|
|
hexmask.long 0x00 0.--31. 1. " DEBUG_STATUS ,debug status {ahb_ch_num[4:0],current_state[2:0],htrans[1:0], hready_m, sync_fifo_full,sync_fifo_empty,cmd_fifo_empty,axi_rgen_ch_num[4:0],ot_full,chx_ready,rready_m, axi_wgen_ch_num[4:0],sync_fifo_empty,wready_m,ot_fifo_empty.."
|
|
group ad:0xF31807E0++0x03
|
|
line.long 0x00 "DMA_INTEN,DMA_INTEN"
|
|
bitfld.long 0x00 31. " DMA_INPUT_SIG_ERR ,'dma input lock step en or selftest mode signal err'" "0,1"
|
|
bitfld.long 0x00 30. " CORE1_MONITOR_ERR ,'dma lock step core mask logic error'" "0,1"
|
|
bitfld.long 0x00 29. " LOCK_STEP_ERR ,'dma lock step compare error'" "0,1"
|
|
bitfld.long 0x00 28. " AXI_RD_MONITOR_FATAL ,'axi data correction monitor fatal err'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HRDATA_FATAL ,'ahb data correction monitor fatal err'" "0,1"
|
|
bitfld.long 0x00 26. " PWDATA_FATAL ,'dma apb wdata correction monitor fatal err interrupt'" "0,1"
|
|
bitfld.long 0x00 25. " HRDATA_CORERR ,'dma ahb e2e correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 24. " RDATA_CORERR ,'dma AXI e2e rdata correctable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "PWDATA_CORERR ,'dma apb e2e pwdata correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 22. " FIFO_COR_ERR ,'FIFO CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 21. " CH_COR_ERR ,'CH CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 20. " FIFO_UNC_ERR ,'FIFO UN CORRECT interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CH_UNC_ERR ,'CH UN CORRECT interrupt'" "0,1"
|
|
bitfld.long 0x00 18. " LBC_COR_ERR ,'LOCAL BUFFER Correct Error interrupt'" "0,1"
|
|
bitfld.long 0x00 17. " LBC_UNC_ERR ,'LOCAL BUFFER UNCorrect Error interrupt'" "0,1"
|
|
bitfld.long 0x00 16. " WREADY_UNCERR ,'dma axi e2e wready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BVALID_UNCERR ,'dma axi e2e bvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 14. " BID_UNCERR ,'dma axi e2e bid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 13. " BCTL_UNCERR ,'dma axi e2e Bctrl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 12. " AWREADY_UNCERR ,'dma axi e2e awready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "ARREADY_UNCERR ,'dma axi e2e arready uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 10. " RCTL_UNCERR ,'dma axi e2e rctl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 9. " RDATA_UNCERR ,'dma axi e2e rdata uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 8. " REOBI_UNCERR ,'dma axi e2e reobi uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RID_UNCERR ,'dma axi e2e rid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 6. " RVALID_UNCERR ,'dma axi e2e rvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 5. " HRESP_UNCERR ,'dma ahb e2e uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 4. " HRDATA_UNCERR ,'dma ahb e2e uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PADDR_UNCERR ,'dma apb e2e paddr uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 2. " PCTL1_UNCERR ,'dma apb e2e pctl1 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 1. " PCTL0_UNCERR ,'dma apb e2e pctl0 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCERR ,'dma apb e2e pwdata uncorrectable err interrupt'" "0,1"
|
|
group ad:0xF31807E4++0x03
|
|
line.long 0x00 "DMA_INTCLR,DMA_INTCLR"
|
|
bitfld.long 0x00 31. " DMA_INPUT_SIG_ERR ,'dma input lock step en or selftest mode signal err'" "0,1"
|
|
bitfld.long 0x00 30. " CORE1_MONITOR_ERR ,'dma lock step core mask logic error'" "0,1"
|
|
bitfld.long 0x00 29. " LOCK_STEP_ERR ,'dma lock step compare error'" "0,1"
|
|
bitfld.long 0x00 28. " AXI_RD_MONITOR_FATAL ,'axi data correction monitor fatal err'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HRDATA_FATAL ,'ahb data correction monitor fatal err'" "0,1"
|
|
bitfld.long 0x00 26. " PWDATA_FATAL ,'dma apb wdata correction monitor fatal err interrupt'" "0,1"
|
|
bitfld.long 0x00 25. " HRDATA_CORERR ,'dma ahb e2e correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 24. " RDATA_CORERR ,'dma AXI e2e rdata correctable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "PWDATA_CORERR ,'dma apb e2e pwdata correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 22. " FIFO_COR_ERR ,'FIFO CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 21. " CH_COR_ERR ,'CH CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 20. " FIFO_UNC_ERR ,'FIFO UN CORRECT interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CH_UNC_ERR ,'CH UN CORRECT interrupt'" "0,1"
|
|
bitfld.long 0x00 18. " LBC_COR_ERR ,'LOCAL BUFFER Correct Error interrupt'" "0,1"
|
|
bitfld.long 0x00 17. " LBC_UNC_ERR ,'LOCAL BUFFER UNCorrect Error interrupt'" "0,1"
|
|
bitfld.long 0x00 16. " WREADY_UNCERR ,'dma axi e2e wready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BVALID_UNCERR ,'dma axi e2e bvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 14. " BID_UNCERR ,'dma axi e2e bid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 13. " BCTL_UNCERR ,'dma axi e2e Bctrl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 12. " AWREADY_UNCERR ,'dma axi e2e awready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "ARREADY_UNCERR ,'dma axi e2e arready uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 10. " RCTL_UNCERR ,'dma axi e2e rctl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 9. " RDATA_UNCERR ,'dma axi e2e rdata uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 8. " REOBI_UNCERR ,'dma axi e2e reobi uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RID_UNCERR ,'dma axi e2e rid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 6. " RVALID_UNCERR ,'dma axi e2e rvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 5. " HRESP_UNCERR ,'dma ahb e2e uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 4. " HRDATA_UNCERR ,'dma ahb e2e uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PADDR_UNCERR ,'dma apb e2e paddr uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 2. " PCTL1_UNCERR ,'dma apb e2e pctl1 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 1. " PCTL0_UNCERR ,'dma apb e2e pctl0 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCERR ,'dma apb e2e pwdata uncorrectable err interrupt'" "0,1"
|
|
group ad:0xF31807E8++0x03
|
|
line.long 0x00 "DMA_INTSTAT,DMA_INTSTAT"
|
|
bitfld.long 0x00 31. " DMA_INPUT_SIG_ERR ,'dma input lock step en or selftest mode signal err'" "0,1"
|
|
bitfld.long 0x00 30. " CORE1_MONITOR_ERR ,'dma lock step core mask logic error'" "0,1"
|
|
bitfld.long 0x00 29. " LOCK_STEP_ERR ,'dma lock step compare error'" "0,1"
|
|
bitfld.long 0x00 28. " AXI_RD_MONITOR_FATAL ,'axi data correction monitor fatal err'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HRDATA_FATAL ,'ahb data correction monitor fatal err'" "0,1"
|
|
bitfld.long 0x00 26. " PWDATA_FATAL ,'dma apb wdata correction monitor fatal err interrupt'" "0,1"
|
|
bitfld.long 0x00 25. " HRDATA_CORERR ,'dma ahb e2e correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 24. " RDATA_CORERR ,'dma AXI e2e rdata correctable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "PWDATA_CORERR ,'dma apb e2e pwdata correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 22. " FIFO_COR_ERR ,'FIFO CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 21. " CH_COR_ERR ,'CH CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 20. " FIFO_UNC_ERR ,'FIFO UN CORRECT interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CH_UNC_ERR ,'CH UN CORRECT interrupt'" "0,1"
|
|
bitfld.long 0x00 18. " LBC_COR_ERR ,'LOCAL BUFFER Correct Error interrupt'" "0,1"
|
|
bitfld.long 0x00 17. " LBC_UNC_ERR ,'LOCAL BUFFER UNCorrect Error interrupt'" "0,1"
|
|
bitfld.long 0x00 16. " WREADY_UNCERR ,'dma axi e2e wready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BVALID_UNCERR ,'dma axi e2e bvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 14. " BID_UNCERR ,'dma axi e2e bid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 13. " BCTL_UNCERR ,'dma axi e2e Bctrl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 12. " AWREADY_UNCERR ,'dma axi e2e awready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "ARREADY_UNCERR ,'dma axi e2e arready uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 10. " RCTL_UNCERR ,'dma axi e2e rctl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 9. " RDATA_UNCERR ,'dma axi e2e rdata uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 8. " REOBI_UNCERR ,'dma axi e2e reobi uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RID_UNCERR ,'dma axi e2e rid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 6. " RVALID_UNCERR ,'dma axi e2e rvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 5. " HRESP_UNCERR ,'dma ahb e2e uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 4. " HRDATA_UNCERR ,'dma ahb e2e uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PADDR_UNCERR ,'dma apb e2e paddr uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 2. " PCTL1_UNCERR ,'dma apb e2e pctl1 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 1. " PCTL0_UNCERR ,'dma apb e2e pctl0 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCERR ,'dma apb e2e pwdata uncorrectable err interrupt'" "0,1"
|
|
group ad:0xF31807F0++0x03
|
|
line.long 0x00 "DMA_CONT_INTEN,DMA_CONT_INTEN"
|
|
bitfld.long 0x00 4. " BUTID_ERR ,'AXI B UTID error'" "0,1"
|
|
bitfld.long 0x00 3. " RUTID_ERR ,'AXI R UTID error'" "0,1"
|
|
bitfld.long 0x00 2. " AHB_ERR ,'dma ahb response error'" "0,1"
|
|
bitfld.long 0x00 1. " AXI_WR_ERR ,'DMA axi write response error'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "AXI_RD_ERR ,'DMA axi read response error'" "0,1"
|
|
group ad:0xF31807F4++0x03
|
|
line.long 0x00 "DMA_CONT_INTCLR,DMA_CONT_INTCLR"
|
|
bitfld.long 0x00 4. " BUTID_ERR ,'AXI B UTID error'" "0,1"
|
|
bitfld.long 0x00 3. " RUTID_ERR ,'AXI R UTID error'" "0,1"
|
|
bitfld.long 0x00 2. " AHB_ERR ,'dma ahb response error'" "0,1"
|
|
bitfld.long 0x00 1. " AXI_WR_ERR ,'DMA axi write response error'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "AXI_RD_ERR ,'DMA axi read response error'" "0,1"
|
|
group ad:0xF31807F8++0x03
|
|
line.long 0x00 "DMA_CONT_INTSTAT,DMA_CONT_INTSTAT"
|
|
bitfld.long 0x00 4. " BUTID_ERR ,'AXI B UTID error'" "0,1"
|
|
bitfld.long 0x00 3. " RUTID_ERR ,'AXI R UTID error'" "0,1"
|
|
bitfld.long 0x00 2. " AHB_ERR ,'dma ahb response error'" "0,1"
|
|
bitfld.long 0x00 1. " AXI_WR_ERR ,'DMA axi write response error'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "AXI_RD_ERR ,'DMA axi read response error'" "0,1"
|
|
tree.end
|
|
tree "DMA_SF1"
|
|
width 27.
|
|
group ad:0xF0540000++0x03
|
|
line.long 0x00 "DMA_CORE_CONFIG,DMA_CORE_CONFIG"
|
|
group ad:0xF0540004++0x03
|
|
line.long 0x00 "GENERIC_TIMER_PRE_DIVIDER,GENERIC_TIMER_PRE_DIVIDER"
|
|
bitfld.long 0x00 31. " LOCK ,'LOCK for GENERIC_TIMER_PRE_DIVIDER register; 1: enable" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMRPD ,'Pre-DIvider count.'"
|
|
group ad:0xF0540008++0x03
|
|
line.long 0x00 "GENERIC_TIMER0,GENERIC_TIMER0"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER0 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer0 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer0 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer0 overflow value.'"
|
|
group ad:0xF054000C++0x03
|
|
line.long 0x00 "GENERIC_TIMER1,GENERIC_TIMER1"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER1 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer1 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer1 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer1 overflow value.'"
|
|
group ad:0xF0540010++0x03
|
|
line.long 0x00 "GENERIC_TIMER2,GENERIC_TIMER2"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER2 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer2 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer2 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer2 overflow value.'"
|
|
group ad:0xF0540014++0x03
|
|
line.long 0x00 "GENERIC_TIMER3,GENERIC_TIMER3"
|
|
bitfld.long 0x00 31. " LOCK ,'Lock for GENERIC_TIMER3 register; 1: enable" "0,1"
|
|
bitfld.long 0x00 17.--18. " MODE ,'Generic Timer3 mode for count clear ;0:Clear by timer overflow value; 1:Clear by ack of handshake signal; 2:Clear by comp of handshake signal; 3:RESERVED.'" "0,1,2,3"
|
|
bitfld.long 0x00 16. " ENABLE ,'Generic Timer3 enable.'" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " GTMROV ,'Generic Timer3 overflow value.'"
|
|
group ad:0xF0540018++0x03
|
|
line.long 0x00 "CH_ARBITRATION_SCHEME,CH_ARBITRATION_SCHEME"
|
|
bitfld.long 0x00 24. " FIFO_ARBIT_SCHEME ,DMA fifo AXI/AHB rw arbitration scheme 0: ahb higher than axi, 1: axi higher than ahb" "0,1"
|
|
bitfld.long 0x00 16.--17. " AHB_ARBIT_SCHEME ,'AHB channel arbitration 0: Default 1: QoS based 2: Round-Robin 3: QoS + Round-Robin (if QoS is equal then apply RR arbitration)'" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " AXI_R_ARBIT_SCHEME ,'AXI read channel arbitration 0: Default 1: QoS based 2: Round-Robin 3: QoS + Round-Robin (if QoS is equal then apply RR arbitration)'" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " AXI_W_ARBIT_SCHEME ,'AXI write channel arbitration 0: Default 1: QoS based 2: Round-Robin 3: QoS + Round-Robin (if QoS is equal then apply RR arbitration)'" "0,1,2,3"
|
|
group ad:0xF054009C++0x03
|
|
line.long 0x00 "DMA_CTRL,DMA_CTRL"
|
|
bitfld.long 0x00 3. " DMA_LOWPOWER_ACCEPT ,1. DMA low power accepted 0. DMA low power not accepted" "0,1"
|
|
bitfld.long 0x00 1. " DMA_LOWPOWER_REQ ,DMA SW low power request, same with Q-channel req" "0,1"
|
|
bitfld.long 0x00 0. " SOFT_RST ,'dma soft reset'" "0,1"
|
|
group ad:0xF05400A0++0x03
|
|
line.long 0x00 "DMA_ERR_INJ_CTRL,DMA_ERR_INJ_CTRL"
|
|
bitfld.long 0x00 31. " LOCK ,'lock the err injection enable'" "0,1"
|
|
bitfld.long 0x00 4.--5. " INSIG_ERR_INJ ,input signal error injection for qreq" "0,1,2,3"
|
|
bitfld.long 0x00 1.--3. " INT_ERR_INJ ,[3:1] control the interrupt error injection position 3'b010 : inject uncerr interrupt 3'b001: inject corerr dma interrupt. 3'b000: error inject to dma interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,'1. error injection enable . 0" "0,1"
|
|
group ad:0xF05400A4++0x03
|
|
line.long 0x00 "LOCK_STEP_ERR_CTRL,LOCK_STEP_ERR_CTRL"
|
|
hexmask.long 0x00 1.--31. 1. " LOCK_STEP_ERR_INJ_SEL ,lock step err injection bits selctions"
|
|
bitfld.long 0x00 0. " LOCK_STEP_ERR_INJ ,'1. dma lock step err injection" "0,1"
|
|
group ad:0xF05400A8++0x03
|
|
line.long 0x00 "APB_ERR_INJ,APB_ERR_INJ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " WECC_INJ ,'apb wecc err injection'"
|
|
group ad:0xF05400AC++0x03
|
|
line.long 0x00 "APB_WDATA_INJ,APB_WDATA_INJ"
|
|
hexmask.long 0x00 0.--31. 1. " WDATA_INJ ,'apb wdata err injection'"
|
|
group ad:0xF05400B0++0x03
|
|
line.long 0x00 "AXI_RECC_INJ,AXI_RECC_INJ"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RECC_INJ ,'AXI recc err injection'"
|
|
group ad:0xF05400B4++0x03
|
|
line.long 0x00 "AXI_RDATA_INJ,AXI_RDATA_INJ"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA_INJ ,'axi rdata[31:0] err injection'"
|
|
group ad:0xF05400B8++0x03
|
|
line.long 0x00 "AXI_RDATA_INJ_CONT,AXI_RDATA_INJ_CONT"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA_INJ ,'axi rdata[63:32] err injection'"
|
|
group ad:0xF05400BC++0x03
|
|
line.long 0x00 "AHB_RECC_INJ,AHB_RECC_INJ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RECC_INJ ,'ahb recc err injection'"
|
|
group ad:0xF05400C0++0x03
|
|
line.long 0x00 "AHB_RDATA_INJ,AHB_RDATA_INJ"
|
|
hexmask.long 0x00 0.--31. 1. " RDATA_INJ ,'ahb rdata[31:0] err injection'"
|
|
group ad:0xF05400C4++0x03
|
|
line.long 0x00 "LB_DATAERR_MASK,LB_DATAERR_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " LB_DATAERR_MASK ,'Local buffer DATA error enjection'"
|
|
group ad:0xF05400C8++0x03
|
|
line.long 0x00 "LB_CODEERR_MASK,LB_CODEERR_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " LB_CODEERR_MASK ,'Local buffer ERROR enjection mask'"
|
|
group ad:0xF05400CC++0x03
|
|
line.long 0x00 "LBC_ERR_ADDR,lbc ecc error address"
|
|
hexmask.long.word 0x00 16.--25. 1. " LBC_UNC_ERR_ADDR ,read address when uncorrectable err occurs"
|
|
hexmask.long.word 0x00 0.--9. 1. " LBC_COR_ERR_ADDR ,read address when correctable err occurs"
|
|
group ad:0xF05400D0++0x03
|
|
line.long 0x00 "DMA_LOCK_STEP_STAT,DMA_LOCK_STEP_STAT"
|
|
bitfld.long 0x00 10. " MISC_LOCK_STEP_ERR_STAT ,'misc err dma_qaccept_n_ls_err" "0,1"
|
|
bitfld.long 0x00 9. " APB_LOCK_STEP_ERR_STAT ,'apb err'" "0,1"
|
|
bitfld.long 0x00 8. " AHB_LOCK_STEP_ERR_STAT ,'ahb err'" "0,1"
|
|
bitfld.long 0x00 7. " DMA_PER_LOCK_STEP_ERR_STAT ,'dma per err '" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "LBC_LOCK_STEP_ERR_STAT ,'lbc err'" "0,1"
|
|
bitfld.long 0x00 5. " DMA_CH_LOCK_STEP_ERR_STAT ,'dma ch err '" "0,1"
|
|
bitfld.long 0x00 4. " W_LOCK_STEP_ERR_STAT ,'axi w err '" "0,1"
|
|
bitfld.long 0x00 3. " R_LOCK_STEP_ERR_STAT ,'axi r err '" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "B_LOCK_STEP_ERR_STAT ,'axi b err '" "0,1"
|
|
bitfld.long 0x00 1. " AR_LOCK_STEP_ERR_STAT ,'axi ar err '" "0,1"
|
|
bitfld.long 0x00 0. " AW_LOCK_STEP_ERR_STAT ,'axi aw err '" "0,1"
|
|
group ad:0xF05400F0++0x03
|
|
line.long 0x00 "PPBASE_ADDR_CTRL,PPBASE_ADDR_CTRL"
|
|
bitfld.long 0x00 31. " LOCK ,'AHB perpheral base address control" "0,1"
|
|
bitfld.long 0x00 24. " PP_OVERWRITE ,'AHB perpheral base address control" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PPBASE_SIZE ,'AHB perpheral base address control unit is 16MB address space'"
|
|
hexmask.long.word 0x00 0.--15. 1. " PPBASE_ADDR ,'AHB perpheral base address control unit is 64KB'"
|
|
group ad:0xF05400F4++0x03
|
|
line.long 0x00 "LBC_ADDR_CTRL,LBC_ADDR_CTRL"
|
|
bitfld.long 0x00 31. " LOCK ,'LBC base address control" "0,1"
|
|
bitfld.long 0x00 24. " LBC_OVERWRITE ,'LBC base address control" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LBCBASE_SIZE ,'LBC base address control unit is 16MB address space'"
|
|
hexmask.long.word 0x00 0.--15. 1. " LBCBASE_ADDR ,'LBC base address control unit is 64KB'"
|
|
group ad:0xF05400F8++0x03
|
|
line.long 0x00 "FIFO_ERR_ADDR,FIFO_ERR_ADDR"
|
|
hexmask.long.word 0x00 16.--25. 1. " FIFO_UNC_ERR_ADDR ,'channel fifo uncorrectable err occur addr'"
|
|
hexmask.long.word 0x00 0.--9. 1. " FIFO_COR_ERR_ADDR ,'channel fifo correctable error occur addr'"
|
|
group ad:0xF0540100++0x03
|
|
line.long 0x00 "FIFO_RDATA_MASK,FIFO_RDATA_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RDATA_MASK ,'channel fifo rdata err enjection mask 0 ~ 31 bit'"
|
|
group ad:0xF0540104++0x03
|
|
line.long 0x00 "FIFO_RDATA_MASK_CONT,FIFO_RDATA_MASK_CONT"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RDATA_MASK_CONT ,'channel fifo rdata err enjection mask 32 ~ 63 bit'"
|
|
group ad:0xF0540108++0x03
|
|
line.long 0x00 "FIFO_RCODE_MASK,FIFO_RCODE_MASK"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RCODE_MASK ,'channel fifo ecc code err enjection mask 0 ~ 31 bit'"
|
|
group ad:0xF054010C++0x03
|
|
line.long 0x00 "FIFO_RCODE_MASK_CONT,FIFO_RCODE_MASK_CONT"
|
|
hexmask.long 0x00 0.--31. 1. " FIFO_RCODE_MASK_CONT ,'channel fifo ecc code err enjection mask 32 ~ 63 bit'"
|
|
group ad:0xF0540110++0x03
|
|
line.long 0x00 "CH_QACK_STATUS,DMA channel-x accept q channel status"
|
|
hexmask.long 0x00 0.--31. 1. " QACK_STATUS ,channel-x q req accept status"
|
|
group ad:0xF0540120++0x03
|
|
line.long 0x00 "DMA_DBG_STATUS,dma debug information"
|
|
hexmask.long 0x00 0.--31. 1. " DEBUG_STATUS ,debug status {ahb_ch_num[4:0],current_state[2:0],htrans[1:0], hready_m, sync_fifo_full,sync_fifo_empty,cmd_fifo_empty,axi_rgen_ch_num[4:0],ot_full,chx_ready,rready_m, axi_wgen_ch_num[4:0],sync_fifo_empty,wready_m,ot_fifo_empty.."
|
|
group ad:0xF05407E0++0x03
|
|
line.long 0x00 "DMA_INTEN,DMA_INTEN"
|
|
bitfld.long 0x00 31. " DMA_INPUT_SIG_ERR ,'dma input lock step en or selftest mode signal err'" "0,1"
|
|
bitfld.long 0x00 30. " CORE1_MONITOR_ERR ,'dma lock step core mask logic error'" "0,1"
|
|
bitfld.long 0x00 29. " LOCK_STEP_ERR ,'dma lock step compare error'" "0,1"
|
|
bitfld.long 0x00 28. " AXI_RD_MONITOR_FATAL ,'axi data correction monitor fatal err'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HRDATA_FATAL ,'ahb data correction monitor fatal err'" "0,1"
|
|
bitfld.long 0x00 26. " PWDATA_FATAL ,'dma apb wdata correction monitor fatal err interrupt'" "0,1"
|
|
bitfld.long 0x00 25. " HRDATA_CORERR ,'dma ahb e2e correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 24. " RDATA_CORERR ,'dma AXI e2e rdata correctable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "PWDATA_CORERR ,'dma apb e2e pwdata correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 22. " FIFO_COR_ERR ,'FIFO CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 21. " CH_COR_ERR ,'CH CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 20. " FIFO_UNC_ERR ,'FIFO UN CORRECT interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CH_UNC_ERR ,'CH UN CORRECT interrupt'" "0,1"
|
|
bitfld.long 0x00 18. " LBC_COR_ERR ,'LOCAL BUFFER Correct Error interrupt'" "0,1"
|
|
bitfld.long 0x00 17. " LBC_UNC_ERR ,'LOCAL BUFFER UNCorrect Error interrupt'" "0,1"
|
|
bitfld.long 0x00 16. " WREADY_UNCERR ,'dma axi e2e wready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BVALID_UNCERR ,'dma axi e2e bvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 14. " BID_UNCERR ,'dma axi e2e bid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 13. " BCTL_UNCERR ,'dma axi e2e Bctrl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 12. " AWREADY_UNCERR ,'dma axi e2e awready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "ARREADY_UNCERR ,'dma axi e2e arready uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 10. " RCTL_UNCERR ,'dma axi e2e rctl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 9. " RDATA_UNCERR ,'dma axi e2e rdata uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 8. " REOBI_UNCERR ,'dma axi e2e reobi uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RID_UNCERR ,'dma axi e2e rid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 6. " RVALID_UNCERR ,'dma axi e2e rvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 5. " HRESP_UNCERR ,'dma ahb e2e uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 4. " HRDATA_UNCERR ,'dma ahb e2e uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PADDR_UNCERR ,'dma apb e2e paddr uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 2. " PCTL1_UNCERR ,'dma apb e2e pctl1 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 1. " PCTL0_UNCERR ,'dma apb e2e pctl0 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCERR ,'dma apb e2e pwdata uncorrectable err interrupt'" "0,1"
|
|
group ad:0xF05407E4++0x03
|
|
line.long 0x00 "DMA_INTCLR,DMA_INTCLR"
|
|
bitfld.long 0x00 31. " DMA_INPUT_SIG_ERR ,'dma input lock step en or selftest mode signal err'" "0,1"
|
|
bitfld.long 0x00 30. " CORE1_MONITOR_ERR ,'dma lock step core mask logic error'" "0,1"
|
|
bitfld.long 0x00 29. " LOCK_STEP_ERR ,'dma lock step compare error'" "0,1"
|
|
bitfld.long 0x00 28. " AXI_RD_MONITOR_FATAL ,'axi data correction monitor fatal err'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HRDATA_FATAL ,'ahb data correction monitor fatal err'" "0,1"
|
|
bitfld.long 0x00 26. " PWDATA_FATAL ,'dma apb wdata correction monitor fatal err interrupt'" "0,1"
|
|
bitfld.long 0x00 25. " HRDATA_CORERR ,'dma ahb e2e correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 24. " RDATA_CORERR ,'dma AXI e2e rdata correctable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "PWDATA_CORERR ,'dma apb e2e pwdata correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 22. " FIFO_COR_ERR ,'FIFO CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 21. " CH_COR_ERR ,'CH CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 20. " FIFO_UNC_ERR ,'FIFO UN CORRECT interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CH_UNC_ERR ,'CH UN CORRECT interrupt'" "0,1"
|
|
bitfld.long 0x00 18. " LBC_COR_ERR ,'LOCAL BUFFER Correct Error interrupt'" "0,1"
|
|
bitfld.long 0x00 17. " LBC_UNC_ERR ,'LOCAL BUFFER UNCorrect Error interrupt'" "0,1"
|
|
bitfld.long 0x00 16. " WREADY_UNCERR ,'dma axi e2e wready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BVALID_UNCERR ,'dma axi e2e bvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 14. " BID_UNCERR ,'dma axi e2e bid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 13. " BCTL_UNCERR ,'dma axi e2e Bctrl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 12. " AWREADY_UNCERR ,'dma axi e2e awready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "ARREADY_UNCERR ,'dma axi e2e arready uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 10. " RCTL_UNCERR ,'dma axi e2e rctl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 9. " RDATA_UNCERR ,'dma axi e2e rdata uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 8. " REOBI_UNCERR ,'dma axi e2e reobi uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RID_UNCERR ,'dma axi e2e rid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 6. " RVALID_UNCERR ,'dma axi e2e rvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 5. " HRESP_UNCERR ,'dma ahb e2e uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 4. " HRDATA_UNCERR ,'dma ahb e2e uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PADDR_UNCERR ,'dma apb e2e paddr uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 2. " PCTL1_UNCERR ,'dma apb e2e pctl1 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 1. " PCTL0_UNCERR ,'dma apb e2e pctl0 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCERR ,'dma apb e2e pwdata uncorrectable err interrupt'" "0,1"
|
|
group ad:0xF05407E8++0x03
|
|
line.long 0x00 "DMA_INTSTAT,DMA_INTSTAT"
|
|
bitfld.long 0x00 31. " DMA_INPUT_SIG_ERR ,'dma input lock step en or selftest mode signal err'" "0,1"
|
|
bitfld.long 0x00 30. " CORE1_MONITOR_ERR ,'dma lock step core mask logic error'" "0,1"
|
|
bitfld.long 0x00 29. " LOCK_STEP_ERR ,'dma lock step compare error'" "0,1"
|
|
bitfld.long 0x00 28. " AXI_RD_MONITOR_FATAL ,'axi data correction monitor fatal err'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HRDATA_FATAL ,'ahb data correction monitor fatal err'" "0,1"
|
|
bitfld.long 0x00 26. " PWDATA_FATAL ,'dma apb wdata correction monitor fatal err interrupt'" "0,1"
|
|
bitfld.long 0x00 25. " HRDATA_CORERR ,'dma ahb e2e correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 24. " RDATA_CORERR ,'dma AXI e2e rdata correctable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "PWDATA_CORERR ,'dma apb e2e pwdata correctable err interrupt'" "0,1"
|
|
bitfld.long 0x00 22. " FIFO_COR_ERR ,'FIFO CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 21. " CH_COR_ERR ,'CH CORRECTABLE interrupt'" "0,1"
|
|
bitfld.long 0x00 20. " FIFO_UNC_ERR ,'FIFO UN CORRECT interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CH_UNC_ERR ,'CH UN CORRECT interrupt'" "0,1"
|
|
bitfld.long 0x00 18. " LBC_COR_ERR ,'LOCAL BUFFER Correct Error interrupt'" "0,1"
|
|
bitfld.long 0x00 17. " LBC_UNC_ERR ,'LOCAL BUFFER UNCorrect Error interrupt'" "0,1"
|
|
bitfld.long 0x00 16. " WREADY_UNCERR ,'dma axi e2e wready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BVALID_UNCERR ,'dma axi e2e bvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 14. " BID_UNCERR ,'dma axi e2e bid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 13. " BCTL_UNCERR ,'dma axi e2e Bctrl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 12. " AWREADY_UNCERR ,'dma axi e2e awready uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "ARREADY_UNCERR ,'dma axi e2e arready uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 10. " RCTL_UNCERR ,'dma axi e2e rctl uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 9. " RDATA_UNCERR ,'dma axi e2e rdata uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 8. " REOBI_UNCERR ,'dma axi e2e reobi uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RID_UNCERR ,'dma axi e2e rid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 6. " RVALID_UNCERR ,'dma axi e2e rvalid uncorrectable error interrupt'" "0,1"
|
|
bitfld.long 0x00 5. " HRESP_UNCERR ,'dma ahb e2e uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 4. " HRDATA_UNCERR ,'dma ahb e2e uncorrectable error interrupt'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PADDR_UNCERR ,'dma apb e2e paddr uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 2. " PCTL1_UNCERR ,'dma apb e2e pctl1 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 1. " PCTL0_UNCERR ,'dma apb e2e pctl0 uncorrectable err interrupt'" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNCERR ,'dma apb e2e pwdata uncorrectable err interrupt'" "0,1"
|
|
group ad:0xF05407F0++0x03
|
|
line.long 0x00 "DMA_CONT_INTEN,DMA_CONT_INTEN"
|
|
bitfld.long 0x00 4. " BUTID_ERR ,'AXI B UTID error'" "0,1"
|
|
bitfld.long 0x00 3. " RUTID_ERR ,'AXI R UTID error'" "0,1"
|
|
bitfld.long 0x00 2. " AHB_ERR ,'dma ahb response error'" "0,1"
|
|
bitfld.long 0x00 1. " AXI_WR_ERR ,'DMA axi write response error'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "AXI_RD_ERR ,'DMA axi read response error'" "0,1"
|
|
group ad:0xF05407F4++0x03
|
|
line.long 0x00 "DMA_CONT_INTCLR,DMA_CONT_INTCLR"
|
|
bitfld.long 0x00 4. " BUTID_ERR ,'AXI B UTID error'" "0,1"
|
|
bitfld.long 0x00 3. " RUTID_ERR ,'AXI R UTID error'" "0,1"
|
|
bitfld.long 0x00 2. " AHB_ERR ,'dma ahb response error'" "0,1"
|
|
bitfld.long 0x00 1. " AXI_WR_ERR ,'DMA axi write response error'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "AXI_RD_ERR ,'DMA axi read response error'" "0,1"
|
|
group ad:0xF05407F8++0x03
|
|
line.long 0x00 "DMA_CONT_INTSTAT,DMA_CONT_INTSTAT"
|
|
bitfld.long 0x00 4. " BUTID_ERR ,'AXI B UTID error'" "0,1"
|
|
bitfld.long 0x00 3. " RUTID_ERR ,'AXI R UTID error'" "0,1"
|
|
bitfld.long 0x00 2. " AHB_ERR ,'dma ahb response error'" "0,1"
|
|
bitfld.long 0x00 1. " AXI_WR_ERR ,'DMA axi write response error'" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "AXI_RD_ERR ,'DMA axi read response error'" "0,1"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "DCDC"
|
|
width 27.
|
|
group ad:0xF0600000++0x03
|
|
line.long 0x00 "DC_CTRL,dc control reg"
|
|
bitfld.long 0x00 31. " SW_RST ,Software reset. High active. When SW set software reset, must make sure all clock are enabled." "0,1"
|
|
bitfld.long 0x00 3. " UNDERRUN_CLR_MODE ,0: not clear GP/SP 1:clear GP/SP when new TCON start coming" "0,1"
|
|
bitfld.long 0x00 2. " MLC_DISCARD_MODE ,0:MLC DIscard previous frame when new TCON start coming 1:not receiving old frame again when new TCON start coming" "0,1"
|
|
bitfld.long 0x00 1. " MS_MODE ,0: Master mode, 1: Slave mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SF_MODE ,0: Normal mode 1: DC will exit Sf mode if the 'gl_sf_failure' is cleared. When DC enter to normal mode, this bit will be cleared by HW." "0,1"
|
|
group ad:0xF0600004++0x03
|
|
line.long 0x00 "DC_FLC_CTRL,dc flc ctrl reg."
|
|
bitfld.long 0x00 3. " CRC32_TRIG ,Crc32 trigger." "0,1"
|
|
bitfld.long 0x00 2. " TCON_TRIG ,Tcon kick register load." "0,1"
|
|
bitfld.long 0x00 1. " DI_TRIG ," "0,1"
|
|
bitfld.long 0x00 0. " FLC_TRIG ,FLC trigger, software set, HW clear. set this bit will trigger the FLC to load updated regster to shadow register." "0,1"
|
|
group ad:0xF0600008++0x03
|
|
line.long 0x00 "DC_FLC_UPDATE,dc flc force update"
|
|
bitfld.long 0x00 0. " FORCE ,FLC force update the all register to shadow register. software set, HW clear. set this bit will trigger the FLC to load updated regster to shadow register." "0,1"
|
|
group ad:0xF0600010++0x03
|
|
line.long 0x00 "SDMA_CTRL,SDMA request control"
|
|
bitfld.long 0x00 4. " GAMMA_EN ,Enable SDMA load gamma table. Only can be used in initial stage ." "0,1"
|
|
bitfld.long 0x00 0. " SDMA_EN ,Enable DMA to config DC register. The CLUT table and gamma table should not be config by SDMA." "0,1"
|
|
group ad:0xF0600020++0x03
|
|
line.long 0x00 "DC_INT_MASK,dc interrupt mask"
|
|
bitfld.long 0x00 29. " CSI_TCON_VSYNC_DLY_DONE ,csi_tcon_vsync_dly_done interrupt mask." "0,1"
|
|
bitfld.long 0x00 28. " CSI_TIMING_DECT_DONE ,csi_timing_dect_done interrupt mask." "0,1"
|
|
hexmask.long.tbyte 0x00 8.--27. 1. " TCON_LAYER_KICK ,TCON_LAYER_KICK interrupt mask."
|
|
bitfld.long 0x00 7. " SDMA_DONE ,SDMA load CLUT/GAMMA table done." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DC_UNDERRUN ,DC underrun interrupt mask" "0,1"
|
|
bitfld.long 0x00 5. " TCON_UNDERRUN ,Tcon underrun interrupt mask" "0,1"
|
|
bitfld.long 0x00 4. " TCON_EOF ,Tcon frame end interrupt mask." "0,1"
|
|
bitfld.long 0x00 3. " TCON_SOF ,Tcon frame start interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "MLC ,Mlc interrupt mask" "0,1"
|
|
bitfld.long 0x00 1. " RLE ,RLE interrupt mask" "0,1"
|
|
bitfld.long 0x00 0. " RDMA ,Rdma interrupt mask." "0,1"
|
|
group ad:0xF0600024++0x03
|
|
line.long 0x00 "DC_INT_STATUS,dc interrupt status"
|
|
bitfld.long 0x00 29. " CSI_TCON_VSYNC_DLY_DONE ,csi_tcon_vsync_dly_done interrupt status." "0,1"
|
|
bitfld.long 0x00 28. " CSI_TIMING_DECT_DONE ,csi_timing_dect_done interrupt status." "0,1"
|
|
bitfld.long 0x00 27. " TCON_LAYER_KICK_19 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 26. " TCON_LAYER_KICK_18 ,Tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "TCON_LAYER_KICK_17 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 24. " TCON_LAYER_KICK_16 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 23. " TCON_LAYER_KICK_15 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 22. " TCON_LAYER_KICK_14 ,Tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "TCON_LAYER_KICK_13 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 20. " TCON_LAYER_KICK_12 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 19. " TCON_LAYER_KICK_11 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 18. " TCON_LAYER_KICK_10 ,Tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "TCON_LAYER_KICK_9 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 16. " TCON_LAYER_KICK_8 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 15. " TCON_LAYER_KICK_7 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 14. " TCON_LAYER_KICK_6 ,Tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TCON_LAYER_KICK_5 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 12. " TCON_LAYER_KICK_4 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 11. " TCON_LAYER_KICK_3 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 10. " TCON_LAYER_KICK_2 ,Tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TCON_LAYER_KICK_1 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 8. " TCON_LAYER_KICK_0 ,Tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 7. " SDMA_DONE ,SDMA load CLUT/GAMMA table done." "0,1"
|
|
bitfld.long 0x00 6. " DC_UNDERRUN ,Tcon underrun interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "TCON_UNDERRUN ,Tcon underrun interrupt status." "0,1"
|
|
bitfld.long 0x00 4. " TCON_EOF ,Tcon frame end interrupt status." "0,1"
|
|
bitfld.long 0x00 3. " TCON_SOF ,Tcon frame start interrupt status." "0,1"
|
|
bitfld.long 0x00 2. " MLC ,Mlc interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RLE ,RLE interrupt status." "0,1"
|
|
bitfld.long 0x00 0. " RDMA ,Rdma interrupt status." "0,1"
|
|
group ad:0xF0600100++0x03
|
|
line.long 0x00 "DC_SF_FLC_CTRL,dc flc ctrl reg."
|
|
bitfld.long 0x00 3. " CRC32_TRIG ,Crc32 trig." "0,1"
|
|
bitfld.long 0x00 2. " TCON_TRIG ,Tcon kick register load." "0,1"
|
|
bitfld.long 0x00 1. " DI_TRIG ,DI register trigger" "0,1"
|
|
bitfld.long 0x00 0. " FLC_TRIG ,FLC trigger, software set, HW clear. set this bit will trigger the FLC to load updated regster to shadow register." "0,1"
|
|
group ad:0xF0600120++0x03
|
|
line.long 0x00 "DC_SF_INT_MASK,dc interrupt mask"
|
|
bitfld.long 0x00 29. " CSI_TCON_VSYNC_DLY_DONE ,csi_tcon_vsync_dly_done interrupt mask." "0,1"
|
|
bitfld.long 0x00 28. " CSI_TIMING_DECT_DONE ,csi_timing_dect_done interrupt mask." "0,1"
|
|
hexmask.long.tbyte 0x00 8.--27. 1. " TCON_LAYER_KICK ,tcon layer kick interrupt mask."
|
|
bitfld.long 0x00 7. " SDMA_DONE ,SDMA load CLUT/GAMMA table done." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "DC_UNDERRUN ,DC underrun interrupt mask" "0,1"
|
|
bitfld.long 0x00 5. " TCON_UNDERRUN ,Tcon underrun interrupt mask" "0,1"
|
|
bitfld.long 0x00 4. " TCON_EOF ,tcon end frame interrupt mask." "0,1"
|
|
bitfld.long 0x00 3. " TCON_SOF ,Tcon start frame interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "MLC ,Mlc interrupt mask" "0,1"
|
|
bitfld.long 0x00 1. " RLE ,RLE interrupt mask" "0,1"
|
|
bitfld.long 0x00 0. " RDMA ,Rdma interrupt mask." "0,1"
|
|
group ad:0xF0600124++0x03
|
|
line.long 0x00 "DC_SF_INT_STATUS,dc interrupt status"
|
|
bitfld.long 0x00 29. " CSI_TCON_VSYNC_DLY_DONE ,csi_tcon_vsync_dly_done interrupt status." "0,1"
|
|
bitfld.long 0x00 28. " CSI_TIMING_DECT_DONE ,csi_timing_dect_done interrupt status." "0,1"
|
|
bitfld.long 0x00 27. " TCON_LAYER_KICK_19 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 26. " TCON_LAYER_KICK_18 ,tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "TCON_LAYER_KICK_17 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 24. " TCON_LAYER_KICK_16 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 23. " TCON_LAYER_KICK_15 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 22. " TCON_LAYER_KICK_14 ,tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "TCON_LAYER_KICK_13 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 20. " TCON_LAYER_KICK_12 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 19. " TCON_LAYER_KICK_11 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 18. " TCON_LAYER_KICK_10 ,tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "TCON_LAYER_KICK_9 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 16. " TCON_LAYER_KICK_8 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 15. " TCON_LAYER_KICK_7 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 14. " TCON_LAYER_KICK_6 ,tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "TCON_LAYER_KICK_5 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 12. " TCON_LAYER_KICK_4 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 11. " TCON_LAYER_KICK_3 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 10. " TCON_LAYER_KICK_2 ,tcon layer kick interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TCON_LAYER_KICK_1 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 8. " TCON_LAYER_KICK_0 ,tcon layer kick interrupt status." "0,1"
|
|
bitfld.long 0x00 7. " SDMA_DONE ,SDMA load CLUT/GAMMA table done." "0,1"
|
|
bitfld.long 0x00 6. " DC_UNDERRUN ,Tcon underrun interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "TCON_UNDERRUN ,Tcon underrun interrupt status." "0,1"
|
|
bitfld.long 0x00 4. " TCON_EOF ,Tcon end frame status." "0,1"
|
|
bitfld.long 0x00 3. " TCON_SOF ,Tcon start frame interrupt status." "0,1"
|
|
bitfld.long 0x00 2. " MLC ,Mlc interrupt status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RLE ,RLE interrupt status." "0,1"
|
|
bitfld.long 0x00 0. " RDMA ,Rdma interrupt status." "0,1"
|
|
group ad:0xF0601000++0x03
|
|
line.long 0x00 "RDMA_DFIFO_WML_0,Data FIFO threshold for leveling."
|
|
hexmask.long.word 0x00 0.--15. 1. " WML ,DFIFO WML"
|
|
group ad:0xF0601004++0x03
|
|
line.long 0x00 "RDMA_DFIFO_DEPTH_0,Data FIFO depth for 16 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Data FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 16"
|
|
group ad:0xF0601008++0x03
|
|
line.long 0x00 "RDMA_CFIFO_DEPTH_0,Command FIFO depth for 4 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Command FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 14"
|
|
group ad:0xF060100C++0x03
|
|
line.long 0x00 "RDMA_CH_PRIO_0,RDMA channel priority setting."
|
|
hexmask.long.byte 0x00 16.--21. 1. " SCHE ,schedule mode enable."
|
|
hexmask.long.byte 0x00 8.--13. 1. " P1 ,P1"
|
|
hexmask.long.byte 0x00 0.--5. 1. " P0 ,p0"
|
|
group ad:0xF0601010++0x03
|
|
line.long 0x00 "RDMA_BURST_0,RDma burst length and burst mode config."
|
|
bitfld.long 0x00 3. " MODE ,burst mode, 1'b0: normal burst mode 1'b1: Incr Aligned burst mode" "0,1"
|
|
bitfld.long 0x00 0.--2. " LEN ,Burst length. 3'b000: Burst size =1; 3'b001: Burst size =2; 3'b010: Burst size =4; 3'b011: Burst size =8; 3'b100: Burst size =16; 3'b101: Burst size =32; 3'b110: Burst size =64; 3'b1111: Burst size =64.." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601014++0x03
|
|
line.long 0x00 "RDMA_AXI_USER_0,RDMA AXI user bit."
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " USER ,User"
|
|
group ad:0xF0601018++0x03
|
|
line.long 0x00 "RDMA_AXI_CTRL_0,RDMA AXI cache and prot setting."
|
|
bitfld.long 0x00 4.--5. " PROT ,prot" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " CACHE ,cache" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF060101C++0x03
|
|
line.long 0x00 "RDMA_PRES_WML_0,Data FIFO threshold for DMA pressure."
|
|
hexmask.long.word 0x00 16.--25. 1. " REQ_INTERVAL ,RDMA Command request interval."
|
|
bitfld.long 0x00 4.--6. " DOWN ,Down threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " UP ,up threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601020++0x03
|
|
line.long 0x00 "RDMA_DFIFO_WML_1,Data FIFO threshold for leveling."
|
|
hexmask.long.word 0x00 0.--15. 1. " WML ,DFIFO WML"
|
|
group ad:0xF0601024++0x03
|
|
line.long 0x00 "RDMA_DFIFO_DEPTH_1,Data FIFO depth for 16 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Data FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 16"
|
|
group ad:0xF0601028++0x03
|
|
line.long 0x00 "RDMA_CFIFO_DEPTH_1,Command FIFO depth for 4 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Command FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 14"
|
|
group ad:0xF060102C++0x03
|
|
line.long 0x00 "RDMA_CH_PRIO_1,RDMA channel priority setting."
|
|
hexmask.long.byte 0x00 16.--21. 1. " SCHE ,schedule mode enable."
|
|
hexmask.long.byte 0x00 8.--13. 1. " P1 ,P1"
|
|
hexmask.long.byte 0x00 0.--5. 1. " P0 ,p0"
|
|
group ad:0xF0601030++0x03
|
|
line.long 0x00 "RDMA_BURST_1,RDma burst length and burst mode config."
|
|
bitfld.long 0x00 3. " MODE ,burst mode, 1'b0: normal burst mode 1'b1: Incr Aligned burst mode" "0,1"
|
|
bitfld.long 0x00 0.--2. " LEN ,Burst length. 3'b000: Burst size =1; 3'b001: Burst size =2; 3'b010: Burst size =4; 3'b011: Burst size =8; 3'b100: Burst size =16; 3'b101: Burst size =32; 3'b110: Burst size =64; 3'b1111: Burst size =64.." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601034++0x03
|
|
line.long 0x00 "RDMA_AXI_USER_1,RDMA AXI user bit."
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " USER ,User"
|
|
group ad:0xF0601038++0x03
|
|
line.long 0x00 "RDMA_AXI_CTRL_1,RDMA AXI cache and prot setting."
|
|
bitfld.long 0x00 4.--5. " PROT ,prot" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " CACHE ,cache" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF060103C++0x03
|
|
line.long 0x00 "RDMA_PRES_WML_1,Data FIFO threshold for DMA pressure."
|
|
hexmask.long.word 0x00 16.--25. 1. " REQ_INTERVAL ,RDMA Command request interval."
|
|
bitfld.long 0x00 4.--6. " DOWN ,Down threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " UP ,up threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601040++0x03
|
|
line.long 0x00 "RDMA_DFIFO_WML_2,Data FIFO threshold for leveling."
|
|
hexmask.long.word 0x00 0.--15. 1. " WML ,DFIFO WML"
|
|
group ad:0xF0601044++0x03
|
|
line.long 0x00 "RDMA_DFIFO_DEPTH_2,Data FIFO depth for 16 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Data FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 16"
|
|
group ad:0xF0601048++0x03
|
|
line.long 0x00 "RDMA_CFIFO_DEPTH_2,Command FIFO depth for 4 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Command FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 14"
|
|
group ad:0xF060104C++0x03
|
|
line.long 0x00 "RDMA_CH_PRIO_2,RDMA channel priority setting."
|
|
hexmask.long.byte 0x00 16.--21. 1. " SCHE ,schedule mode enable."
|
|
hexmask.long.byte 0x00 8.--13. 1. " P1 ,P1"
|
|
hexmask.long.byte 0x00 0.--5. 1. " P0 ,p0"
|
|
group ad:0xF0601050++0x03
|
|
line.long 0x00 "RDMA_BURST_2,RDma burst length and burst mode config."
|
|
bitfld.long 0x00 3. " MODE ,burst mode, 1'b0: normal burst mode 1'b1: Incr Aligned burst mode" "0,1"
|
|
bitfld.long 0x00 0.--2. " LEN ,Burst length. 3'b000: Burst size =1; 3'b001: Burst size =2; 3'b010: Burst size =4; 3'b011: Burst size =8; 3'b100: Burst size =16; 3'b101: Burst size =32; 3'b110: Burst size =64; 3'b1111: Burst size =64.." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601054++0x03
|
|
line.long 0x00 "RDMA_AXI_USER_2,RDMA AXI user bit."
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " USER ,User"
|
|
group ad:0xF0601058++0x03
|
|
line.long 0x00 "RDMA_AXI_CTRL_2,RDMA AXI cache and prot setting."
|
|
bitfld.long 0x00 4.--5. " PROT ,prot" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " CACHE ,cache" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF060105C++0x03
|
|
line.long 0x00 "RDMA_PRES_WML_2,Data FIFO threshold for DMA pressure."
|
|
hexmask.long.word 0x00 16.--25. 1. " REQ_INTERVAL ,RDMA Command request interval."
|
|
bitfld.long 0x00 4.--6. " DOWN ,Down threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " UP ,up threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601060++0x03
|
|
line.long 0x00 "RDMA_DFIFO_WML_3,Data FIFO threshold for leveling."
|
|
hexmask.long.word 0x00 0.--15. 1. " WML ,DFIFO WML"
|
|
group ad:0xF0601064++0x03
|
|
line.long 0x00 "RDMA_DFIFO_DEPTH_3,Data FIFO depth for 16 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Data FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 16"
|
|
group ad:0xF0601068++0x03
|
|
line.long 0x00 "RDMA_CFIFO_DEPTH_3,Command FIFO depth for 4 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Command FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 14"
|
|
group ad:0xF060106C++0x03
|
|
line.long 0x00 "RDMA_CH_PRIO_3,RDMA channel priority setting."
|
|
hexmask.long.byte 0x00 16.--21. 1. " SCHE ,schedule mode enable."
|
|
hexmask.long.byte 0x00 8.--13. 1. " P1 ,P1"
|
|
hexmask.long.byte 0x00 0.--5. 1. " P0 ,p0"
|
|
group ad:0xF0601070++0x03
|
|
line.long 0x00 "RDMA_BURST_3,RDma burst length and burst mode config."
|
|
bitfld.long 0x00 3. " MODE ,burst mode, 1'b0: normal burst mode 1'b1: Incr Aligned burst mode" "0,1"
|
|
bitfld.long 0x00 0.--2. " LEN ,Burst length. 3'b000: Burst size =1; 3'b001: Burst size =2; 3'b010: Burst size =4; 3'b011: Burst size =8; 3'b100: Burst size =16; 3'b101: Burst size =32; 3'b110: Burst size =64; 3'b1111: Burst size =64.." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601074++0x03
|
|
line.long 0x00 "RDMA_AXI_USER_3,RDMA AXI user bit."
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " USER ,User"
|
|
group ad:0xF0601078++0x03
|
|
line.long 0x00 "RDMA_AXI_CTRL_3,RDMA AXI cache and prot setting."
|
|
bitfld.long 0x00 4.--5. " PROT ,prot" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " CACHE ,cache" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF060107C++0x03
|
|
line.long 0x00 "RDMA_PRES_WML_3,Data FIFO threshold for DMA pressure."
|
|
hexmask.long.word 0x00 16.--25. 1. " REQ_INTERVAL ,RDMA Command request interval."
|
|
bitfld.long 0x00 4.--6. " DOWN ,Down threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " UP ,up threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601100++0x03
|
|
line.long 0x00 "RDMA_CTRL,RDMA control."
|
|
bitfld.long 0x00 1. " CFG_LOAD ,rdma config load." "0,1"
|
|
bitfld.long 0x00 0. " ARB_SEL ,arbitor mode select." "0,1"
|
|
group ad:0xF0601200++0x03
|
|
line.long 0x00 "RDMA_DFIFO_FULL,rdma_dfifo full"
|
|
bitfld.long 0x00 6. " CH_6 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,dfifo full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,dfifo full." "0,1"
|
|
group ad:0xF0601204++0x03
|
|
line.long 0x00 "RDMA_DFIFO_EMPTY,rdma_dfifo empy"
|
|
bitfld.long 0x00 6. " CH_6 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,dfifo empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,dfifo empty." "0,1"
|
|
group ad:0xF0601208++0x03
|
|
line.long 0x00 "RDMA_CFIFO_FULL,rdma_ cfifo full"
|
|
bitfld.long 0x00 6. " CH_6 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,cfifo full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,cfifo full." "0,1"
|
|
group ad:0xF060120C++0x03
|
|
line.long 0x00 "RDMA_CFIFO_EMPTY,rdma_ fifo empy"
|
|
bitfld.long 0x00 6. " CH_6 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,cfifo empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,cfifo empty." "0,1"
|
|
group ad:0xF0601210++0x03
|
|
line.long 0x00 "RDMA_CH_IDLE,RDMA channel status."
|
|
bitfld.long 0x00 6. " CH_6 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,1: IDLE, 0: Busy." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,1: IDLE, 0: Busy." "0,1"
|
|
group ad:0xF0601220++0x03
|
|
line.long 0x00 "RDMA_INT_MASK,RDMA interrupt maks."
|
|
bitfld.long 0x00 6. " ERR_CH_6 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 5. " ERR_CH_5 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 4. " ERR_CH_4 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 3. " ERR_CH_3 ,Rdam Channle error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "ERR_CH_2 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 1. " ERR_CH_1 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 0. " ERR_CH_0 ,Rdam Channle error." "0,1"
|
|
group ad:0xF0601224++0x03
|
|
line.long 0x00 "RDMA_INT_STATUS,RDMA interrupt status"
|
|
bitfld.long 0x00 6. " ERR_CH_6 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 5. " ERR_CH_5 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 4. " ERR_CH_4 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 3. " ERR_CH_3 ,Rdam Channle error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "ERR_CH_2 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 1. " ERR_CH_1 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 0. " ERR_CH_0 ,Rdam Channle error." "0,1"
|
|
group ad:0xF0601240++0x03
|
|
line.long 0x00 "RDMA_DEBUG_CTRL,rdma_debug_ctrl"
|
|
bitfld.long 0x00 0.--3. " DEBUG_SEL ,debg_sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0601244++0x03
|
|
line.long 0x00 "RDMA_DEBUG_STA,rdma_debug_sta"
|
|
hexmask.long.word 0x00 16.--31. 1. " CFIFO_DEP ,cfifo_dep"
|
|
hexmask.long.word 0x00 0.--15. 1. " DFIFO_DEP ,dfifo_dep"
|
|
group ad:0xF0601400++0x03
|
|
line.long 0x00 "S_RDMA_DFIFO_WML_0,Data FIFO threshold for leveling."
|
|
hexmask.long.word 0x00 0.--15. 1. " WML ,DFIFO WML"
|
|
group ad:0xF0601404++0x03
|
|
line.long 0x00 "S_RDMA_DFIFO_DEPTH_0,Data FIFO depth for 16 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Data FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 16"
|
|
group ad:0xF0601408++0x03
|
|
line.long 0x00 "S_RDMA_CFIFO_DEPTH_0,Command FIFO depth for 4 words."
|
|
hexmask.long.word 0x00 0.--15. 1. " DEPTH ,Data FIFO Depth for each DMA channel. The real FIFO depth = DEPTH * 16"
|
|
group ad:0xF060140C++0x03
|
|
line.long 0x00 "S_RDMA_CH_PRIO_0,RDMA channel priority setting."
|
|
hexmask.long.byte 0x00 16.--21. 1. " SCHE ,schedule mode enable."
|
|
hexmask.long.byte 0x00 8.--13. 1. " P1 ,P1"
|
|
hexmask.long.byte 0x00 0.--5. 1. " P0 ,p0"
|
|
group ad:0xF0601410++0x03
|
|
line.long 0x00 "S_RDMA_BURST_0,RDma burst length and burst mode config."
|
|
bitfld.long 0x00 3. " MODE ,burst mode, 1'b0: normal burst mode 1'b1: Incr Aligned burst mode" "0,1"
|
|
bitfld.long 0x00 0.--2. " LEN ,Burst length. 3'b000: Burst size =1; 3'b001: Burst size =2; 3'b010: Burst size =4; 3'b011: Burst size =8; 3'b100: Burst size =16; 3'b101: Burst size =32; 3'b110: Burst size =64; 3'b1111: Burst size =64.." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601414++0x03
|
|
line.long 0x00 "S_RDMA_AXI_USER_0,RDMA AXI user bit."
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " USER ,User"
|
|
group ad:0xF0601418++0x03
|
|
line.long 0x00 "S_RDMA_AXI_CTRL_0,RDMA AXI cache and prot setting."
|
|
bitfld.long 0x00 4.--5. " PROT ,prot" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " CACHE ,cache" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF060141C++0x03
|
|
line.long 0x00 "S_RDMA_PRES_WML_0,Data FIFO threshold for DMA pressure."
|
|
hexmask.long.word 0x00 16.--25. 1. " REQ_INTERVAL ,RDMA Command request interval."
|
|
bitfld.long 0x00 4.--6. " DOWN ,Down threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " UP ,up threshold. 0: 0 1: 1/8 2: 2/8 3: 3/8 4: 4/8 5: 5/8 6: 6/8 7: 7/8" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0601500++0x03
|
|
line.long 0x00 "S_RDMA_CTRL,RDMA control."
|
|
bitfld.long 0x00 1. " CFG_LOAD ,rdma config load." "0,1"
|
|
bitfld.long 0x00 0. " ARB_SEL ,arbitor mode select." "0,1"
|
|
group ad:0xF0601600++0x03
|
|
line.long 0x00 "S_RDMA_DFIFO_FULL,rdma dfifo full"
|
|
bitfld.long 0x00 6. " CH_6 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,dfifo full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,dfifo full." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,dfifo full." "0,1"
|
|
group ad:0xF0601604++0x03
|
|
line.long 0x00 "S_RDMA_DFIFO_EMPTY,rdma dfifo empy"
|
|
bitfld.long 0x00 6. " CH_6 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,dfifo empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,dfifo empty." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,dfifo empty." "0,1"
|
|
group ad:0xF0601608++0x03
|
|
line.long 0x00 "S_RDMA_CFIFO_FULL,rdma cfifo full"
|
|
bitfld.long 0x00 6. " CH_6 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,cfifo full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,cfifo full." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,cfifo full." "0,1"
|
|
group ad:0xF060160C++0x03
|
|
line.long 0x00 "S_RDMA_CFIFO_EMPTY,rdma_fifo empy"
|
|
bitfld.long 0x00 6. " CH_6 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,cfifo empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,cfifo empty." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,cfifo empty." "0,1"
|
|
group ad:0xF0601610++0x03
|
|
line.long 0x00 "S_RDMA_CH_IDLE,rdma channel status."
|
|
bitfld.long 0x00 6. " CH_6 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 5. " CH_5 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 4. " CH_4 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 3. " CH_3 ,1: IDLE, 0: Busy." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CH_2 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 1. " CH_1 ,1: IDLE, 0: Busy." "0,1"
|
|
bitfld.long 0x00 0. " CH_0 ,1: IDLE, 0: Busy." "0,1"
|
|
group ad:0xF0601620++0x03
|
|
line.long 0x00 "S_RDMA_INT_MASK,rdma interrupt maks."
|
|
bitfld.long 0x00 6. " ERR_CH_6 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 5. " ERR_CH_5 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 4. " ERR_CH_4 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 3. " ERR_CH_3 ,Rdam Channle error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "ERR_CH_2 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 1. " ERR_CH_1 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 0. " ERR_CH_0 ,Rdam Channle error." "0,1"
|
|
group ad:0xF0601624++0x03
|
|
line.long 0x00 "S_RDMA_INT_STATUS,rdma interrupt status"
|
|
bitfld.long 0x00 6. " ERR_CH_6 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 5. " ERR_CH_5 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 4. " ERR_CH_4 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 3. " ERR_CH_3 ,Rdam Channle error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "ERR_CH_2 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 1. " ERR_CH_1 ,Rdam Channle error." "0,1"
|
|
bitfld.long 0x00 0. " ERR_CH_0 ,Rdam Channle error." "0,1"
|
|
group ad:0xF0601640++0x03
|
|
line.long 0x00 "S_RDMA_DEBUG_CTRL,rdma_debug_ctrl"
|
|
bitfld.long 0x00 0.--3. " DEBUG_SEL ,debg_sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0601644++0x03
|
|
line.long 0x00 "S_RDMA_DEBUG_STA,rdma_debug_sta"
|
|
hexmask.long.word 0x00 16.--31. 1. " CFIFO_DEP ,cfifo_dep"
|
|
hexmask.long.word 0x00 0.--15. 1. " DFIFO_DEP ,dfifo_dep"
|
|
group ad:0xF0602000++0x03
|
|
line.long 0x00 "DC_GP_PIX_COMP_0,Pixle comp bpp setting."
|
|
bitfld.long 0x00 24.--27. " BPV ,bit per each V component, in bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " BPU ,bit per each U component, in bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--12. " BPY ,BPY[4:0]: bit per each Y component When BPY[4] = 0, bit per each Y component, in bit count When BPY[4] = 1, Byte per pixel, in Byte count -1 4'b0000: 1Byte/pixel 4'b0001: 2Byte/pixel 4'b0010: 3Byte/pixel 4'b0011:4Byte/pixel (.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " BPA ,Bpa: bit per each A component." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0602004++0x03
|
|
line.long 0x00 "DC_GP_FRM_CTRL_0,Frame control register."
|
|
bitfld.long 0x00 16.--18. " ENDIAN_CTRL ,Bit0: byte swap, bit1, hword swap, bit2 word swap" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. " COMP_SWAP ,Pixel component swap. When bit[3] = 1'b0, A channel is in MSB, When bit[3] =1'b1, A channel is in LSB, that means the B channel will be as A channel. 4'b0000:A/RGB 4'b0001:A/RBG 4'b0010:A/GBR 4'b0011:A/GRB 4'b0100:A/BGR .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--10. " ROT ,bit2: HFLIP, Bit1:Vflip Bit0:Rotation." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " RGB_YUV ,1'b0, RGB mode, 1'b1, YUV mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "UV_SWAP ,u/v channel swap" "0,1"
|
|
bitfld.long 0x00 4.--5. " UV_MODE ,UV_MODE[1:0], 2-bits encoded YUV sub-sample mode 2'b00: YUV444/RGB 2'b01: YUV422 2'b10: YUV440, this format happens when YUV422 image is rotated by 90 or 270 degree 2'b11: YUV420" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MODE ,2'b00: linear mode 2'b01: RLE compression mode. 2'b10: GPU tile mode 2'b11: reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FMT ,2-bits encoded frame buffer storage format 2'b00: Interleaved (RGB/YUV when BPA=0, ARGB/AYUV when BPA!=0) 2'b01: Monotonic 2'b10: Semi-Planar 2'b11: Planar" "0,1,2,3"
|
|
group ad:0xF0602008++0x03
|
|
line.long 0x00 "DC_GP_FRM_SIZE_0,Frame size."
|
|
hexmask.long.word 0x00 16.--31. 1. " HEIGHT ,Frame height, set value =real size -1;"
|
|
hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Frame width, set valule = real size -1;"
|
|
group ad:0xF060200C++0x03
|
|
line.long 0x00 "DC_GP_Y_BADDR_L_0,RGB or Y base address"
|
|
hexmask.long 0x00 0.--31. 1. " Y ,Y base address Low 32 bit."
|
|
group ad:0xF0602010++0x03
|
|
line.long 0x00 "DC_GP_Y_BADDR_H_0,RGB or Y base address"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Y ,Y base address high 8 bit."
|
|
group ad:0xF0602014++0x03
|
|
line.long 0x00 "DC_GP_U_BADDR_L_0,U channel base address."
|
|
hexmask.long 0x00 0.--31. 1. " U ,U base address Low 32 bit."
|
|
group ad:0xF0602018++0x03
|
|
line.long 0x00 "DC_GP_U_BADDR_H_0,U base address high 8 bit."
|
|
hexmask.long.byte 0x00 0.--7. 1. " U ,U base address high 8 bit."
|
|
group ad:0xF060201C++0x03
|
|
line.long 0x00 "DC_GP_V_BADDR_L_0,V channel base address."
|
|
hexmask.long 0x00 0.--31. 1. " V ,V base address Low 32 bit."
|
|
group ad:0xF0602020++0x03
|
|
line.long 0x00 "DC_GP_V_BADDR_H_0,V channel base address."
|
|
hexmask.long.byte 0x00 0.--7. 1. " V ,V base address high 8 bit."
|
|
group ad:0xF060202C++0x03
|
|
line.long 0x00 "DC_GP_Y_STRIDE_0,Stride for RGB or Y , byte unit."
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " Y ,Stride for RGB or Y , byte unit, real size -1; In GPU tile mode, it must align to GPU H-size"
|
|
group ad:0xF0602030++0x03
|
|
line.long 0x00 "DC_GP_U_STRIDE_0,Stride for U, byte unit."
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " U ,Stride for U , byte unit, real size -1;"
|
|
group ad:0xF0602034++0x03
|
|
line.long 0x00 "DC_GP_V_STRIDE_0,Stride for V , byte unit."
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " V ,Stride for V , byte unit, real size -1;"
|
|
group ad:0xF0602040++0x03
|
|
line.long 0x00 "DC_GP_FRM_OFFSET_0,dc_gp_frm_offset"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Frame UL y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Frame UL x coorDInate."
|
|
group ad:0xF0602044++0x03
|
|
line.long 0x00 "DC_GP_YUVUP_CTRL_0,YUV UP control register."
|
|
bitfld.long 0x00 31. " EN ,{EN,FITER_MODE}= 00, h average mode,v average mode 01, h repeat mode, v repeat mode 10, h repeat mode, v average mode 11, h average mode, v repeat mode" "0,1"
|
|
bitfld.long 0x00 6.--7. " VOFSET ,00: 0(default) 01: +0.5 10: 0 11: -0.5" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " HOFSET ,00: 0(default) 01: +0.5 10: 0 11: -0.5" "0,1,2,3"
|
|
bitfld.long 0x00 3. " FILTER_MODE ,1: repeat mode , 0 : average mode." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "UPV_BYPASS ,Force bypass v-upscale." "0,1"
|
|
bitfld.long 0x00 1. " UPH_BYPASS ,Force bypass h-upscale." "0,1"
|
|
bitfld.long 0x00 0. " BYPASS ,YUV UP bypass." "0,1"
|
|
group ad:0xF0602200++0x03
|
|
line.long 0x00 "GP_CSC_CTRL_0,CSC control register."
|
|
bitfld.long 0x00 2. " ALPHA ,0: {alpha, pixel}, 1: {pixel, alpha};" "0,1"
|
|
bitfld.long 0x00 1. " SBUP_CONV ,0: p2,p1,p0, 1: p0,p1,p2" "0,1"
|
|
bitfld.long 0x00 0. " BYPASS ,CSC bypss" "0,1"
|
|
group ad:0xF0602204++0x03
|
|
line.long 0x00 "GP_CSC_COEF1_0,csc coef."
|
|
hexmask.long.word 0x00 16.--29. 1. " A01 ,a01"
|
|
hexmask.long.word 0x00 0.--13. 1. " A00 ,a00"
|
|
group ad:0xF0602208++0x03
|
|
line.long 0x00 "GP_CSC_COEF2_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " A10 ,a10"
|
|
hexmask.long.word 0x00 0.--13. 1. " A02 ,a02"
|
|
group ad:0xF060220C++0x03
|
|
line.long 0x00 "GP_CSC_COEF3_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " A12 ,a12"
|
|
hexmask.long.word 0x00 0.--13. 1. " A11 ,a11"
|
|
group ad:0xF0602210++0x03
|
|
line.long 0x00 "GP_CSC_COEF4_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " A21 ,a21"
|
|
hexmask.long.word 0x00 0.--13. 1. " A20 ,a20"
|
|
group ad:0xF0602214++0x03
|
|
line.long 0x00 "GP_CSC_COEF5_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " B0 ,b0"
|
|
hexmask.long.word 0x00 0.--13. 1. " A22 ,a22"
|
|
group ad:0xF0602218++0x03
|
|
line.long 0x00 "GP_CSC_COEF6_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " B2 ,b2"
|
|
hexmask.long.word 0x00 0.--13. 1. " B1 ,b1"
|
|
group ad:0xF060221C++0x03
|
|
line.long 0x00 "GP_CSC_COEF7_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--25. 1. " C1 ,c1"
|
|
hexmask.long.word 0x00 0.--9. 1. " C0 ,c0"
|
|
group ad:0xF0602220++0x03
|
|
line.long 0x00 "GP_CSC_COEF8_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 0.--9. 1. " C2 ,c2"
|
|
group ad:0xF0602D00++0x03
|
|
line.long 0x00 "GP_HDSK_CTRL_0,GP handshake controll register."
|
|
bitfld.long 0x00 1.--2. " HDSK_MODE ,Handshake mode: 0:8 line 1:16 line 2:32 line 3: 64 line" "0,1,2,3"
|
|
bitfld.long 0x00 0. " HDSK_EN ,Handshake enable." "0,1"
|
|
group ad:0xF0602D04++0x03
|
|
line.long 0x00 "GP_HDSK_STATUS_0,GP handshake controll register."
|
|
bitfld.long 0x00 3. " Y_RDY_1 ,Y channel buffer 1 rdy" "0,1"
|
|
bitfld.long 0x00 0. " Y_RDY_0 ,Y channel buffer 0 rdy" "0,1"
|
|
group ad:0xF0602E00++0x03
|
|
line.long 0x00 "GP_SW_RST_0,GP Software reset."
|
|
bitfld.long 0x00 0. " RST ,G-pipe software reset ,High active." "0,1"
|
|
group ad:0xF0602F00++0x03
|
|
line.long 0x00 "GP_SDW_CTRL_0,GP shadow ctrl"
|
|
bitfld.long 0x00 0. " TRIG ,channel shadow load trigger, software set to 1, when the registers are loaded, it will be cleard by HW." "0,1"
|
|
group ad:0xF0605000++0x03
|
|
line.long 0x00 "DC_SP_PIX_COMP_0,Pixle comp bpp setting."
|
|
bitfld.long 0x00 24.--27. " BPV ,bit per each V component, in bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " BPU ,bit per each U component, in bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--12. " BPY ,BPY[4:0]: bit per each Y component When BPY[4] = 0, bit per each Y component, in bit count When BPY[4] = 1, Byte per pixel, in Byte count -1 4'b0000: 1Byte/pixel 4'b0001: 2Byte/pixel 4'b0010: 3Byte/pixel 4'b0011:4Byte/pixel (.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " BPA ,Bpa: bit per each A component." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0605004++0x03
|
|
line.long 0x00 "DC_SP_FRM_CTRL_0,Frame control register."
|
|
bitfld.long 0x00 16.--18. " ENDIAN_CTRL ,Bit0: byte swap, bit1, hword swap, bit2 word swap" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. " COMP_SWAP ,Pixel component swap. When bit[3] = 1'b0, A channel is in MSB, When bit[3] =1'b1, A channel is in LSB, that means the B channel will be as A channel. 4'b0000:A/RGB 4'b0001:A/RBG 4'b0010:A/GBR 4'b0011:A/GRB 4'b0100:A/BGR .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--10. " ROT ,bit2: HFLIP, Bit1:Vflip Bit0:Rotation." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " RGB_YUV ,1'b0, RGB mode, 1'b1, YUV mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "UV_SWAP ,u/v channel swap" "0,1"
|
|
bitfld.long 0x00 4.--5. " UV_MODE ,UV_MODE[1:0], 2-bits encoded YUV sub-sample mode 2'b00: YUV444/RGB 2'b01: YUV422 2'b10: YUV440, this format happens when YUV422 image is rotated by 90 or 270 degree 2'b11: YUV420" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MODE ,2'b00: linear mode 2'b01: RLE compression mode. 2'b10: GPU tile mode 2'b11: reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FMT ,2-bits encoded frame buffer storage format 2'b00: Interleaved (RGB/YUV when BPA=0, ARGB/AYUV when BPA!=0) 2'b01: Monotonic 2'b10: Semi-Planar 2'b11: Planar" "0,1,2,3"
|
|
group ad:0xF0605008++0x03
|
|
line.long 0x00 "DC_SP_FRM_SIZE_0,Frame size."
|
|
hexmask.long.word 0x00 16.--31. 1. " HEIGHT ,Frame height, set value =real size -1;"
|
|
hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Frame width, set valule = real size -1;"
|
|
group ad:0xF060500C++0x03
|
|
line.long 0x00 "DC_SP_Y_BADDR_L_0,RGB or Y base address"
|
|
hexmask.long 0x00 0.--31. 1. " Y ,Y base address Low 32 bit."
|
|
group ad:0xF0605010++0x03
|
|
line.long 0x00 "DC_SP_Y_BADDR_H_0,RGB or Y base address"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Y ,Y base address high 8 bit."
|
|
group ad:0xF060502C++0x03
|
|
line.long 0x00 "DC_SP_Y_STRIDE_0,Stride for RGB or Y , byte unit."
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " Y ,Stride for RGB or Y , byte unit, real size -1; In GPU tile mode, it must align to GPU H-size"
|
|
group ad:0xF0605040++0x03
|
|
line.long 0x00 "DC_SP_FRM_OFFSET_0,dc_sp_frm_offset"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Frame UL y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Frame UL x coorDInate."
|
|
group ad:0xF0605100++0x03
|
|
line.long 0x00 "RLE_Y_LEN_0,RLE rgby length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " Y ,Y length. The setting value = RLE length(byte)/Data_size - 1)."
|
|
group ad:0xF0605110++0x03
|
|
line.long 0x00 "RLE_Y_CHECK_SUM_0,Y channel check sum set value."
|
|
hexmask.long 0x00 0.--31. 1. " Y ,RLE Y channel check_sum set value"
|
|
group ad:0xF0605120++0x03
|
|
line.long 0x00 "RLE_CTRL_0,RLE control register"
|
|
bitfld.long 0x00 1.--2. " RLE_DATA_SIZE ,RLE data size: 0: 1byte, 1: 2 byte. 2: 3 byte. 3: 4 byte." "0,1,2,3"
|
|
bitfld.long 0x00 0. " RLE_EN ,RLE enable." "0,1"
|
|
group ad:0xF0605130++0x03
|
|
line.long 0x00 "RLE_Y_CHECK_SUM_ST_0,Y channel check_sum real value"
|
|
hexmask.long 0x00 0.--31. 1. " Y ,RLE Y channel check sum real value."
|
|
group ad:0xF0605134++0x03
|
|
line.long 0x00 "RLE_U_CHECK_SUM_ST_0,U channel check_sum real value"
|
|
hexmask.long 0x00 0.--31. 1. " U ,U channel check sum real value ."
|
|
group ad:0xF0605138++0x03
|
|
line.long 0x00 "RLE_V_CHECK_SUM_ST_0,V channel check_sum real value"
|
|
hexmask.long 0x00 0.--31. 1. " V ,V channel check sum real value."
|
|
group ad:0xF060513C++0x03
|
|
line.long 0x00 "RLE_A_CHECK_SUM_ST_0,Alpha channel check_sum real value"
|
|
hexmask.long 0x00 0.--31. 1. " A ,Alpha channel check sum real value."
|
|
group ad:0xF0605140++0x03
|
|
line.long 0x00 "RLE_INT_MASK_0,RLE interrupt mask."
|
|
bitfld.long 0x00 3. " V_ERR ,v channel check sum error mask" "0,1"
|
|
bitfld.long 0x00 2. " U_ERR ,y channel check sum error mask" "0,1"
|
|
bitfld.long 0x00 1. " Y_ERR ,Y channel check sum error mask" "0,1"
|
|
bitfld.long 0x00 0. " A_ERR ,Alpha channel check sum error mask" "0,1"
|
|
group ad:0xF0605144++0x03
|
|
line.long 0x00 "RLE_INT_STATUS_0,RLE interrupt status."
|
|
bitfld.long 0x00 3. " V_ERR ,v channel check sum error status" "0,1"
|
|
bitfld.long 0x00 2. " U_ERR ,y channel check sum error status" "0,1"
|
|
bitfld.long 0x00 1. " Y_ERR ,Y channel check sum error status." "0,1"
|
|
bitfld.long 0x00 0. " A_ERR ,Alpha channel check sum error status" "0,1"
|
|
group ad:0xF0605200++0x03
|
|
line.long 0x00 "CLUT_A_CTRL_0,CLUT Alpha channel control."
|
|
bitfld.long 0x00 18. " HAS_ALPHA ,Alpha exist or not." "0,1"
|
|
bitfld.long 0x00 17. " A_Y_SEL ,Each channel use y channel input or own input select." "0,1"
|
|
bitfld.long 0x00 16. " BYPASS ,bypass" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OFFSET ,offset"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DEPTH ,clut depth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0605204++0x03
|
|
line.long 0x00 "CLUT_Y_CTRL_0,CLUT Y channel control."
|
|
bitfld.long 0x00 16. " BYPASS ,bypass" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OFFSET ,offset"
|
|
bitfld.long 0x00 0.--3. " DEPTH ,clut depth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0605208++0x03
|
|
line.long 0x00 "CLUT_U_CTRL_0,CLUT U channel control."
|
|
bitfld.long 0x00 17. " U_Y_SEL ,Each channel use y channel input or own input select." "0,1"
|
|
bitfld.long 0x00 16. " BYPASS ,bypass" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OFFSET ,offset"
|
|
bitfld.long 0x00 0.--3. " DEPTH ,clut depth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF060520C++0x03
|
|
line.long 0x00 "CLUT_V_CTRL_0,CLUT V channel control."
|
|
bitfld.long 0x00 17. " V_Y_SEL ,Each channel use y channel input or own input select." "0,1"
|
|
bitfld.long 0x00 16. " BYPASS ,bypass" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OFFSET ,offset"
|
|
bitfld.long 0x00 0.--3. " DEPTH ,clut depth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0605210++0x03
|
|
line.long 0x00 "CLUT_READ_CTRL_0,Color look up table read control."
|
|
bitfld.long 0x00 0. " APB_SEL ,0: CLUT read, 1: APB read ." "0,1"
|
|
group ad:0xF0605214++0x03
|
|
line.long 0x00 "CLUT_BADDRL_0,Color look up table Baddr."
|
|
hexmask.long 0x00 0.--31. 1. " CLUT ,clut table addr[31:0]"
|
|
group ad:0xF0605218++0x03
|
|
line.long 0x00 "CLUT_BADDRH_0,Color look up table Baddr."
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLUT ,CLUT table addr[39:32]"
|
|
group ad:0xF060521C++0x03
|
|
line.long 0x00 "CLUT_LOAD_CTRL_0,Color look up table load control register."
|
|
bitfld.long 0x00 0. " EN ,CLUT table load enable." "0,1"
|
|
group ad:0xF0605E00++0x03
|
|
line.long 0x00 "SP_SW_RST_0,S-pipe SW reset."
|
|
bitfld.long 0x00 0. " RST ,S-pipe software reset, high active." "0,1"
|
|
group ad:0xF0605F00++0x03
|
|
line.long 0x00 "SP_SDW_CTRL_0,sp_sdw_ctrl"
|
|
bitfld.long 0x00 0. " TRIG ,channel shadow load trigger, software set to 1, when the registers are loaded, it will be cleard by HW." "0,1"
|
|
group ad:0xF0606000++0x03
|
|
line.long 0x00 "DC_SP_PIX_COMP_1,Pixle comp bpp setting."
|
|
bitfld.long 0x00 24.--27. " BPV ,bit per each V component, in bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " BPU ,bit per each U component, in bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--12. " BPY ,BPY[4:0]: bit per each Y component When BPY[4] = 0, bit per each Y component, in bit count When BPY[4] = 1, Byte per pixel, in Byte count -1 4'b0000: 1Byte/pixel 4'b0001: 2Byte/pixel 4'b0010: 3Byte/pixel 4'b0011:4Byte/pixel (.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " BPA ,Bpa: bit per each A component." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0606004++0x03
|
|
line.long 0x00 "DC_SP_FRM_CTRL_1,Frame control register."
|
|
bitfld.long 0x00 16.--18. " ENDIAN_CTRL ,Bit0: byte swap, bit1, hword swap, bit2 word swap" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. " COMP_SWAP ,Pixel component swap. When bit[3] = 1'b0, A channel is in MSB, When bit[3] =1'b1, A channel is in LSB, that means the B channel will be as A channel. 4'b0000:A/RGB 4'b0001:A/RBG 4'b0010:A/GBR 4'b0011:A/GRB 4'b0100:A/BGR .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--10. " ROT ,bit2: HFLIP, Bit1:Vflip Bit0:Rotation." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " RGB_YUV ,1'b0, RGB mode, 1'b1, YUV mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "UV_SWAP ,u/v channel swap" "0,1"
|
|
bitfld.long 0x00 4.--5. " UV_MODE ,UV_MODE[1:0], 2-bits encoded YUV sub-sample mode 2'b00: YUV444/RGB 2'b01: YUV422 2'b10: YUV440, this format happens when YUV422 image is rotated by 90 or 270 degree 2'b11: YUV420" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MODE ,2'b00: linear mode 2'b01: RLE compression mode. 2'b10: GPU tile mode 2'b11: reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FMT ,2-bits encoded frame buffer storage format 2'b00: Interleaved (RGB/YUV when BPA=0, ARGB/AYUV when BPA!=0) 2'b01: Monotonic 2'b10: Semi-Planar 2'b11: Planar" "0,1,2,3"
|
|
group ad:0xF0606008++0x03
|
|
line.long 0x00 "DC_SP_FRM_SIZE_1,Frame size."
|
|
hexmask.long.word 0x00 16.--31. 1. " HEIGHT ,Frame height, set value =real size -1;"
|
|
hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Frame width, set valule = real size -1;"
|
|
group ad:0xF060600C++0x03
|
|
line.long 0x00 "DC_SP_Y_BADDR_L_1,RGB or Y base address"
|
|
hexmask.long 0x00 0.--31. 1. " Y ,Y base address Low 32 bit."
|
|
group ad:0xF0606010++0x03
|
|
line.long 0x00 "DC_SP_Y_BADDR_H_1,RGB or Y base address"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Y ,Y base address high 8 bit."
|
|
group ad:0xF060602C++0x03
|
|
line.long 0x00 "DC_SP_Y_STRIDE_1,Stride for RGB or Y , byte unit."
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " Y ,Stride for RGB or Y , byte unit, real size -1; In GPU tile mode, it must align to GPU H-size"
|
|
group ad:0xF0606040++0x03
|
|
line.long 0x00 "DC_SP_FRM_OFFSET_1,dc_sp_frm_offset"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Frame UL y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Frame UL x coorDInate."
|
|
group ad:0xF0606100++0x03
|
|
line.long 0x00 "RLE_Y_LEN_1,RLE rgby length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " Y ,Y length. The setting value = RLE length(byte)/Data_size - 1)."
|
|
group ad:0xF0606110++0x03
|
|
line.long 0x00 "RLE_Y_CHECK_SUM_1,Y channel check sum set value."
|
|
hexmask.long 0x00 0.--31. 1. " Y ,RLE Y channel check_sum set value"
|
|
group ad:0xF0606120++0x03
|
|
line.long 0x00 "RLE_CTRL_1,RLE control register"
|
|
bitfld.long 0x00 1.--2. " RLE_DATA_SIZE ,RLE data size: 0: 1byte, 1: 2 byte. 2: 3 byte. 3: 4 byte." "0,1,2,3"
|
|
bitfld.long 0x00 0. " RLE_EN ,RLE enable." "0,1"
|
|
group ad:0xF0606130++0x03
|
|
line.long 0x00 "RLE_Y_CHECK_SUM_ST_1,Y channel check_sum real value"
|
|
hexmask.long 0x00 0.--31. 1. " Y ,RLE Y channel check sum real value."
|
|
group ad:0xF0606134++0x03
|
|
line.long 0x00 "RLE_U_CHECK_SUM_ST_1,U channel check_sum real value"
|
|
hexmask.long 0x00 0.--31. 1. " U ,U channel check sum real value ."
|
|
group ad:0xF0606138++0x03
|
|
line.long 0x00 "RLE_V_CHECK_SUM_ST_1,V channel check_sum real value"
|
|
hexmask.long 0x00 0.--31. 1. " V ,V channel check sum real value."
|
|
group ad:0xF060613C++0x03
|
|
line.long 0x00 "RLE_A_CHECK_SUM_ST_1,Alpha channel check_sum real value"
|
|
hexmask.long 0x00 0.--31. 1. " A ,Alpha channel check sum real value."
|
|
group ad:0xF0606140++0x03
|
|
line.long 0x00 "RLE_INT_MASK_1,RLE interrupt mask."
|
|
bitfld.long 0x00 3. " V_ERR ,v channel check sum error mask" "0,1"
|
|
bitfld.long 0x00 2. " U_ERR ,y channel check sum error mask" "0,1"
|
|
bitfld.long 0x00 1. " Y_ERR ,Y channel check sum error mask" "0,1"
|
|
bitfld.long 0x00 0. " A_ERR ,Alpha channel check sum error mask" "0,1"
|
|
group ad:0xF0606144++0x03
|
|
line.long 0x00 "RLE_INT_STATUS_1,RLE interrupt status."
|
|
bitfld.long 0x00 3. " V_ERR ,v channel check sum error status" "0,1"
|
|
bitfld.long 0x00 2. " U_ERR ,y channel check sum error status" "0,1"
|
|
bitfld.long 0x00 1. " Y_ERR ,Y channel check sum error status." "0,1"
|
|
bitfld.long 0x00 0. " A_ERR ,Alpha channel check sum error status" "0,1"
|
|
group ad:0xF0606200++0x03
|
|
line.long 0x00 "CLUT_A_CTRL_1,CLUT Alpha channel control."
|
|
bitfld.long 0x00 18. " HAS_ALPHA ,Alpha exist or not." "0,1"
|
|
bitfld.long 0x00 17. " A_Y_SEL ,Each channel use y channel input or own input select." "0,1"
|
|
bitfld.long 0x00 16. " BYPASS ,bypass" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OFFSET ,offset"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DEPTH ,clut depth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0606204++0x03
|
|
line.long 0x00 "CLUT_Y_CTRL_1,CLUT Y channel control."
|
|
bitfld.long 0x00 16. " BYPASS ,bypass" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OFFSET ,offset"
|
|
bitfld.long 0x00 0.--3. " DEPTH ,clut depth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0606208++0x03
|
|
line.long 0x00 "CLUT_U_CTRL_1,CLUT U channel control."
|
|
bitfld.long 0x00 17. " U_Y_SEL ,Each channel use y channel input or own input select." "0,1"
|
|
bitfld.long 0x00 16. " BYPASS ,bypass" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OFFSET ,offset"
|
|
bitfld.long 0x00 0.--3. " DEPTH ,clut depth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF060620C++0x03
|
|
line.long 0x00 "CLUT_V_CTRL_1,CLUT V channel control."
|
|
bitfld.long 0x00 17. " V_Y_SEL ,Each channel use y channel input or own input select." "0,1"
|
|
bitfld.long 0x00 16. " BYPASS ,bypass" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OFFSET ,offset"
|
|
bitfld.long 0x00 0.--3. " DEPTH ,clut depth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0606210++0x03
|
|
line.long 0x00 "CLUT_READ_CTRL_1,Color look up table read control."
|
|
bitfld.long 0x00 0. " APB_SEL ,0: CLUT read, 1: APB read ." "0,1"
|
|
group ad:0xF0606214++0x03
|
|
line.long 0x00 "CLUT_BADDRL_1,Color look up table Baddr."
|
|
hexmask.long 0x00 0.--31. 1. " CLUT ,clut table addr[31:0]"
|
|
group ad:0xF0606218++0x03
|
|
line.long 0x00 "CLUT_BADDRH_1,Color look up table Baddr."
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLUT ,CLUT table addr[39:32]"
|
|
group ad:0xF060621C++0x03
|
|
line.long 0x00 "CLUT_LOAD_CTRL_1,Color look up table load control register."
|
|
bitfld.long 0x00 0. " EN ,CLUT table load enable." "0,1"
|
|
group ad:0xF0606E00++0x03
|
|
line.long 0x00 "SP_SW_RST_1,S-pipe SW reset."
|
|
bitfld.long 0x00 0. " RST ,S-pipe software reset, high active." "0,1"
|
|
group ad:0xF0606F00++0x03
|
|
line.long 0x00 "SP_SDW_CTRL_1,sp_sdw_ctrl"
|
|
bitfld.long 0x00 0. " TRIG ,channel shadow load trigger, software set to 1, when the registers are loaded, it will be cleard by HW." "0,1"
|
|
group ad:0xF0607000++0x03
|
|
line.long 0x00 "MLC_SF_CTRL_0,MLC surface control register."
|
|
hexmask.long.byte 0x00 8.--13. 1. " PROT_VAL ,Protect Y value."
|
|
bitfld.long 0x00 7. " VPOS_PROT_EN ,Vertical position protect enable." "0,1"
|
|
bitfld.long 0x00 6. " SLOWDOWN_EN ,Slowdown enable." "0,1"
|
|
bitfld.long 0x00 5. " AFLU_PSEL ,auto flush pixel select 0=DIsplay the last normal pixel after flush 1=do not DIsplay broken part after flush" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 3. " CKEY_EN ,color key enable." "0,1"
|
|
bitfld.long 0x00 2. " G_ALPHA_EN ,Globl Alpha enable." "0,1"
|
|
bitfld.long 0x00 1. " CROP_EN ,crop enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SF_EN ,surface enable. If this bit is changed, then corresponDIng GPIPE/SPIPE SDW_CTRL.trig bit must be set." "0,1"
|
|
group ad:0xF0607004++0x03
|
|
line.long 0x00 "MLC_SF_H_SPOS_0,Surface h position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " H ,h positon."
|
|
group ad:0xF0607008++0x03
|
|
line.long 0x00 "MLC_SF_V_SPOS_0,Surface v position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " V ,v position."
|
|
group ad:0xF060700C++0x03
|
|
line.long 0x00 "MLC_SF_SIZE_0,Surface size."
|
|
hexmask.long.word 0x00 16.--31. 1. " V ,v size"
|
|
hexmask.long.word 0x00 0.--15. 1. " H ,h size."
|
|
group ad:0xF0607010++0x03
|
|
line.long 0x00 "MLC_SF_CROP_H_POS_0,Surface crop h position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop h end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop h start position"
|
|
group ad:0xF0607014++0x03
|
|
line.long 0x00 "MLC_SF_CROP_V_POS_0,Surface crop v position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop v end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop v start position"
|
|
group ad:0xF0607018++0x03
|
|
line.long 0x00 "MLC_SF_G_ALPHA_0,Surface globl alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,Globl alpha"
|
|
group ad:0xF060701C++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_ALPHA_0,Surface color key alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,color key alpha"
|
|
group ad:0xF0607020++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_R_LV_0,R channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,down level."
|
|
group ad:0xF0607024++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_G_LV_0,g channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF0607028++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_B_LV_0,b channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF060702C++0x03
|
|
line.long 0x00 "MLC_SF_AFLU_TIME_0,auto flush time."
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,auto-flush time setting bit[31:16]=not used {bit[15:1],1'b0}=time-out time setting counted by MLC clock cycles when bit[0]=0 and MLC_SF_CTRL_0.AFLU_EN=0, DIsable flush timer, in other cases, enable flush timer.."
|
|
group ad:0xF0607030++0x03
|
|
line.long 0x00 "MLC_SF_CTRL_1,MLC surface control register."
|
|
hexmask.long.byte 0x00 8.--13. 1. " PROT_VAL ,Protect Y value."
|
|
bitfld.long 0x00 7. " VPOS_PROT_EN ,Vertical position protect enable." "0,1"
|
|
bitfld.long 0x00 6. " SLOWDOWN_EN ,Slowdown enable." "0,1"
|
|
bitfld.long 0x00 5. " AFLU_PSEL ,auto flush pixel select 0=DIsplay the last normal pixel after flush 1=do not DIsplay broken part after flush" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 3. " CKEY_EN ,color key enable." "0,1"
|
|
bitfld.long 0x00 2. " G_ALPHA_EN ,Globl Alpha enable." "0,1"
|
|
bitfld.long 0x00 1. " CROP_EN ,crop enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SF_EN ,surface enable. If this bit is changed, then corresponDIng GPIPE/SPIPE SDW_CTRL.trig bit must be set." "0,1"
|
|
group ad:0xF0607034++0x03
|
|
line.long 0x00 "MLC_SF_H_SPOS_1,Surface h position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " H ,h positon."
|
|
group ad:0xF0607038++0x03
|
|
line.long 0x00 "MLC_SF_V_SPOS_1,Surface v position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " V ,v position."
|
|
group ad:0xF060703C++0x03
|
|
line.long 0x00 "MLC_SF_SIZE_1,Surface size."
|
|
hexmask.long.word 0x00 16.--31. 1. " V ,v size"
|
|
hexmask.long.word 0x00 0.--15. 1. " H ,h size."
|
|
group ad:0xF0607040++0x03
|
|
line.long 0x00 "MLC_SF_CROP_H_POS_1,Surface crop h position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop h end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop h start position"
|
|
group ad:0xF0607044++0x03
|
|
line.long 0x00 "MLC_SF_CROP_V_POS_1,Surface crop v position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop v end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop v start position"
|
|
group ad:0xF0607048++0x03
|
|
line.long 0x00 "MLC_SF_G_ALPHA_1,Surface globl alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,Globl alpha"
|
|
group ad:0xF060704C++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_ALPHA_1,Surface color key alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,color key alpha"
|
|
group ad:0xF0607050++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_R_LV_1,R channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,down level."
|
|
group ad:0xF0607054++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_G_LV_1,g channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF0607058++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_B_LV_1,b channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF060705C++0x03
|
|
line.long 0x00 "MLC_SF_AFLU_TIME_1,auto flush time."
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,auto-flush time setting bit[31:16]=not used {bit[15:1],1'b0}=time-out time setting counted by MLC clock cycles when bit[0]=0 and MLC_SF_CTRL_1.AFLU_EN=0, DIsable flush timer, in other cases, enable flush timer.."
|
|
group ad:0xF0607060++0x03
|
|
line.long 0x00 "MLC_SF_CTRL_2,MLC surface control register."
|
|
hexmask.long.byte 0x00 8.--13. 1. " PROT_VAL ,Protect Y value."
|
|
bitfld.long 0x00 7. " VPOS_PROT_EN ,Vertical position protect enable." "0,1"
|
|
bitfld.long 0x00 6. " SLOWDOWN_EN ,Slowdown enable." "0,1"
|
|
bitfld.long 0x00 5. " AFLU_PSEL ,auto flush pixel select 0=DIsplay the last normal pixel after flush 1=do not DIsplay broken part after flush" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 3. " CKEY_EN ,color key enable." "0,1"
|
|
bitfld.long 0x00 2. " G_ALPHA_EN ,Globl Alpha enable." "0,1"
|
|
bitfld.long 0x00 1. " CROP_EN ,crop enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SF_EN ,surface enable. If this bit is changed, then corresponDIng GPIPE/SPIPE SDW_CTRL.trig bit must be set." "0,1"
|
|
group ad:0xF0607064++0x03
|
|
line.long 0x00 "MLC_SF_H_SPOS_2,Surface h position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " H ,h positon."
|
|
group ad:0xF0607068++0x03
|
|
line.long 0x00 "MLC_SF_V_SPOS_2,Surface v position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " V ,v position."
|
|
group ad:0xF060706C++0x03
|
|
line.long 0x00 "MLC_SF_SIZE_2,Surface size."
|
|
hexmask.long.word 0x00 16.--31. 1. " V ,v size"
|
|
hexmask.long.word 0x00 0.--15. 1. " H ,h size."
|
|
group ad:0xF0607070++0x03
|
|
line.long 0x00 "MLC_SF_CROP_H_POS_2,Surface crop h position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop h end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop h start position"
|
|
group ad:0xF0607074++0x03
|
|
line.long 0x00 "MLC_SF_CROP_V_POS_2,Surface crop v position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop v end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop v start position"
|
|
group ad:0xF0607078++0x03
|
|
line.long 0x00 "MLC_SF_G_ALPHA_2,Surface globl alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,Globl alpha"
|
|
group ad:0xF060707C++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_ALPHA_2,Surface color key alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,color key alpha"
|
|
group ad:0xF0607080++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_R_LV_2,R channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,down level."
|
|
group ad:0xF0607084++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_G_LV_2,g channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF0607088++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_B_LV_2,b channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF060708C++0x03
|
|
line.long 0x00 "MLC_SF_AFLU_TIME_2,auto flush time."
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,auto-flush time setting bit[31:16]=not used {bit[15:1],1'b0}=time-out time setting counted by MLC clock cycles when bit[0]=0 and MLC_SF_CTRL_2.AFLU_EN=0, DIsable flush timer, in other cases, enable flush timer.."
|
|
group ad:0xF0607090++0x03
|
|
line.long 0x00 "MLC_SF_CTRL_3,MLC surface control register."
|
|
hexmask.long.byte 0x00 8.--13. 1. " PROT_VAL ,Protect Y value."
|
|
bitfld.long 0x00 7. " VPOS_PROT_EN ,Vertical position protect enable." "0,1"
|
|
bitfld.long 0x00 6. " SLOWDOWN_EN ,Slowdown enable." "0,1"
|
|
bitfld.long 0x00 5. " AFLU_PSEL ,auto flush pixel select 0=DIsplay the last normal pixel after flush 1=do not DIsplay broken part after flush" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 3. " CKEY_EN ,color key enable." "0,1"
|
|
bitfld.long 0x00 2. " G_ALPHA_EN ,Globl Alpha enable." "0,1"
|
|
bitfld.long 0x00 1. " CROP_EN ,crop enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SF_EN ,surface enable. If this bit is changed, then corresponDIng GPIPE/SPIPE SDW_CTRL.trig bit must be set." "0,1"
|
|
group ad:0xF0607094++0x03
|
|
line.long 0x00 "MLC_SF_H_SPOS_3,Surface h position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " H ,h positon."
|
|
group ad:0xF0607098++0x03
|
|
line.long 0x00 "MLC_SF_V_SPOS_3,Surface v position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " V ,v position."
|
|
group ad:0xF060709C++0x03
|
|
line.long 0x00 "MLC_SF_SIZE_3,Surface size."
|
|
hexmask.long.word 0x00 16.--31. 1. " V ,v size"
|
|
hexmask.long.word 0x00 0.--15. 1. " H ,h size."
|
|
group ad:0xF06070A0++0x03
|
|
line.long 0x00 "MLC_SF_CROP_H_POS_3,Surface crop h position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop h end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop h start position"
|
|
group ad:0xF06070A4++0x03
|
|
line.long 0x00 "MLC_SF_CROP_V_POS_3,Surface crop v position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop v end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop v start position"
|
|
group ad:0xF06070A8++0x03
|
|
line.long 0x00 "MLC_SF_G_ALPHA_3,Surface globl alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,Globl alpha"
|
|
group ad:0xF06070AC++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_ALPHA_3,Surface color key alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,color key alpha"
|
|
group ad:0xF06070B0++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_R_LV_3,R channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,down level."
|
|
group ad:0xF06070B4++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_G_LV_3,g channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF06070B8++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_B_LV_3,b channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF06070BC++0x03
|
|
line.long 0x00 "MLC_SF_AFLU_TIME_3,auto flush time."
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,auto-flush time setting bit[31:16]=not used {bit[15:1],1'b0}=time-out time setting counted by MLC clock cycles when bit[0]=0 and MLC_SF_CTRL_3.AFLU_EN=0, DIsable flush timer, in other cases, enable flush timer.."
|
|
group ad:0xF0607200++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_0,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0607204++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_1,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0607208++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_2,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF060720C++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_3,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0607210++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_4,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0607220++0x03
|
|
line.long 0x00 "MLC_BG_CTRL,mlc back groud layer and canvas layer control."
|
|
hexmask.long.byte 0x00 8.--15. 1. " BG_A ,Back ground layer Alpha."
|
|
bitfld.long 0x00 7. " AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 4.--6. " FSTART_SEL ,fs frame start select." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " BG_A_SEL ,back ground layer alpha select." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "BG_EN ,back ground layer enable." "0,1"
|
|
bitfld.long 0x00 0. " ALPHA_BLD_BYPS ,alpha blenDIng bypass." "0,1"
|
|
group ad:0xF0607224++0x03
|
|
line.long 0x00 "MLC_BG_COLOR,MLC Back ground color."
|
|
hexmask.long.word 0x00 20.--29. 1. " R ,R channel color."
|
|
hexmask.long.word 0x00 10.--19. 1. " G ,G channel color."
|
|
hexmask.long.word 0x00 0.--9. 1. " B ,B channel color."
|
|
group ad:0xF0607228++0x03
|
|
line.long 0x00 "MLC_BG_AFLU_TIME,BG auto flush time"
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,not used"
|
|
group ad:0xF0607230++0x03
|
|
line.long 0x00 "MLC_CANVAS_COLOR,MLC Canvas color."
|
|
hexmask.long.word 0x00 20.--29. 1. " R ,R channel color."
|
|
hexmask.long.word 0x00 10.--19. 1. " G ,G channel color."
|
|
hexmask.long.word 0x00 0.--9. 1. " B ,B channel color."
|
|
group ad:0xF0607234++0x03
|
|
line.long 0x00 "MLC_CLK_RATIO,Ratio of dsp_clk and pix_clk period."
|
|
hexmask.long.word 0x00 0.--15. 1. " RATIO ,(int) ((TCON clock period/MLC clock period)*2^12)"
|
|
group ad:0xF0607238++0x03
|
|
line.long 0x00 "MLC_AFLU_HBLANK_TIME,TCON hblank time setting for flush timer"
|
|
hexmask.long 0x00 0.--31. 1. " val ,(int)(((htotal-hactive)*(TCON clock period/MLC clock period))*2^12)"
|
|
group ad:0xF0607240++0x03
|
|
line.long 0x00 "MLC_INT_MASK,MLC interrupt mask."
|
|
bitfld.long 0x00 12. " ERR_LAYER_5 ,MCL Layer5 Error(For DC reserved.)" "0,1"
|
|
bitfld.long 0x00 11. " ERR_LAYER_4 ,MCL Layer4 Error(For DC reserved.)" "0,1"
|
|
bitfld.long 0x00 10. " ERR_LAYER_3 ,MCL Layer3 Error(For DC, DP layer.)" "0,1"
|
|
bitfld.long 0x00 9. " ERR_LAYER_2 ,MCL Layer2 Error(gp)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "ERR_LAYER_1 ,MCL Layer1 Error(sp)" "0,1"
|
|
bitfld.long 0x00 7. " ERR_LAYER_0 ,MCL Layer0 Error(BG, for the DC reserved.)" "0,1"
|
|
bitfld.long 0x00 6. " FLU_LAYER_5 ,MCL Layer5 flsah(For DC reserved.)" "0,1"
|
|
bitfld.long 0x00 5. " FLU_LAYER_4 ,MCL Layer4 flsah(For the DC reserved)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FLU_LAYER_3 ,MCL Layer3 flsah(For the DC DP layer.)" "0,1"
|
|
bitfld.long 0x00 3. " FLU_LAYER_2 ,MCL Layer2 flsah(GP)" "0,1"
|
|
bitfld.long 0x00 2. " FLU_LAYER_1 ,MCL Layer1 flsah(SP)" "0,1"
|
|
bitfld.long 0x00 1. " FLU_LAYER_0 ,MCL Layer0 flsah(BG layer, for DC, reserved.)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FRM_END ,MCL frame end" "0,1"
|
|
group ad:0xF0607244++0x03
|
|
line.long 0x00 "MLC_INT_STATUS,MLC interrupt status."
|
|
bitfld.long 0x00 27. " SLOWD_LAYER_5 ,slow down layer 5." "0,1"
|
|
bitfld.long 0x00 26. " SLOWD_LAYER_4 ,slow down layer 4." "0,1"
|
|
bitfld.long 0x00 25. " SLOWD_LAYER_3 ,slow down layer 3." "0,1"
|
|
bitfld.long 0x00 24. " SLOWD_LAYER_2 ,slow down layer 2." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SLOWD_LAYER_1 ,slow down layer 1." "0,1"
|
|
bitfld.long 0x00 22. " SLOWD_LAYER_0 ,slow down layer 0." "0,1"
|
|
bitfld.long 0x00 21. " CROP_ERR_LAYER_5 ,crop position error." "0,1"
|
|
bitfld.long 0x00 20. " CROP_ERR_LAYER_4 ,crop position error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CROP_ERR_LAYER_3 ,crop position error." "0,1"
|
|
bitfld.long 0x00 18. " CROP_ERR_LAYER_2 ,crop position error." "0,1"
|
|
bitfld.long 0x00 17. " CROP_ERR_LAYER_1 ,crop position error." "0,1"
|
|
bitfld.long 0x00 16. " CROP_ERR_LAYER_0 ,crop position error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ERR_LAYER_5 ,MLC Layer5Error." "0,1"
|
|
bitfld.long 0x00 11. " ERR_LAYER_4 ,MLC Layer4Error." "0,1"
|
|
bitfld.long 0x00 10. " ERR_LAYER_3 ,MLC Layer3Error." "0,1"
|
|
bitfld.long 0x00 9. " ERR_LAYER_2 ,MLC Layer2Error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "ERR_LAYER_1 ,MLC Layer1 Error." "0,1"
|
|
bitfld.long 0x00 7. " ERR_LAYER_0 ,MLC Layer0 Error." "0,1"
|
|
bitfld.long 0x00 6. " FLU_LAYER_5 ,Reserved" "0,1"
|
|
bitfld.long 0x00 5. " FLU_LAYER_4 ,MCL Layer3 flush(optional DP2 for DC1/DC2 )" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FLU_LAYER_3 ,MCL Layer2 flush(DP1)" "0,1"
|
|
bitfld.long 0x00 3. " FLU_LAYER_2 ,MCL Layer1 flush(GP)" "0,1"
|
|
bitfld.long 0x00 2. " FLU_LAYER_1 ,MCL Layer0 flush(SP)" "0,1"
|
|
bitfld.long 0x00 1. " FLU_LAYER_0 ,MCL BG layer, For DC reserved." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FRM_END ,MCL frame end" "0,1"
|
|
group ad:0xF0608000++0x03
|
|
line.long 0x00 "MLC_SF_CTRL_S_0,MLC surface control register."
|
|
hexmask.long.byte 0x00 8.--13. 1. " PROT_VAL ,Protect Y value."
|
|
bitfld.long 0x00 7. " VPOS_PROT_EN ,Vertical position protect enable." "0,1"
|
|
bitfld.long 0x00 6. " SLOWDOWN_EN ,Slowdown enable." "0,1"
|
|
bitfld.long 0x00 5. " AFLU_PSEL ,auto flush pixel select." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 3. " CKEY_EN ,color key enable." "0,1"
|
|
bitfld.long 0x00 2. " G_ALPHA_EN ,Globl Alpha enable." "0,1"
|
|
bitfld.long 0x00 1. " CROP_EN ,crop enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SF_EN ,surface enable." "0,1"
|
|
group ad:0xF0608004++0x03
|
|
line.long 0x00 "MLC_SF_H_SPOS_S_0,Surface h position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " H ,h positon."
|
|
group ad:0xF0608008++0x03
|
|
line.long 0x00 "MLC_SF_V_SPOS_S_0,Surface v position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " V ,v position."
|
|
group ad:0xF060800C++0x03
|
|
line.long 0x00 "MLC_SF_SIZE_S_0,Surface size."
|
|
hexmask.long.word 0x00 16.--31. 1. " V ,v size"
|
|
hexmask.long.word 0x00 0.--15. 1. " H ,h size."
|
|
group ad:0xF0608010++0x03
|
|
line.long 0x00 "MLC_SF_CROP_H_POS_S_0,Surface crop h position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop h end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop h start position"
|
|
group ad:0xF0608014++0x03
|
|
line.long 0x00 "MLC_SF_CROP_V_POS_S_0,Surface crop v position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop v end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop v start position"
|
|
group ad:0xF0608018++0x03
|
|
line.long 0x00 "MLC_SF_G_ALPHA_S_0,Surface globl alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,Globl alpha"
|
|
group ad:0xF060801C++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_ALPHA_S_0,Surface color key alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,color key alpha"
|
|
group ad:0xF0608020++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_R_LV_S_0,R channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,down level."
|
|
group ad:0xF0608024++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_G_LV_S_0,g channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF0608028++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_B_LV_S_0,b channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF060802C++0x03
|
|
line.long 0x00 "MLC_SF_AFLU_TIME_S_0,auto flush time."
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,auto-flush time setting bit[31:16]=current layer's blank time counted by MLC clock cycles {bit[15:1],1'b0}=time-out time setting counted by MLC clock cycles when bit[0]=0 and MLC_SF_CTRL_0.AFLU_EN=0, DIsable flush timer, in .."
|
|
group ad:0xF0608030++0x03
|
|
line.long 0x00 "MLC_SF_CTRL_S_1,MLC surface control register."
|
|
hexmask.long.byte 0x00 8.--13. 1. " PROT_VAL ,Protect Y value."
|
|
bitfld.long 0x00 7. " VPOS_PROT_EN ,Vertical position protect enable." "0,1"
|
|
bitfld.long 0x00 6. " SLOWDOWN_EN ,Slowdown enable." "0,1"
|
|
bitfld.long 0x00 5. " AFLU_PSEL ,auto flush pixel select." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 3. " CKEY_EN ,color key enable." "0,1"
|
|
bitfld.long 0x00 2. " G_ALPHA_EN ,Globl Alpha enable." "0,1"
|
|
bitfld.long 0x00 1. " CROP_EN ,crop enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SF_EN ,surface enable." "0,1"
|
|
group ad:0xF0608034++0x03
|
|
line.long 0x00 "MLC_SF_H_SPOS_S_1,Surface h position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " H ,h positon."
|
|
group ad:0xF0608038++0x03
|
|
line.long 0x00 "MLC_SF_V_SPOS_S_1,Surface v position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " V ,v position."
|
|
group ad:0xF060803C++0x03
|
|
line.long 0x00 "MLC_SF_SIZE_S_1,Surface size."
|
|
hexmask.long.word 0x00 16.--31. 1. " V ,v size"
|
|
hexmask.long.word 0x00 0.--15. 1. " H ,h size."
|
|
group ad:0xF0608040++0x03
|
|
line.long 0x00 "MLC_SF_CROP_H_POS_S_1,Surface crop h position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop h end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop h start position"
|
|
group ad:0xF0608044++0x03
|
|
line.long 0x00 "MLC_SF_CROP_V_POS_S_1,Surface crop v position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop v end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop v start position"
|
|
group ad:0xF0608048++0x03
|
|
line.long 0x00 "MLC_SF_G_ALPHA_S_1,Surface globl alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,Globl alpha"
|
|
group ad:0xF060804C++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_ALPHA_S_1,Surface color key alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,color key alpha"
|
|
group ad:0xF0608050++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_R_LV_S_1,R channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,down level."
|
|
group ad:0xF0608054++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_G_LV_S_1,g channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF0608058++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_B_LV_S_1,b channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF060805C++0x03
|
|
line.long 0x00 "MLC_SF_AFLU_TIME_S_1,auto flush time."
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,auto-flush time setting bit[31:16]=current layer's blank time counted by MLC clock cycles {bit[15:1],1'b0}=time-out time setting counted by MLC clock cycles when bit[0]=0 and MLC_SF_CTRL_1.AFLU_EN=0, DIsable flush timer, in .."
|
|
group ad:0xF0608060++0x03
|
|
line.long 0x00 "MLC_SF_CTRL_S_2,MLC surface control register."
|
|
hexmask.long.byte 0x00 8.--13. 1. " PROT_VAL ,Protect Y value."
|
|
bitfld.long 0x00 7. " VPOS_PROT_EN ,Vertical position protect enable." "0,1"
|
|
bitfld.long 0x00 6. " SLOWDOWN_EN ,Slowdown enable." "0,1"
|
|
bitfld.long 0x00 5. " AFLU_PSEL ,auto flush pixel select." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 3. " CKEY_EN ,color key enable." "0,1"
|
|
bitfld.long 0x00 2. " G_ALPHA_EN ,Globl Alpha enable." "0,1"
|
|
bitfld.long 0x00 1. " CROP_EN ,crop enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SF_EN ,surface enable." "0,1"
|
|
group ad:0xF0608064++0x03
|
|
line.long 0x00 "MLC_SF_H_SPOS_S_2,Surface h position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " H ,h positon."
|
|
group ad:0xF0608068++0x03
|
|
line.long 0x00 "MLC_SF_V_SPOS_S_2,Surface v position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " V ,v position."
|
|
group ad:0xF060806C++0x03
|
|
line.long 0x00 "MLC_SF_SIZE_S_2,Surface size."
|
|
hexmask.long.word 0x00 16.--31. 1. " V ,v size"
|
|
hexmask.long.word 0x00 0.--15. 1. " H ,h size."
|
|
group ad:0xF0608070++0x03
|
|
line.long 0x00 "MLC_SF_CROP_H_POS_S_2,Surface crop h position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop h end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop h start position"
|
|
group ad:0xF0608074++0x03
|
|
line.long 0x00 "MLC_SF_CROP_V_POS_S_2,Surface crop v position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop v end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop v start position"
|
|
group ad:0xF0608078++0x03
|
|
line.long 0x00 "MLC_SF_G_ALPHA_S_2,Surface globl alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,Globl alpha"
|
|
group ad:0xF060807C++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_ALPHA_S_2,Surface color key alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,color key alpha"
|
|
group ad:0xF0608080++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_R_LV_S_2,R channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,down level."
|
|
group ad:0xF0608084++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_G_LV_S_2,g channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF0608088++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_B_LV_S_2,b channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF060808C++0x03
|
|
line.long 0x00 "MLC_SF_AFLU_TIME_S_2,auto flush time."
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,auto-flush time setting bit[31:16]=current layer's blank time counted by MLC clock cycles {bit[15:1],1'b0}=time-out time setting counted by MLC clock cycles when bit[0]=0 and MLC_SF_CTRL_2.AFLU_EN=0, DIsable flush timer, in .."
|
|
group ad:0xF0608090++0x03
|
|
line.long 0x00 "MLC_SF_CTRL_S_3,MLC surface control register."
|
|
hexmask.long.byte 0x00 8.--13. 1. " PROT_VAL ,Protect Y value."
|
|
bitfld.long 0x00 7. " VPOS_PROT_EN ,Vertical position protect enable." "0,1"
|
|
bitfld.long 0x00 6. " SLOWDOWN_EN ,Slowdown enable." "0,1"
|
|
bitfld.long 0x00 5. " AFLU_PSEL ,auto flush pixel select." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 3. " CKEY_EN ,color key enable." "0,1"
|
|
bitfld.long 0x00 2. " G_ALPHA_EN ,Globl Alpha enable." "0,1"
|
|
bitfld.long 0x00 1. " CROP_EN ,crop enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SF_EN ,surface enable." "0,1"
|
|
group ad:0xF0608094++0x03
|
|
line.long 0x00 "MLC_SF_H_SPOS_S_3,Surface h position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " H ,h positon."
|
|
group ad:0xF0608098++0x03
|
|
line.long 0x00 "MLC_SF_V_SPOS_S_3,Surface v position"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " V ,v position."
|
|
group ad:0xF060809C++0x03
|
|
line.long 0x00 "MLC_SF_SIZE_S_3,Surface size."
|
|
hexmask.long.word 0x00 16.--31. 1. " V ,v size"
|
|
hexmask.long.word 0x00 0.--15. 1. " H ,h size."
|
|
group ad:0xF06080A0++0x03
|
|
line.long 0x00 "MLC_SF_CROP_H_POS_S_3,Surface crop h position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop h end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop h start position"
|
|
group ad:0xF06080A4++0x03
|
|
line.long 0x00 "MLC_SF_CROP_V_POS_S_3,Surface crop v position."
|
|
hexmask.long.word 0x00 16.--31. 1. " END ,crop v end position."
|
|
hexmask.long.word 0x00 0.--15. 1. " START ,crop v start position"
|
|
group ad:0xF06080A8++0x03
|
|
line.long 0x00 "MLC_SF_G_ALPHA_S_3,Surface globl alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,Globl alpha"
|
|
group ad:0xF06080AC++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_ALPHA_S_3,Surface color key alpha."
|
|
hexmask.long.byte 0x00 0.--7. 1. " A ,color key alpha"
|
|
group ad:0xF06080B0++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_R_LV_S_3,R channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,down level."
|
|
group ad:0xF06080B4++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_G_LV_S_3,g channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF06080B8++0x03
|
|
line.long 0x00 "MLC_SF_CKEY_B_LV_S_3,b channel color key low level"
|
|
hexmask.long.word 0x00 16.--25. 1. " UP ,up level."
|
|
hexmask.long.word 0x00 0.--9. 1. " DN ,low level."
|
|
group ad:0xF06080BC++0x03
|
|
line.long 0x00 "MLC_SF_AFLU_TIME_S_3,auto flush time."
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,auto-flush time setting bit[31:16]=current layer's blank time counted by MLC clock cycles {bit[15:1],1'b0}=time-out time setting counted by MLC clock cycles when bit[0]=0 and MLC_SF_CTRL_3.AFLU_EN=0, DIsable flush timer, in .."
|
|
group ad:0xF0608200++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_S_0,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0608204++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_S_1,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0608208++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_S_2,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF060820C++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_S_3,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0608210++0x03
|
|
line.long 0x00 "MLC_PATH_CTRL_S_4,mlc_path_ctrl"
|
|
bitfld.long 0x00 29. " PMA_EN ,Pre-multiplier alpha enable" "0,1"
|
|
bitfld.long 0x00 16.--19. " ALPHA_BLD_IDX ,Alpha blenDIng src index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LAYER_OUT_IDX ,Layer out index." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0608220++0x03
|
|
line.long 0x00 "MLC_BG_CTRL_S,mlc back groud layer and canvas layer control."
|
|
hexmask.long.byte 0x00 8.--15. 1. " BG_A ,Back ground layer Alpha."
|
|
bitfld.long 0x00 7. " AFLU_EN ,Auto flush enable." "0,1"
|
|
bitfld.long 0x00 4.--6. " FSTART_SEL ,fs frame start select." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " BG_A_SEL ,back ground layer alpha select." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "BG_EN ,back ground layer enable." "0,1"
|
|
bitfld.long 0x00 0. " ALPHA_BLD_BYPS ,alpha blenDIng bypass." "0,1"
|
|
group ad:0xF0608224++0x03
|
|
line.long 0x00 "MLC_BG_COLOR_S,MLC Back ground color."
|
|
hexmask.long.word 0x00 20.--29. 1. " R ,R channel color."
|
|
hexmask.long.word 0x00 10.--19. 1. " G ,G channel color."
|
|
hexmask.long.word 0x00 0.--9. 1. " B ,B channel color."
|
|
group ad:0xF0608228++0x03
|
|
line.long 0x00 "MLC_BG_AFLU_TIME_S,BG auto flush time"
|
|
hexmask.long 0x00 0.--31. 1. " TIMER ,not used"
|
|
group ad:0xF0608230++0x03
|
|
line.long 0x00 "MLC_CANVAS_COLOR_S,MLC Canvas color."
|
|
hexmask.long.word 0x00 20.--29. 1. " R ,R channel color."
|
|
hexmask.long.word 0x00 10.--19. 1. " G ,G channel color."
|
|
hexmask.long.word 0x00 0.--9. 1. " B ,B channel color."
|
|
group ad:0xF0608234++0x03
|
|
line.long 0x00 "MLC_CLK_RATIO_S,Ratio of dsp_clk and pix_clk period."
|
|
hexmask.long.word 0x00 0.--15. 1. " RATIO ,(int) ((TCON clock period/MLC clock period)*2^12)"
|
|
group ad:0xF0608240++0x03
|
|
line.long 0x00 "MLC_INT_MASK_S,MLC interrupt mask."
|
|
bitfld.long 0x00 12. " ERR_LAYER_5 ,MCL Layer5 Error(For DC reserved.)" "0,1"
|
|
bitfld.long 0x00 11. " ERR_LAYER_4 ,MCL Layer4 Error(For DC reserved.)" "0,1"
|
|
bitfld.long 0x00 10. " ERR_LAYER_3 ,MCL Layer3 Error(For DC, DP layer.)" "0,1"
|
|
bitfld.long 0x00 9. " ERR_LAYER_2 ,MCL Layer2 Error(gp)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "ERR_LAYER_1 ,MCL Layer1 Error(sp)" "0,1"
|
|
bitfld.long 0x00 7. " ERR_LAYER_0 ,MCL Layer0 Error(BG, for the DC reserved.)" "0,1"
|
|
bitfld.long 0x00 6. " FLU_LAYER_5 ,MCL Layer5 flsah(For DC reserved.)" "0,1"
|
|
bitfld.long 0x00 5. " FLU_LAYER_4 ,MCL Layer4 flsah(For the DC reserved)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FLU_LAYER_3 ,MCL Layer3 flsah(For the DC DP layer.)" "0,1"
|
|
bitfld.long 0x00 3. " FLU_LAYER_2 ,MCL Layer2 flsah(GP)" "0,1"
|
|
bitfld.long 0x00 2. " FLU_LAYER_1 ,MCL Layer1 flsah(SP)" "0,1"
|
|
bitfld.long 0x00 1. " FLU_LAYER_0 ,MCL Layer0 flsah(BG layer, for DC, reserved.)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FRM_END ,MCL frame end" "0,1"
|
|
group ad:0xF0608244++0x03
|
|
line.long 0x00 "MLC_INT_STATUS_S,MLC interrupt status."
|
|
bitfld.long 0x00 27. " SLOWD_LAYER_5 ,slow down layer 5." "0,1"
|
|
bitfld.long 0x00 26. " SLOWD_LAYER_4 ,slow down layer 4." "0,1"
|
|
bitfld.long 0x00 25. " SLOWD_LAYER_3 ,slow down layer 3." "0,1"
|
|
bitfld.long 0x00 24. " SLOWD_LAYER_2 ,slow down layer 2." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "SLOWD_LAYER_1 ,slow down layer 1." "0,1"
|
|
bitfld.long 0x00 22. " SLOWD_LAYER_0 ,slow down layer 0." "0,1"
|
|
bitfld.long 0x00 21. " CROP_ERR_LAYER_5 ,crop position error." "0,1"
|
|
bitfld.long 0x00 20. " CROP_ERR_LAYER_4 ,crop position error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CROP_ERR_LAYER_3 ,crop position error." "0,1"
|
|
bitfld.long 0x00 18. " CROP_ERR_LAYER_2 ,crop position error." "0,1"
|
|
bitfld.long 0x00 17. " CROP_ERR_LAYER_1 ,crop position error." "0,1"
|
|
bitfld.long 0x00 16. " CROP_ERR_LAYER_0 ,crop position error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. "ERR_LAYER_5 ,MLC Layer5Error." "0,1"
|
|
bitfld.long 0x00 11. " ERR_LAYER_4 ,MLC Layer4Error." "0,1"
|
|
bitfld.long 0x00 10. " ERR_LAYER_3 ,MLC Layer3Error." "0,1"
|
|
bitfld.long 0x00 9. " ERR_LAYER_2 ,MLC Layer2Error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "ERR_LAYER_1 ,MLC Layer1 Error." "0,1"
|
|
bitfld.long 0x00 7. " ERR_LAYER_0 ,MLC Layer0 Error." "0,1"
|
|
bitfld.long 0x00 6. " FLU_LAYER_5 ,MCL Layer45flsah(BG layer, For DC reserved.)" "0,1"
|
|
bitfld.long 0x00 5. " FLU_LAYER_4 ,MCL Layer4 flsah(For the DC reserved)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "FLU_LAYER_3 ,MCL Layer3 flsah(For the DC reserved)" "0,1"
|
|
bitfld.long 0x00 3. " FLU_LAYER_2 ,MCL Layer2 flsah(For the DC DP layer)" "0,1"
|
|
bitfld.long 0x00 2. " FLU_LAYER_1 ,MCL Layer1 flsah(GP)" "0,1"
|
|
bitfld.long 0x00 1. " FLU_LAYER_0 ,MCL Layer0 flsah(SP)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FRM_END ,MCL frame end" "0,1"
|
|
group ad:0xF0609000++0x03
|
|
line.long 0x00 "TCON_H_PARA_1,tcon parameter."
|
|
hexmask.long.word 0x00 16.--31. 1. " HACT ,Horizontal active size in pixels. Real size minus 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " HTOL ,Total horizontal size in pixels.Real size minus 1"
|
|
group ad:0xF0609004++0x03
|
|
line.long 0x00 "TCON_H_PARA_2,tcon parameter."
|
|
hexmask.long.word 0x00 16.--31. 1. " HSBP ,Horizontal back porch size in pixels.Real value minus 1."
|
|
hexmask.long.word 0x00 0.--15. 1. " HSYNC ,width of hsync pulse in pixels.Real value minus 1."
|
|
group ad:0xF0609008++0x03
|
|
line.long 0x00 "TCON_V_PARA_1,tcon parameter."
|
|
hexmask.long.word 0x00 16.--31. 1. " VACT ,vertical active size in lines.Real value minus 1."
|
|
hexmask.long.word 0x00 0.--15. 1. " VTOL ,Total vertical size in lines.Real value minus 1."
|
|
group ad:0xF060900C++0x03
|
|
line.long 0x00 "TCON_V_PARA_2,tcon parameter."
|
|
hexmask.long.word 0x00 16.--31. 1. " VSBP ,vertical back porch size in lines.Real value minus 1."
|
|
hexmask.long.word 0x00 0.--15. 1. " VSYNC ,width of vsync pulse in lines.Real value minus 1."
|
|
group ad:0xF0609010++0x03
|
|
line.long 0x00 "TCON_CTRL,tcon ctrl."
|
|
bitfld.long 0x00 6.--7. " PIX_SCR ,tcon pixel data source : 0: MLC 1: BG 2: Canvas 3: Reserved." "0,1,2,3"
|
|
bitfld.long 0x00 5. " DSP_CLK_EN ,DIplay clock output enable." "0,1"
|
|
bitfld.long 0x00 4. " DSP_CLK_POL ,clock output polarity." "0,1"
|
|
bitfld.long 0x00 3. " DE_POL ,de output polarity." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "VSYNC_POL ,vsync output polarity" "0,1"
|
|
bitfld.long 0x00 1. " HSYNC_POL ,Hsyc output polarity." "0,1"
|
|
bitfld.long 0x00 0. " EN ,tcon enable." "0,1"
|
|
group ad:0xF0609020++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_0,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF0609024++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_0,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609028++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_1,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF060902C++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_1,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609030++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_2,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF0609034++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_2,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609038++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_3,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF060903C++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_3,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609040++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_4,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF0609044++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_4,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609048++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_5,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF060904C++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_5,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609050++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_6,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF0609054++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_6,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609058++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_7,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF060905C++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_7,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609060++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_8,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF0609064++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_8,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609068++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_9,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF060906C++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_9,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609070++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_10,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF0609074++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_10,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609078++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_11,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF060907C++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_11,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609080++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_12,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF0609084++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_12,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609088++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_13,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF060908C++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_13,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609090++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_14,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF0609094++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_14,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609098++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_15,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF060909C++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_15,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF06090A0++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_16,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF06090A4++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_16,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF06090A8++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_17,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF06090AC++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_17,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF06090B0++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_COOR_18,TCON_layer_kick_coorDInate"
|
|
hexmask.long.word 0x00 16.--31. 1. " Y ,Layer kick y coorDInate."
|
|
hexmask.long.word 0x00 0.--15. 1. " X ,Layer kick x coorDInate."
|
|
group ad:0xF06090B4++0x03
|
|
line.long 0x00 "TCON_LAYER_KICK_EN_18,TCON_layer_kick_en"
|
|
bitfld.long 0x00 0. " ENABLE ,Layer kick enable" "0,1"
|
|
group ad:0xF0609100++0x03
|
|
line.long 0x00 "TCON_UNDERRUN_CNT,TCON_underrun_cnt status."
|
|
hexmask.long 0x00 0.--31. 1. " STATUS ,TCON_underrun_cnt status."
|
|
group ad:0xF0609400++0x03
|
|
line.long 0x00 "TCON_POST_CTRL,Tcon post control register."
|
|
bitfld.long 0x00 1. " EN ,select the tcon output signal source: 0: from tcon. 1: from tcon_post." "0,1"
|
|
bitfld.long 0x00 0. " SYNC_SCR ,source select. 0: hlast & vlast will trig the post count. 1: Hsyn /Vsyn will trig post count start." "0,1"
|
|
group ad:0xF0609410++0x03
|
|
line.long 0x00 "TCON_POST_CH_CTRL_0,Tcon post channel control."
|
|
bitfld.long 0x00 3. " OUT_MODE ,channel output mode. 0: No any operation. 1: AND previous channel ." "0,1"
|
|
bitfld.long 0x00 2. " OUT_SCR ,channel output source select. 0: pixel count. 1: line count." "0,1"
|
|
bitfld.long 0x00 1. " OUT_POL ,channel output polarity." "0,1"
|
|
bitfld.long 0x00 0. " OUT_EN ,channel output enable." "0,1"
|
|
group ad:0xF0609414++0x03
|
|
line.long 0x00 "TCON_POST_CH_CTRL_1,Tcon post channel control."
|
|
bitfld.long 0x00 3. " OUT_MODE ,channel output mode. 0: No any operation. 1: AND previous channel ." "0,1"
|
|
bitfld.long 0x00 2. " OUT_SCR ,channel output source select. 0: pixel count. 1: line count." "0,1"
|
|
bitfld.long 0x00 1. " OUT_POL ,channel output polarity." "0,1"
|
|
bitfld.long 0x00 0. " OUT_EN ,channel output enable." "0,1"
|
|
group ad:0xF0609418++0x03
|
|
line.long 0x00 "TCON_POST_CH_CTRL_2,Tcon post channel control."
|
|
bitfld.long 0x00 3. " OUT_MODE ,channel output mode. 0: No any operation. 1: AND previous channel ." "0,1"
|
|
bitfld.long 0x00 2. " OUT_SCR ,channel output source select. 0: pixel count. 1: line count." "0,1"
|
|
bitfld.long 0x00 1. " OUT_POL ,channel output polarity." "0,1"
|
|
bitfld.long 0x00 0. " OUT_EN ,channel output enable." "0,1"
|
|
group ad:0xF060941C++0x03
|
|
line.long 0x00 "TCON_POST_CH_CTRL_3,Tcon post channel control."
|
|
bitfld.long 0x00 3. " OUT_MODE ,channel output mode. 0: No any operation. 1: AND previous channel ." "0,1"
|
|
bitfld.long 0x00 2. " OUT_SCR ,channel output source select. 0: pixel count. 1: line count." "0,1"
|
|
bitfld.long 0x00 1. " OUT_POL ,channel output polarity." "0,1"
|
|
bitfld.long 0x00 0. " OUT_EN ,channel output enable." "0,1"
|
|
group ad:0xF0609430++0x03
|
|
line.long 0x00 "TCON_POST_POS_0,Tcon post on/off position ."
|
|
hexmask.long.word 0x00 16.--31. 1. " OFF ,OFF position."
|
|
hexmask.long.word 0x00 0.--15. 1. " ON ,ON position ."
|
|
group ad:0xF0609434++0x03
|
|
line.long 0x00 "TCON_POST_POS_1,Tcon post on/off position ."
|
|
hexmask.long.word 0x00 16.--31. 1. " OFF ,OFF position."
|
|
hexmask.long.word 0x00 0.--15. 1. " ON ,ON position ."
|
|
group ad:0xF0609438++0x03
|
|
line.long 0x00 "TCON_POST_POS_2,Tcon post on/off position ."
|
|
hexmask.long.word 0x00 16.--31. 1. " OFF ,OFF position."
|
|
hexmask.long.word 0x00 0.--15. 1. " ON ,ON position ."
|
|
group ad:0xF060943C++0x03
|
|
line.long 0x00 "TCON_POST_POS_3,Tcon post on/off position ."
|
|
hexmask.long.word 0x00 16.--31. 1. " OFF ,OFF position."
|
|
hexmask.long.word 0x00 0.--15. 1. " ON ,ON position ."
|
|
group ad:0xF0609500++0x03
|
|
line.long 0x00 "TCON_CSI_FRAM_LOCK_CTRL,Tcon CSI frame lock control register."
|
|
hexmask.long.word 0x00 16.--31. 1. " TCON_DE_DLY ,Data enable Delay between CSI and TCON."
|
|
bitfld.long 0x00 8. " AUTO_ADJ_EN ,Auto adjust enable." "0,1"
|
|
bitfld.long 0x00 4.--5. " FRM_RATIO ,CSI frame rate : DIsplay frame rate 00: 1:1 01: 1:2 10: 1:3 11: 1:4" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " VS_MASK ,VS mask signal: 00: no mask. 01: mask 1 frame. 10: mask 2 frame. 11: mask 3 frame." "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1. "VS_POL ,Vsync polarity." "0,1"
|
|
bitfld.long 0x00 0. " HS_POL ,Hsync polarity" "0,1"
|
|
group ad:0xF0609504++0x03
|
|
line.long 0x00 "TCON_CSI_TIMING_DETECT,Tcon CSI frame Timing detect enable."
|
|
bitfld.long 0x00 0. " EN ,CSI timing detection enable." "0,1"
|
|
group ad:0xF0609510++0x03
|
|
line.long 0x00 "CSI_HTOL,CSI h-total. (unit : pixel)"
|
|
hexmask.long 0x00 0.--31. 1. " HTOL ,csi Htol."
|
|
group ad:0xF0609514++0x03
|
|
line.long 0x00 "CSI_VTOL,CSI v-total. (unit : pixel)"
|
|
hexmask.long 0x00 0.--31. 1. " VTOL ,csi vtol"
|
|
group ad:0xF0609518++0x03
|
|
line.long 0x00 "CSI_VSBP,CSI vsbp. (unit : pixel)"
|
|
hexmask.long 0x00 0.--31. 1. " VSBP ,csi vsbp"
|
|
group ad:0xF060951C++0x03
|
|
line.long 0x00 "CSI_VSYNC,CSI csi_vsync. (unit : pixel)"
|
|
hexmask.long 0x00 0.--31. 1. " VSYNC ,CSI Vsync."
|
|
group ad:0xF0609520++0x03
|
|
line.long 0x00 "VSYNC_CNT,The Delay line between CSI Vsync and TCOn Vsync."
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,The Delay line between CSI Vsync and TCOn Vsync."
|
|
group ad:0xF0609600++0x03
|
|
line.long 0x00 "TCON_SDW_EN,Tcon sdw enable."
|
|
bitfld.long 0x00 0. " EN ,Tcon sdw enable." "0,1"
|
|
group ad:0xF060A000++0x03
|
|
line.long 0x00 "DC_CSC_CTRL_0,CSC control register."
|
|
bitfld.long 0x00 2. " ALPHA ,0: {alpha, pixel}, 1: {pixel, alpha};" "0,1"
|
|
bitfld.long 0x00 1. " SBUP_CONV ,0: p2,p1,p0, 1: p0,p1,p2" "0,1"
|
|
bitfld.long 0x00 0. " BYPASS ,CSC bypss" "0,1"
|
|
group ad:0xF060A004++0x03
|
|
line.long 0x00 "DC_CSC_COEF1_0,csc coef."
|
|
hexmask.long.word 0x00 16.--29. 1. " A01 ,a01"
|
|
hexmask.long.word 0x00 0.--13. 1. " A00 ,a00"
|
|
group ad:0xF060A008++0x03
|
|
line.long 0x00 "DC_CSC_COEF2_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " A10 ,a10"
|
|
hexmask.long.word 0x00 0.--13. 1. " A02 ,a02"
|
|
group ad:0xF060A00C++0x03
|
|
line.long 0x00 "DC_CSC_COEF3_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " A12 ,a12"
|
|
hexmask.long.word 0x00 0.--13. 1. " A11 ,a11"
|
|
group ad:0xF060A010++0x03
|
|
line.long 0x00 "DC_CSC_COEF4_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " A21 ,a21"
|
|
hexmask.long.word 0x00 0.--13. 1. " A20 ,a20"
|
|
group ad:0xF060A014++0x03
|
|
line.long 0x00 "DC_CSC_COEF5_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " B0 ,b0"
|
|
hexmask.long.word 0x00 0.--13. 1. " A22 ,a22"
|
|
group ad:0xF060A018++0x03
|
|
line.long 0x00 "DC_CSC_COEF6_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " B2 ,b2"
|
|
hexmask.long.word 0x00 0.--13. 1. " B1 ,b1"
|
|
group ad:0xF060A01C++0x03
|
|
line.long 0x00 "DC_CSC_COEF7_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--25. 1. " C1 ,c1"
|
|
hexmask.long.word 0x00 0.--9. 1. " C0 ,c0"
|
|
group ad:0xF060A020++0x03
|
|
line.long 0x00 "DC_CSC_COEF8_0,dc_csc_coef"
|
|
hexmask.long.word 0x00 0.--9. 1. " C2 ,c2"
|
|
group ad:0xF060B000++0x03
|
|
line.long 0x00 "DC_CSC_CTRL_1,CSC control register."
|
|
bitfld.long 0x00 2. " ALPHA ,0: {alpha, pixel}, 1: {pixel, alpha};" "0,1"
|
|
bitfld.long 0x00 1. " SBUP_CONV ,0: p2,p1,p0, 1: p0,p1,p2" "0,1"
|
|
bitfld.long 0x00 0. " BYPASS ,CSC bypss" "0,1"
|
|
group ad:0xF060B004++0x03
|
|
line.long 0x00 "DC_CSC_COEF1_1,csc coef."
|
|
hexmask.long.word 0x00 16.--29. 1. " A01 ,a01"
|
|
hexmask.long.word 0x00 0.--13. 1. " A00 ,a00"
|
|
group ad:0xF060B008++0x03
|
|
line.long 0x00 "DC_CSC_COEF2_1,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " A10 ,a10"
|
|
hexmask.long.word 0x00 0.--13. 1. " A02 ,a02"
|
|
group ad:0xF060B00C++0x03
|
|
line.long 0x00 "DC_CSC_COEF3_1,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " A12 ,a12"
|
|
hexmask.long.word 0x00 0.--13. 1. " A11 ,a11"
|
|
group ad:0xF060B010++0x03
|
|
line.long 0x00 "DC_CSC_COEF4_1,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " A21 ,a21"
|
|
hexmask.long.word 0x00 0.--13. 1. " A20 ,a20"
|
|
group ad:0xF060B014++0x03
|
|
line.long 0x00 "DC_CSC_COEF5_1,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " B0 ,b0"
|
|
hexmask.long.word 0x00 0.--13. 1. " A22 ,a22"
|
|
group ad:0xF060B018++0x03
|
|
line.long 0x00 "DC_CSC_COEF6_1,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--29. 1. " B2 ,b2"
|
|
hexmask.long.word 0x00 0.--13. 1. " B1 ,b1"
|
|
group ad:0xF060B01C++0x03
|
|
line.long 0x00 "DC_CSC_COEF7_1,dc_csc_coef"
|
|
hexmask.long.word 0x00 16.--25. 1. " C1 ,c1"
|
|
hexmask.long.word 0x00 0.--9. 1. " C0 ,c0"
|
|
group ad:0xF060B020++0x03
|
|
line.long 0x00 "DC_CSC_COEF8_1,dc_csc_coef"
|
|
hexmask.long.word 0x00 0.--9. 1. " C2 ,c2"
|
|
group ad:0xF060C000++0x03
|
|
line.long 0x00 "GAMMA_CTRL,gamma ctrl register."
|
|
hexmask.long.byte 0x00 8.--15. 1. " APB_RD_TO ,APB read time out setting."
|
|
bitfld.long 0x00 0. " BYPASS ,gamma bypass." "0,1"
|
|
group ad:0xF060C004++0x03
|
|
line.long 0x00 "DITHER_CTRL,DIther ctrl register."
|
|
bitfld.long 0x00 16.--19. " V_DEP ,v dep." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " U_DEP ,u dep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " Y_DEP ,Y dep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " MODE_12 ,DIther input 12 bit or not." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "SPA_LSB_EXP_MODE ,SPA DIther LSB generation mode." "0,1,2,3"
|
|
bitfld.long 0x00 3. " SPA_1ST ,Spa DIther first." "0,1"
|
|
bitfld.long 0x00 2. " SPA_EN ,spatial DIther enable." "0,1"
|
|
bitfld.long 0x00 1. " TEM_EN ,Temporal DIther enale." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "BYPASS ,DIther bypass." "0,1"
|
|
group ad:0xF060E000++0x03
|
|
line.long 0x00 "CRC32_CTRL,crc32 ctrl register"
|
|
bitfld.long 0x00 9. " VSYNC_POL ,vsync polarity" "0,1"
|
|
bitfld.long 0x00 8. " HSYNC_POL ,hsync polarity" "0,1"
|
|
bitfld.long 0x00 7. " DATA_EN_POL ,data_en polarity" "0,1"
|
|
bitfld.long 0x00 0. " GLOBAL_ENABLE ,global enable" "0,1"
|
|
group ad:0xF060E004++0x03
|
|
line.long 0x00 "CRC32_INT_ST,crc32 interrupt status"
|
|
bitfld.long 0x00 15. " CRC_ERROR_7 ,crc error" "0,1"
|
|
bitfld.long 0x00 14. " CRC_ERROR_6 ,crc error" "0,1"
|
|
bitfld.long 0x00 13. " CRC_ERROR_5 ,crc error" "0,1"
|
|
bitfld.long 0x00 12. " CRC_ERROR_4 ,crc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CRC_ERROR_3 ,crc error" "0,1"
|
|
bitfld.long 0x00 10. " CRC_ERROR_2 ,crc error" "0,1"
|
|
bitfld.long 0x00 9. " CRC_ERROR_1 ,crc error" "0,1"
|
|
bitfld.long 0x00 8. " CRC_ERROR_0 ,crc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CRC_DONE_7 ,crc done" "0,1"
|
|
bitfld.long 0x00 6. " CRC_DONE_6 ,crc done" "0,1"
|
|
bitfld.long 0x00 5. " CRC_DONE_5 ,crc done" "0,1"
|
|
bitfld.long 0x00 4. " CRC_DONE_4 ,crc done" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CRC_DONE_3 ,crc done" "0,1"
|
|
bitfld.long 0x00 2. " CRC_DONE_2 ,crc done" "0,1"
|
|
bitfld.long 0x00 1. " CRC_DONE_1 ,crc done" "0,1"
|
|
bitfld.long 0x00 0. " CRC_DONE_0 ,crc done" "0,1"
|
|
group ad:0xF060E008++0x03
|
|
line.long 0x00 "CRC32_INT_MASK,crc32 interrupt enable."
|
|
hexmask.long.byte 0x00 8.--15. 1. " CRC_ERROR ,crc error"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CRC_DONE ,crc done"
|
|
group ad:0xF060E010++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL0_0,crc32 block control0"
|
|
bitfld.long 0x00 31. " ENABLE ,block enable" "0,1"
|
|
bitfld.long 0x00 30. " LOCK ,LOCK enable" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_START_Y ,position start y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_START_X ,position start x"
|
|
group ad:0xF060E014++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL1_0,crc32 block control1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_END_Y ,end position y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_END_X ,end position x"
|
|
group ad:0xF060E018++0x03
|
|
line.long 0x00 "CRC32_BLOCK_EXPECT_DATA_0,crc32 block expect data"
|
|
hexmask.long 0x00 0.--31. 1. " EXPECT_DATA ,expect data"
|
|
group ad:0xF060E01C++0x03
|
|
line.long 0x00 "CRC32_BLOCK_RESULT_DATA_0,crc32 block result data"
|
|
hexmask.long 0x00 0.--31. 1. " RESULT_DATA ,result data"
|
|
group ad:0xF060E030++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL0_1,crc32 block control0"
|
|
bitfld.long 0x00 31. " ENABLE ,block enable" "0,1"
|
|
bitfld.long 0x00 30. " LOCK ,LOCK enable" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_START_Y ,position start y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_START_X ,position start x"
|
|
group ad:0xF060E034++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL1_1,crc32 block control1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_END_Y ,end position y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_END_X ,end position x"
|
|
group ad:0xF060E038++0x03
|
|
line.long 0x00 "CRC32_BLOCK_EXPECT_DATA_1,crc32 block expect data"
|
|
hexmask.long 0x00 0.--31. 1. " EXPECT_DATA ,expect data"
|
|
group ad:0xF060E03C++0x03
|
|
line.long 0x00 "CRC32_BLOCK_RESULT_DATA_1,crc32 block result data"
|
|
hexmask.long 0x00 0.--31. 1. " RESULT_DATA ,result data"
|
|
group ad:0xF060E050++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL0_2,crc32 block control0"
|
|
bitfld.long 0x00 31. " ENABLE ,block enable" "0,1"
|
|
bitfld.long 0x00 30. " LOCK ,LOCK enable" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_START_Y ,position start y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_START_X ,position start x"
|
|
group ad:0xF060E054++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL1_2,crc32 block control1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_END_Y ,end position y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_END_X ,end position x"
|
|
group ad:0xF060E058++0x03
|
|
line.long 0x00 "CRC32_BLOCK_EXPECT_DATA_2,crc32 block expect data"
|
|
hexmask.long 0x00 0.--31. 1. " EXPECT_DATA ,expect data"
|
|
group ad:0xF060E05C++0x03
|
|
line.long 0x00 "CRC32_BLOCK_RESULT_DATA_2,crc32 block result data"
|
|
hexmask.long 0x00 0.--31. 1. " RESULT_DATA ,result data"
|
|
group ad:0xF060E070++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL0_3,crc32 block control0"
|
|
bitfld.long 0x00 31. " ENABLE ,block enable" "0,1"
|
|
bitfld.long 0x00 30. " LOCK ,LOCK enable" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_START_Y ,position start y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_START_X ,position start x"
|
|
group ad:0xF060E074++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL1_3,crc32 block control1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_END_Y ,end position y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_END_X ,end position x"
|
|
group ad:0xF060E078++0x03
|
|
line.long 0x00 "CRC32_BLOCK_EXPECT_DATA_3,crc32 block expect data"
|
|
hexmask.long 0x00 0.--31. 1. " EXPECT_DATA ,expect data"
|
|
group ad:0xF060E07C++0x03
|
|
line.long 0x00 "CRC32_BLOCK_RESULT_DATA_3,crc32 block result data"
|
|
hexmask.long 0x00 0.--31. 1. " RESULT_DATA ,result data"
|
|
group ad:0xF060E090++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL0_4,crc32 block control0"
|
|
bitfld.long 0x00 31. " ENABLE ,block enable" "0,1"
|
|
bitfld.long 0x00 30. " LOCK ,LOCK enable" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_START_Y ,position start y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_START_X ,position start x"
|
|
group ad:0xF060E094++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL1_4,crc32 block control1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_END_Y ,end position y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_END_X ,end position x"
|
|
group ad:0xF060E098++0x03
|
|
line.long 0x00 "CRC32_BLOCK_EXPECT_DATA_4,crc32 block expect data"
|
|
hexmask.long 0x00 0.--31. 1. " EXPECT_DATA ,expect data"
|
|
group ad:0xF060E09C++0x03
|
|
line.long 0x00 "CRC32_BLOCK_RESULT_DATA_4,crc32 block result data"
|
|
hexmask.long 0x00 0.--31. 1. " RESULT_DATA ,result data"
|
|
group ad:0xF060E0B0++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL0_5,crc32 block control0"
|
|
bitfld.long 0x00 31. " ENABLE ,block enable" "0,1"
|
|
bitfld.long 0x00 30. " LOCK ,LOCK enable" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_START_Y ,position start y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_START_X ,position start x"
|
|
group ad:0xF060E0B4++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL1_5,crc32 block control1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_END_Y ,end position y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_END_X ,end position x"
|
|
group ad:0xF060E0B8++0x03
|
|
line.long 0x00 "CRC32_BLOCK_EXPECT_DATA_5,crc32 block expect data"
|
|
hexmask.long 0x00 0.--31. 1. " EXPECT_DATA ,expect data"
|
|
group ad:0xF060E0BC++0x03
|
|
line.long 0x00 "CRC32_BLOCK_RESULT_DATA_5,crc32 block result data"
|
|
hexmask.long 0x00 0.--31. 1. " RESULT_DATA ,result data"
|
|
group ad:0xF060E0D0++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL0_6,crc32 block control0"
|
|
bitfld.long 0x00 31. " ENABLE ,block enable" "0,1"
|
|
bitfld.long 0x00 30. " LOCK ,LOCK enable" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_START_Y ,position start y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_START_X ,position start x"
|
|
group ad:0xF060E0D4++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL1_6,crc32 block control1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_END_Y ,end position y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_END_X ,end position x"
|
|
group ad:0xF060E0D8++0x03
|
|
line.long 0x00 "CRC32_BLOCK_EXPECT_DATA_6,crc32 block expect data"
|
|
hexmask.long 0x00 0.--31. 1. " EXPECT_DATA ,expect data"
|
|
group ad:0xF060E0DC++0x03
|
|
line.long 0x00 "CRC32_BLOCK_RESULT_DATA_6,crc32 block result data"
|
|
hexmask.long 0x00 0.--31. 1. " RESULT_DATA ,result data"
|
|
group ad:0xF060E0F0++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL0_7,crc32 block control0"
|
|
bitfld.long 0x00 31. " ENABLE ,block enable" "0,1"
|
|
bitfld.long 0x00 30. " LOCK ,LOCK enable" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_START_Y ,position start y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_START_X ,position start x"
|
|
group ad:0xF060E0F4++0x03
|
|
line.long 0x00 "CRC32_BLOCK_CTRL1_7,crc32 block control1"
|
|
hexmask.long.word 0x00 16.--29. 1. " POS_END_Y ,end position y"
|
|
hexmask.long.word 0x00 0.--13. 1. " POS_END_X ,end position x"
|
|
group ad:0xF060E0F8++0x03
|
|
line.long 0x00 "CRC32_BLOCK_EXPECT_DATA_7,crc32 block expect data"
|
|
hexmask.long 0x00 0.--31. 1. " EXPECT_DATA ,expect data"
|
|
group ad:0xF060E0FC++0x03
|
|
line.long 0x00 "CRC32_BLOCK_RESULT_DATA_7,crc32 block result data"
|
|
hexmask.long 0x00 0.--31. 1. " RESULT_DATA ,result data"
|
|
tree.end
|
|
config 16. 8.
|
|
config 16. 8.
|
|
tree "EIC"
|
|
tree "EIC_SF"
|
|
width 28.
|
|
group ad:0xF0FE0000++0x03
|
|
line.long 0x00 "LOCK,lock enable register"
|
|
bitfld.long 0x00 0. " LOCK ,when LOCK=1'b1,the Enable configure group can only read by APB bus when LOCK=1'b0,the Enable configure group can be read/write by APB bus" "0,1"
|
|
group ad:0xF0FE0100++0x03
|
|
line.long 0x00 "EN_0,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF0FE0104++0x03
|
|
line.long 0x00 "EN_1,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF0FE0108++0x03
|
|
line.long 0x00 "EN_2,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF0FE010C++0x03
|
|
line.long 0x00 "EN_3,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF0FE0200++0x03
|
|
line.long 0x00 "BIT_0,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0204++0x03
|
|
line.long 0x00 "BIT_1,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0208++0x03
|
|
line.long 0x00 "BIT_2,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE020C++0x03
|
|
line.long 0x00 "BIT_3,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0210++0x03
|
|
line.long 0x00 "BIT_4,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0214++0x03
|
|
line.long 0x00 "BIT_5,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0218++0x03
|
|
line.long 0x00 "BIT_6,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE021C++0x03
|
|
line.long 0x00 "BIT_7,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0220++0x03
|
|
line.long 0x00 "BIT_8,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0224++0x03
|
|
line.long 0x00 "BIT_9,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0228++0x03
|
|
line.long 0x00 "BIT_10,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE022C++0x03
|
|
line.long 0x00 "BIT_11,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0230++0x03
|
|
line.long 0x00 "BIT_12,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0234++0x03
|
|
line.long 0x00 "BIT_13,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0238++0x03
|
|
line.long 0x00 "BIT_14,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE023C++0x03
|
|
line.long 0x00 "BIT_15,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0FE0300++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0FE0304++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,status enable" "0,1"
|
|
group ad:0xF0FE0308++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,signal enable" "0,1"
|
|
group ad:0xF0FE030C++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,selftest_mode_p and selftest_mode_n redundant inputs e2e check error occur" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error occur ,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PWDATA_UNCOR_ERR ,Pwdata uncorrectable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0FE0310++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,selftest_mode_p and selftest_mode_n redundant inputs e2e check error status enable" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error status enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error status enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PWDATA_UNCOR_ERR ,Pwdata uncorrectable error status enable" "0,1"
|
|
group ad:0xF0FE0314++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,selftest_mode_p and selftest_mode_n redundant inputs e2e check error signal enable" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error signal enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error signal enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PWDATA_UNCOR_ERR ,Pwdata uncorrectable error signal enable" "0,1"
|
|
group ad:0xF0FE0318++0x03
|
|
line.long 0x00 "PWDATA,pwdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,error injection on pwdata"
|
|
group ad:0xF0FE031C++0x03
|
|
line.long 0x00 "PWCODE,pwcode error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INJ ,error injection on pwcode"
|
|
group ad:0xF0FE0320++0x03
|
|
line.long 0x00 "INT_ERR,interrupt error injection"
|
|
bitfld.long 0x00 1. " FUSA_UNCOR_INJ ,apb bus uncorrectable error and input error injection" "0,1"
|
|
bitfld.long 0x00 0. " FUSA_COR_INJ ,pwdata correctable interruput error injection" "0,1"
|
|
group ad:0xF0FE0324++0x03
|
|
line.long 0x00 "SELFTEST_MODE,enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,selftest mode enable" "0,1"
|
|
group ad:0xF0FE0328++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
group ad:0xF0FE032C++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
group ad:0xF0FE0330++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
group ad:0xF0FE0334++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
tree.end
|
|
tree "EIC_BOOT"
|
|
width 28.
|
|
group ad:0xF0720000++0x03
|
|
line.long 0x00 "LOCK,lock enable register"
|
|
bitfld.long 0x00 0. " LOCK ,when LOCK=1'b1,the Enable configure group can only read by APB bus when LOCK=1'b0,the Enable configure group can be read/write by APB bus" "0,1"
|
|
group ad:0xF0720100++0x03
|
|
line.long 0x00 "EN_0,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF0720104++0x03
|
|
line.long 0x00 "EN_1,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF0720108++0x03
|
|
line.long 0x00 "EN_2,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF072010C++0x03
|
|
line.long 0x00 "EN_3,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF0720200++0x03
|
|
line.long 0x00 "BIT_0,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720204++0x03
|
|
line.long 0x00 "BIT_1,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720208++0x03
|
|
line.long 0x00 "BIT_2,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF072020C++0x03
|
|
line.long 0x00 "BIT_3,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720210++0x03
|
|
line.long 0x00 "BIT_4,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720214++0x03
|
|
line.long 0x00 "BIT_5,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720218++0x03
|
|
line.long 0x00 "BIT_6,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF072021C++0x03
|
|
line.long 0x00 "BIT_7,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720220++0x03
|
|
line.long 0x00 "BIT_8,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720224++0x03
|
|
line.long 0x00 "BIT_9,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720228++0x03
|
|
line.long 0x00 "BIT_10,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF072022C++0x03
|
|
line.long 0x00 "BIT_11,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720230++0x03
|
|
line.long 0x00 "BIT_12,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720234++0x03
|
|
line.long 0x00 "BIT_13,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720238++0x03
|
|
line.long 0x00 "BIT_14,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF072023C++0x03
|
|
line.long 0x00 "BIT_15,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF0720300++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0720304++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,status enable" "0,1"
|
|
group ad:0xF0720308++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,signal enable" "0,1"
|
|
group ad:0xF072030C++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,selftest_mode_p and selftest_mode_n redundant inputs e2e check error occur" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error occur ,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PWDATA_UNCOR_ERR ,Pwdata uncorrectable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF0720310++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,selftest_mode_p and selftest_mode_n redundant inputs e2e check error status enable" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error status enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error status enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PWDATA_UNCOR_ERR ,Pwdata uncorrectable error status enable" "0,1"
|
|
group ad:0xF0720314++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,selftest_mode_p and selftest_mode_n redundant inputs e2e check error signal enable" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error signal enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error signal enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PWDATA_UNCOR_ERR ,Pwdata uncorrectable error signal enable" "0,1"
|
|
group ad:0xF0720318++0x03
|
|
line.long 0x00 "PWDATA,pwdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,error injection on pwdata"
|
|
group ad:0xF072031C++0x03
|
|
line.long 0x00 "PWCODE,pwcode error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INJ ,error injection on pwcode"
|
|
group ad:0xF0720320++0x03
|
|
line.long 0x00 "INT_ERR,interrupt error injection"
|
|
bitfld.long 0x00 1. " FUSA_UNCOR_INJ ,apb bus uncorrectable error and input error injection" "0,1"
|
|
bitfld.long 0x00 0. " FUSA_COR_INJ ,pwdata correctable interruput error injection" "0,1"
|
|
group ad:0xF0720324++0x03
|
|
line.long 0x00 "SELFTEST_MODE,enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,selftest mode enable" "0,1"
|
|
group ad:0xF0720328++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
group ad:0xF072032C++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
group ad:0xF0720330++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
group ad:0xF0720334++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
tree.end
|
|
tree "EIC_SP"
|
|
width 28.
|
|
group ad:0xF2050000++0x03
|
|
line.long 0x00 "LOCK,lock enable register"
|
|
bitfld.long 0x00 0. " LOCK ,when LOCK=1'b1,the Enable configure group can only read by APB bus when LOCK=1'b0,the Enable configure group can be read/write by APB bus" "0,1"
|
|
group ad:0xF2050100++0x03
|
|
line.long 0x00 "EN_0,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF2050104++0x03
|
|
line.long 0x00 "EN_1,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF2050108++0x03
|
|
line.long 0x00 "EN_2,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF205010C++0x03
|
|
line.long 0x00 "EN_3,block enable configure register"
|
|
hexmask.long 0x00 0.--31. 1. " ENABLE ,error inject enable"
|
|
group ad:0xF2050200++0x03
|
|
line.long 0x00 "BIT_0,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050204++0x03
|
|
line.long 0x00 "BIT_1,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050208++0x03
|
|
line.long 0x00 "BIT_2,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF205020C++0x03
|
|
line.long 0x00 "BIT_3,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050210++0x03
|
|
line.long 0x00 "BIT_4,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050214++0x03
|
|
line.long 0x00 "BIT_5,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050218++0x03
|
|
line.long 0x00 "BIT_6,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF205021C++0x03
|
|
line.long 0x00 "BIT_7,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050220++0x03
|
|
line.long 0x00 "BIT_8,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050224++0x03
|
|
line.long 0x00 "BIT_9,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050228++0x03
|
|
line.long 0x00 "BIT_10,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF205022C++0x03
|
|
line.long 0x00 "BIT_11,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050230++0x03
|
|
line.long 0x00 "BIT_12,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050234++0x03
|
|
line.long 0x00 "BIT_13,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050238++0x03
|
|
line.long 0x00 "BIT_14,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF205023C++0x03
|
|
line.long 0x00 "BIT_15,bit configure register"
|
|
hexmask.long 0x00 0.--31. 1. " BITS ,bits"
|
|
group ad:0xF2050300++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF2050304++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STAT_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,status enable" "0,1"
|
|
group ad:0xF2050308++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,signal enable" "0,1"
|
|
group ad:0xF205030C++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,selftest_mode_p and selftest_mode_n redundant inputs e2e check error occur" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error occur ,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error occur,and you can write 1 to clear it" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error occur,and you can write 1 to clear it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PWDATA_UNCOR_ERR ,Pwdata uncorrectable error occur,and you can write 1 to clear it" "0,1"
|
|
group ad:0xF2050310++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_STAT_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,selftest_mode_p and selftest_mode_n redundant inputs e2e check error status enable" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error status enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error status enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PWDATA_UNCOR_ERR ,Pwdata uncorrectable error status enable" "0,1"
|
|
group ad:0xF2050314++0x03
|
|
line.long 0x00 "FUSA_UNCOR_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " INPUT_ERR ,selftest_mode_p and selftest_mode_n redundant inputs e2e check error signal enable" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNCOR_ERR ,Apb control siganls(pwrite, psel and penable,pstrob[3:0]) parity error signal enable" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNCOR_ERR ,Paddr parity error signal enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_FATAL_ERR ,Pwdata fatal error signal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "PWDATA_UNCOR_ERR ,Pwdata uncorrectable error signal enable" "0,1"
|
|
group ad:0xF2050318++0x03
|
|
line.long 0x00 "PWDATA,pwdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,error injection on pwdata"
|
|
group ad:0xF205031C++0x03
|
|
line.long 0x00 "PWCODE,pwcode error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INJ ,error injection on pwcode"
|
|
group ad:0xF2050320++0x03
|
|
line.long 0x00 "INT_ERR,interrupt error injection"
|
|
bitfld.long 0x00 1. " FUSA_UNCOR_INJ ,apb bus uncorrectable error and input error injection" "0,1"
|
|
bitfld.long 0x00 0. " FUSA_COR_INJ ,pwdata correctable interruput error injection" "0,1"
|
|
group ad:0xF2050324++0x03
|
|
line.long 0x00 "SELFTEST_MODE,enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,selftest mode enable" "0,1"
|
|
group ad:0xF2050328++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
group ad:0xF205032C++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
group ad:0xF2050330++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
group ad:0xF2050334++0x03
|
|
line.long 0x00 "ERR_ENABLE,error enable output e2e error inject"
|
|
hexmask.long 0x00 0.--31. 1. " INJ ,"
|
|
tree.end
|
|
tree.end
|
|
tree "ETIMER"
|
|
tree "ETIMER1"
|
|
width 28.
|
|
group ad:0xF04C0000++0x03
|
|
line.long 0x00 "INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,LCNT_D snapshot event happens" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,LCNT_C snapshot event happens" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,LCNT_B snapshot event happens" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,LCNT_A snapshot event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,CNT_G1 snapshot event happens" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,CNT_G0 snapshot event happens" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,CNT_LOCAL_D overflow" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,CNT_LOCAL_C overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,CNT_LOCAL_B overflow" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,CNT_LOCAL_A overflow" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,CNT_G1 overflow" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,CNT_G0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Compare D event happens" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Compare C event happens" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Compare B event happens" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Compare A event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Capture D event happens" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Capture C event happens" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Capture B event happens" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Capture A event happens" "0,1"
|
|
group ad:0xF04C0004++0x03
|
|
line.long 0x00 "INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Status enable" "0,1"
|
|
group ad:0xF04C0008++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt singal enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Singal enable" "0,1"
|
|
group ad:0xF04C000C++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA,Correctable error interrupt status register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,CPT D vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,CPT C vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,CPT B vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,CPT A vaule is not fetched" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,FIFO D overrun" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,FIFO C overrun" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,FIFO B overrun" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,FIFO A overrun" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04C0010++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA_EN,Correctable error interrupt status enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04C0014++0x03
|
|
line.long 0x00 "COR_ERR_INT_SIG_EN,Correctable error interrupt singal enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04C0018++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA,Uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,CPT D vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,CPT C vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,CPT B vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,CPT A vaule is not fetched" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,FIFO D overrun" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,FIFO C overrun" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,FIFO B overrun" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,FIFO A overrun" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04C001C++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04C0020++0x03
|
|
line.long 0x00 "UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt singal enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04C0024++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata corrctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04C0028++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04C002C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04C0030++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Cock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Cock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error." "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error." "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error." "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04C0034++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04C0038++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error." "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error." "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,CONFIG_DMA eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04C003C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_1,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04C0040++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN_1,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04C0044++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN_1,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,CONFIG_DMA eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04C004C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF04C0050++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF04C0054++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF04C005C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF04C0060++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,RAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04C0064++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04C0068++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,RAM B rdata monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04C006C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,RAM B rdata ECC monitorerror injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04C0070++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF04C0074++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF04C0080++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 16.--18. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF04C0084++0x03
|
|
line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04C0088++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04C008C++0x03
|
|
line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04C0090++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 6. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
|
bitfld.long 0x00 5. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
|
bitfld.long 0x00 4. " CNT_OVF ,Counter overflow and snapshot interrupt error injection." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Channel D interrupt error injection." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CHN_C ,Channel C interrupt error injection." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B ,Channel B interrupt error injection." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Channel A interrupt error injection." "0,1"
|
|
group ad:0xF04C0094++0x03
|
|
line.long 0x00 "CLK_MON_CMP_ERR_INJ,Clock monitor compare error injection r"
|
|
bitfld.long 0x00 2.--3. " ERR1 ,Clock monitor 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ERR0 ,Clock monitor 0" "0,1,2,3"
|
|
group ad:0xF04C00A0++0x03
|
|
line.long 0x00 "TIM_CLK_CONFIG,Timer clock select and DIvider configuration."
|
|
bitfld.long 0x00 31. " CLK_CHANGE_UPD ,Set this bit to make new DIV_NUM/SRC_CLK_SEL value effective. Will be auto cleared after new DIV_NUM/SRC_CLK_SEL is effective" "0,1"
|
|
bitfld.long 0x00 16.--17. " SRC_CLK_SEL ,Clock source select. 00: High frequency(HF) clock, update to 400mhz. 01: Alternative High frequency(AHF) clock, update to 400mhz. 10: External clock. 11: Low power(LP) clock, typically from low speed on chip RCOSC." "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV_NUM ,DIvider number for timer clock."
|
|
group ad:0xF04C00A4++0x03
|
|
line.long 0x00 "CLK_MON_EN,Clock monitor enable register"
|
|
bitfld.long 0x00 2. " CMP_SET ,When enable or DIsable clock monitor, set this bit together. This bit is used to inDIcate configuration is completed." "0,1"
|
|
bitfld.long 0x00 1. " EN_N ,Active low. Enable clock monitor1" "0,1"
|
|
bitfld.long 0x00 0. " EN_P ,Active high.Enable clock monitor0" "0,1"
|
|
group ad:0xF04C00A8++0x03
|
|
line.long 0x00 "SW_RST,Software reset"
|
|
bitfld.long 0x00 5. " CNT_G1 ,Reset CNT_G1.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0 ,Reset CNT_G0.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Reset channel D. Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 2. " CHN_C ,Reset channel C.Will be auto cleared after reset complete." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CHN_B ,Reset channel B.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Reset channel A.Will be auto cleared after reset complete." "0,1"
|
|
group ad:0xF04C00B0++0x03
|
|
line.long 0x00 "CHN_DMA_CTRL,Channel DMA control register"
|
|
bitfld.long 0x00 19. " CHN_D_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 18. " CHN_C_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 17. " CHN_B_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 16. " CHN_A_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CHN_D_SIG_MASK ,Mask channel D dma request hardware output" "0,1"
|
|
bitfld.long 0x00 14. " CHN_C_SIG_MASK ,Mask channel C dma request hardware output" "0,1"
|
|
bitfld.long 0x00 13. " CHN_B_SIG_MASK ,Mask channel B dma request hardware output" "0,1"
|
|
bitfld.long 0x00 12. " CHN_A_SIG_MASK ,Mask channel A dma request hardware output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "CHN_D_SEL ,Select dma request working for CAPTURE D/COMPARE D channel 1x: Use for CPT_CMP delay mode D 01: Use for capture channel D. 00: Use for compare channel D." "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " CHN_C_SEL ,Select dma request working for CAPTURE C/COMPARE C channel 1x: Use for CPT_CMP delay mode C 01: Use for capture channel C. 00: Use for compare channel C." "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " CHN_B_SEL ,Select dma request working for CAPTURE B/COMPARE B channel 1x: Use for CPT_CMP delay mode B 01: Use for capture channel B. 00: Use for compare channel B." "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CHN_A_SEL ,Select dma request working for CAPTURE A/COMPARE A channel 1x: Use for CPT_CMP delay mode A 01: Use for capture channel A. 00: Use for compare channel A." "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CHN_D_EN ,Enable dma request for CAPTURE D/COMPARE D channel accorDIng to channel D FIFO WML." "0,1"
|
|
bitfld.long 0x00 2. " CHN_C_EN ,Enable dma request for CAPTURE C/COMPARE C channel accorDIng to channel C FIFO WML." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B_EN ,Enable dma request for CAPTURE B/COMPARE B channel accorDIng to channel B FIFO WML." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A_EN ,Enable dma request for CAPTURE A/COMPARE A channel accorDIng to channle A FIFO WML." "0,1"
|
|
group ad:0xF04C00B4++0x03
|
|
line.long 0x00 "DMA_WML,DMA watermark leverl register"
|
|
bitfld.long 0x00 24.--27. " CHN_D ,Waterwark level setting for channel D DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CHN_C ,Waterwark level setting for channel C DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CHN_B ,Waterwark level setting for channel B DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CHN_A ,Waterwark level setting for channel A DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04C00B8++0x03
|
|
line.long 0x00 "CONFIG_DMA_CTL,Configuration dma control register"
|
|
hexmask.long.word 0x00 2.--15. 1. " TRIG_SEL ,Select source to trigger dma request. 1. CMP_A_CE 2. CMP_B_CE 3. CMP_C_CE 4. CMP_D_CE 5. CPT_A_CE 6. CPT_B_CE 7. CPT_C_CE 8. CPT_D_CE 9. CNT_G0_CE 10. CNT_G1_CE 11. LCNT_A_CE 12. LCNT_B_CE 13. LCNT_C_CE 14. LCNT_D_CE.."
|
|
bitfld.long 0x00 1. " SIG_MASK ,Mask configuration dma request hardware output" "0,1"
|
|
bitfld.long 0x00 0. " EN ,DMA enable for register configuration" "0,1"
|
|
group ad:0xF04C00BC++0x03
|
|
line.long 0x00 "FIFO_REQ_STATUS,FIFO request status"
|
|
bitfld.long 0x00 3. " CHN_D ,Channel D FIFO reach water mark level" "0,1"
|
|
bitfld.long 0x00 2. " CHN_C ,Channel C FIFO reach water mark level" "0,1"
|
|
bitfld.long 0x00 1. " CHN_B ,Channel B FIFO reach water mark level" "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Channel A FIFO reach water mark level" "0,1"
|
|
group ad:0xF04C00C0++0x03
|
|
line.long 0x00 "FIFO_A,FIFO_entry for capture and compare channel A"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04C00C4++0x03
|
|
line.long 0x00 "FIFO_B,FIFO_entry for capture and compare channel B"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04C00C8++0x03
|
|
line.long 0x00 "FIFO_C,FIFO_entry for capture and compare channel C"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04C00CC++0x03
|
|
line.long 0x00 "FIFO_D,FIFO_entry for capture and compare channel D"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04C00D0++0x03
|
|
line.long 0x00 "FIFO_STA,FIFO status."
|
|
bitfld.long 0x00 31. " FIFO_ERR_D ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 26.--30. " FIFO_ENTRIES_D ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 25. " FIFO_EMPTY_D ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 24. " FIFO_FULL_D ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "FIFO_ERR_C ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 18.--22. " FIFO_ENTRIES_C ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17. " FIFO_EMPTY_C ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 16. " FIFO_FULL_C ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "FIFO_ERR_B ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 10.--14. " FIFO_ENTRIES_B ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " FIFO_EMPTY_B ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 8. " FIFO_FULL_B ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_ERR_A ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 2.--6. " FIFO_ENTRIES_A ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " FIFO_EMPTY_A ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 0. " FIFO_FULL_A ,InDIcate FIFO is full." "0,1"
|
|
group ad:0xF04C0100++0x03
|
|
line.long 0x00 "CNT_G0_INIT,Counter G0 initial value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0104++0x03
|
|
line.long 0x00 "CNT_G0_OVF,Counter G0 overflow value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0108++0x03
|
|
line.long 0x00 "CNT_G0_CFG,CNT_G0 configuration register."
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|
bitfld.long 0x00 31. " CASCADE_MODE ,When this bit is set, CNT_G1 only increase when CNT_G0 is overflowed. In this setup, CNT_G0 can work as a 64 bit timer if CNT_G0_OVF_VAL is 32'hffffffff." "0,1"
|
|
bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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|
bitfld.long 0x00 1.--2. " SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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|
group ad:0xF04C010C++0x03
|
|
line.long 0x00 "CNT_G0_EN,CNT_G0 enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
|
group ad:0xF04C0110++0x03
|
|
line.long 0x00 "CNT_G0,CNT_G0 TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C0114++0x03
|
|
line.long 0x00 "CNT_G0_HOLD,CNT_G0 Hold Register"
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|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04C0118++0x03
|
|
line.long 0x00 "CNT_G0_DIFF,CNT_G0 DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C0120++0x03
|
|
line.long 0x00 "CNT_G1_INIT,Counter G1 initial value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0124++0x03
|
|
line.long 0x00 "CNT_G1_OVF,Counter G1 overflow value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0128++0x03
|
|
line.long 0x00 "CNT_G1_CFG,CNT_G1 configuration register."
|
|
bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW" "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04C012C++0x03
|
|
line.long 0x00 "CNT_G1_EN,CNT_G1 enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
|
group ad:0xF04C0130++0x03
|
|
line.long 0x00 "CNT_G1,CNT_G1 TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C0134++0x03
|
|
line.long 0x00 "CNT_G1_HOLD,CNT_G1 Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
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|
group ad:0xF04C0138++0x03
|
|
line.long 0x00 "CNT_G1_DIFF,CNT_G1 DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C0140++0x03
|
|
line.long 0x00 "LCNT_A_INIT,Local counter A initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0144++0x03
|
|
line.long 0x00 "LCNT_A_OVF,Local counter A overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0148++0x03
|
|
line.long 0x00 "LCNT_A_CFG,Local counter A configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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|
group ad:0xF04C014C++0x03
|
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line.long 0x00 "LCNT_A_EN,Local counter A enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
|
|
group ad:0xF04C0150++0x03
|
|
line.long 0x00 "LCNT_A,LCNT_A TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C0154++0x03
|
|
line.long 0x00 "LCNT_A_HOLD,LCNT_A Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04C0158++0x03
|
|
line.long 0x00 "LCNT_A_DIFF,LCNT_A DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C0160++0x03
|
|
line.long 0x00 "LCNT_B_INIT,Local counter B initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0164++0x03
|
|
line.long 0x00 "LCNT_B_OVF,Local counter B overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0168++0x03
|
|
line.long 0x00 "LCNT_B_CFG,Local counter B configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04C016C++0x03
|
|
line.long 0x00 "LCNT_B_EN,Local counter B enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
|
|
group ad:0xF04C0170++0x03
|
|
line.long 0x00 "LCNT_B,LCNT_B TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C0174++0x03
|
|
line.long 0x00 "LCNT_B_HOLD,LCNT_B Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04C0178++0x03
|
|
line.long 0x00 "LCNT_B_DIFF,LCNT_B DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C0180++0x03
|
|
line.long 0x00 "LCNT_C_INIT,Local counter C initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0184++0x03
|
|
line.long 0x00 "LCNT_C_OVF,Local counter C overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C0188++0x03
|
|
line.long 0x00 "LCNT_C_CFG,Local counter C configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04C018C++0x03
|
|
line.long 0x00 "LCNT_C_EN,Local counter C enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
|
|
group ad:0xF04C0190++0x03
|
|
line.long 0x00 "LCNT_C,LCNT_C TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C0194++0x03
|
|
line.long 0x00 "LCNT_C_HOLD,LCNT_C Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04C0198++0x03
|
|
line.long 0x00 "LCNT_C_DIFF,LCNT_C DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04C01A0++0x03
|
|
line.long 0x00 "LCNT_D_INIT,Local counter D initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C01A4++0x03
|
|
line.long 0x00 "LCNT_D_OVF,Local counter D overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04C01A8++0x03
|
|
line.long 0x00 "LCNT_D_CFG,Local counter D configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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textline " "
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04C01AC++0x03
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line.long 0x00 "LCNT_D_EN,Local counter D enable register"
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
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group ad:0xF04C01B0++0x03
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line.long 0x00 "LCNT_D,LCNT_D TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04C01B4++0x03
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line.long 0x00 "LCNT_D_HOLD,LCNT_D Hold Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
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group ad:0xF04C01B8++0x03
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line.long 0x00 "LCNT_D_DIFF,LCNT_D DIff Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04C01C0++0x03
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line.long 0x00 "CPT_A_CPT0_CNT0,Capture A capture 0 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01C4++0x03
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line.long 0x00 "CPT_A_CPT0_CNT1,Capture A capture 0 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01C8++0x03
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line.long 0x00 "CPT_A_CPT1_CNT0,Capture A capture 1 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01CC++0x03
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line.long 0x00 "CPT_A_CPT1_CNT1,Capture A capture 1 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01D0++0x03
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line.long 0x00 "CPT_B_CPT0_CNT0,Capture B capture 0 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01D4++0x03
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line.long 0x00 "CPT_B_CPT0_CNT1,Capture B capture 0 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01D8++0x03
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line.long 0x00 "CPT_B_CPT1_CNT0,Capture B capture 1 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01DC++0x03
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line.long 0x00 "CPT_B_CPT1_CNT1,Capture B capture 1 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01E0++0x03
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line.long 0x00 "CPT_C_CPT0_CNT0,Capture C capture 0 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01E4++0x03
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line.long 0x00 "CPT_C_CPT0_CNT1,Capture C capture 0 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01E8++0x03
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line.long 0x00 "CPT_C_CPT1_CNT0,Capture C capture 1 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01EC++0x03
|
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line.long 0x00 "CPT_C_CPT1_CNT1,Capture C capture 1 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01F0++0x03
|
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line.long 0x00 "CPT_D_CPT0_CNT0,Capture D capture 0 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01F4++0x03
|
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line.long 0x00 "CPT_D_CPT0_CNT1,Capture D capture 0 counter 1 Register"
|
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01F8++0x03
|
|
line.long 0x00 "CPT_D_CPT1_CNT0,Capture D capture 1 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C01FC++0x03
|
|
line.long 0x00 "CPT_D_CPT1_CNT1,Capture D capture 1 counter 1 Register"
|
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04C0200++0x03
|
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line.long 0x00 "CPT_A_CONFIG,Capture A channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
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bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
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|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
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bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04C0204++0x03
|
|
line.long 0x00 "CPT_B_CONFIG,Capture B channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
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bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
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bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
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group ad:0xF04C0208++0x03
|
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line.long 0x00 "CPT_C_CONFIG,Capture C channel configuration register"
|
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bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
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textline " "
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bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
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bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
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group ad:0xF04C020C++0x03
|
|
line.long 0x00 "CPT_D_CONFIG,Capture D channel configuration register"
|
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bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
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bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
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textline " "
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bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
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bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
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|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
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group ad:0xF04C0210++0x03
|
|
line.long 0x00 "CPT_CTRL,Capture control register"
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bitfld.long 0x00 7. " CPT_D_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CPT_C_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
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bitfld.long 0x00 5. " CPT_B_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
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bitfld.long 0x00 4. " CPT_A_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
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textline " "
|
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bitfld.long 0x00 3. "CPT_D_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
bitfld.long 0x00 2. " CPT_C_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
bitfld.long 0x00 1. " CPT_B_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
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bitfld.long 0x00 0. " CPT_A_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
group ad:0xF04C0220++0x03
|
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line.long 0x00 "CMP_A_CONFIG,Compare A channel configuration register"
|
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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|
bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
|
|
bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
|
|
group ad:0xF04C0224++0x03
|
|
line.long 0x00 "CMP_A_EVENT_OUT_MODE,Compare A channel event output mode register"
|
|
bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
|
|
bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04C0228++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID0,Compare A channel output pulse width register0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
|
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
|
|
group ad:0xF04C022C++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID1,Compare A channel output pulse width register1"
|
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
|
|
group ad:0xF04C0230++0x03
|
|
line.long 0x00 "CMP_A_00_VAL,Compare value for compare A channel cmp00 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04C0234++0x03
|
|
line.long 0x00 "CMP_A_01_VAL,Compare value for compare A channel cmp01 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04C0238++0x03
|
|
line.long 0x00 "CMP_A_10_VAL,Compare value for compare A channel cmp10 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04C023C++0x03
|
|
line.long 0x00 "CMP_A_11_VAL,Compare value for compare A channel cmp11 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04C0240++0x03
|
|
line.long 0x00 "CMP_A_DITHER,Compare A channel DIther register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
|
|
group ad:0xF04C0244++0x03
|
|
line.long 0x00 "CMP_A_OFFSET,Compare A offset value register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
|
group ad:0xF04C0248++0x03
|
|
line.long 0x00 "CMP_A_EID,Compare A channel event ID register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,CMP11 event ID"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,CMP10 event ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,CMP01 event ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,CMP00 event ID"
|
|
group ad:0xF04C0250++0x03
|
|
line.long 0x00 "CMP_B_CONFIG,Compare B channel configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use.In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
|
|
bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
|
bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
|
|
bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04C0254++0x03
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line.long 0x00 "CMP_B_EVENT_OUT_MODE,Compare B channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04C0258++0x03
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line.long 0x00 "CMP_B_PULSE_WID0,Compare B channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04C025C++0x03
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line.long 0x00 "CMP_B_PULSE_WID1,Compare B channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04C0260++0x03
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line.long 0x00 "CMP_B_00_VAL,Compare value for compare B channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C0264++0x03
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line.long 0x00 "CMP_B_01_VAL,Compare value for compare B channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C0268++0x03
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line.long 0x00 "CMP_B_10_VAL,Compare value for compare B channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C026C++0x03
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line.long 0x00 "CMP_B_11_VAL,Compare value for compare B channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C0270++0x03
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line.long 0x00 "CMP_B_DITHER,Compare B channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04C0274++0x03
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line.long 0x00 "CMP_B_OFFSET,Compare B offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04C0280++0x03
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line.long 0x00 "CMP_C_CONFIG,Compare C channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04C0284++0x03
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line.long 0x00 "CMP_C_EVENT_OUT_MODE,Compare C channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04C0288++0x03
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line.long 0x00 "CMP_C_PULSE_WID0,Compare C channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04C028C++0x03
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line.long 0x00 "CMP_C_PULSE_WID1,Compare C channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04C0290++0x03
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line.long 0x00 "CMP_C_00_VAL,Compare value for compare C channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C0294++0x03
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line.long 0x00 "CMP_C_01_VAL,Compare value for compare C channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C0298++0x03
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line.long 0x00 "CMP_C_10_VAL,Compare value for compare C channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C029C++0x03
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line.long 0x00 "CMP_C_11_VAL,Compare value for compare C channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C02A0++0x03
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line.long 0x00 "CMP_C_DITHER,Compare C channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04C02A4++0x03
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line.long 0x00 "CMP_C_OFFSET,Compare C offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04C02B0++0x03
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line.long 0x00 "CMP_D_CONFIG,Compare D channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04C02B4++0x03
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line.long 0x00 "CMP_D_EVENT_OUT_MODE,Compare D channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04C02B8++0x03
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line.long 0x00 "CMP_D_PULSE_WID0,Compare D channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04C02BC++0x03
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line.long 0x00 "CMP_D_PULSE_WID1,Compare D channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04C02C0++0x03
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line.long 0x00 "CMP_D_00_VAL,Compare value for compare D channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C02C4++0x03
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line.long 0x00 "CMP_D_01_VAL,Compare value for compare D channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C02C8++0x03
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line.long 0x00 "CMP_D_10_VAL,Compare value for compare D channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C02CC++0x03
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line.long 0x00 "CMP_D_11_VAL,Compare value for compare D channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04C02D0++0x03
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line.long 0x00 "CMP_D_DITHER,Compare D channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04C02D4++0x03
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line.long 0x00 "CMP_D_OFFSET,Compare D offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04C02E0++0x03
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line.long 0x00 "CMP_CTRL,Compare control register"
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bitfld.long 0x00 28. " CMP_A_EID_UPD ,Update EID value. Will be auto clear after completing update EID value." "0,1"
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bitfld.long 0x00 27. " CMP_D1_INIT_UPD ,Update cmp_d1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 26. " CMP_D0_INIT_UPD ,Update cmp_d0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 25. " CMP_C1_INIT_UPD ,Update cmp_c1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 24. "CMP_C0_INIT_UPD ,Update cmp_c0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 23. " CMP_B1_INIT_UPD ,Update cmp_b1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 22. " CMP_B0_INIT_UPD ,Update cmp_b0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 21. " CMP_A1_INIT_UPD ,Update cmp_a1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 20. "CMP_A0_INIT_UPD ,Update cmp_a0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 19. " CMP_D1_INIT_STATUS ,cmp_d1 output initial status" "0,1"
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bitfld.long 0x00 18. " CMP_D0_INIT_STATUS ,cmp_d0 output initial status" "0,1"
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bitfld.long 0x00 17. " CMP_C1_INIT_STATUS ,cmp_c1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 16. "CMP_C0_INIT_STATUS ,cmp_c0 output initial status" "0,1"
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bitfld.long 0x00 15. " CMP_B1_INIT_STATUS ,cmp_b1 output initial status" "0,1"
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bitfld.long 0x00 14. " CMP_B0_INIT_STATUS ,cmp_b0 output initial status" "0,1"
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bitfld.long 0x00 13. " CMP_A1_INIT_STATUS ,cmp_a1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 12. "CMP_A0_INIT_STATUS ,cmp_a0 output initial status" "0,1"
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bitfld.long 0x00 11. " CMP_D_VAL_UPD ,Update all the compare value registers for compare D channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 10. " CMP_C_VAL_UPD ,Update all the compare value registers for compare C channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 9. " CMP_B_VAL_UPD ,Update all the compare value registers for compare B channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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textline " "
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bitfld.long 0x00 8. "CMP_A_VAL_UPD ,Update all the compare value registers for compare A channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 7. " CMP_D_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CMP_C_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 5. " CMP_B_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour.." "0,1"
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textline " "
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bitfld.long 0x00 4. "CMP_A_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 3. " CMP_D_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 2. " CMP_C_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 1. " CMP_B_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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textline " "
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bitfld.long 0x00 0. "CMP_A_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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group ad:0xF04C0300++0x03
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line.long 0x00 "CPT_A_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_A0 signals into one signal for capture channel A"
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bitfld.long 0x00 26. " QUAD_INDEX_POL ,When this bit is set, INDEX signal polarity is changed." "0,1"
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bitfld.long 0x00 25. " QUAD_HOME_POL ,When this bit is set, HOME signal polarity is changed." "0,1"
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bitfld.long 0x00 21.--24. " QUAD_CLR_SEL ,In quadrature mode, the counter CLR event can be configured to be initiated by HOME or INDEX input 0000: HOME high 0001: INDEX high 0010: HOME high and {PHASE_B, PHASE_A} = 2'b00; 0011: HOME high and {PHASE_B, PHASE_A} = 2'.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 17.--20. " QUAD_SET_SEL ,In quadrature mode, the counter SET event can be configured to be initiated by HOME or INDEX input 0000: HOME high 0001: INDEX high 0010: HOME high and {PHASE_B, PHASE_A} = 2'b00; 0011: HOME high and {PHASE_B, PHASE_A} = 2'.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 16. "QUAD_MODE_EN ,Quadrature mode enable" "0,1"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04C0304++0x03
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line.long 0x00 "CPT_A_SSE_REG,Signal synthesis for CAPTURE A"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04C0308++0x03
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line.long 0x00 "CPT_B_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_B0 signals into one signal for capture channel B"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04C030C++0x03
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line.long 0x00 "CPT_B_SSE_REG,Signal synthesis for CAPTURE B"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04C0310++0x03
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line.long 0x00 "CPT_C_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_C0 signals into one signal for capture channel C"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04C0314++0x03
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line.long 0x00 "CPT_C_SSE_REG,Signal synthesis for CAPTURE C"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04C0318++0x03
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line.long 0x00 "CPT_D_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_D0 signals into one signal for capture channel D"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04C031C++0x03
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line.long 0x00 "CPT_D_SSE_REG,Signal synthesis for CAPTURE D"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04C0320++0x03
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line.long 0x00 "CMP_A_SSE_CTRL,Synthesis CMP_A0,CMP_B0,CMP_C0 and CMP_D0 outputs and CPT_A_SSE SO signals into one signal for compare channel A"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_A_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04C0324++0x03
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line.long 0x00 "CMP_A_SSE_REG,Signal synthesis for compare A output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04C0328++0x03
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line.long 0x00 "CMP_B_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_B_SSE SO signals into one signal for compare channel B"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_B_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04C032C++0x03
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line.long 0x00 "CMP_B_SSE_REG,Signal synthesis for compare B output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04C0330++0x03
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line.long 0x00 "CMP_C_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_C_SSE SO signals into one signal for compare channel C"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_C_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04C0334++0x03
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line.long 0x00 "CMP_C_SSE_REG,Signal synthesis for compare C output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04C0338++0x03
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line.long 0x00 "CMP_D_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_D_SSE SO signals into one signal for compare channel D"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_D_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04C033C++0x03
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line.long 0x00 "CMP_D_SSE_REG,Signal synthesis for compare D output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04C0340++0x03
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line.long 0x00 "CPT_A_INPUT_SEL,Capture A channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_A1 1000: CMP_A1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_A_SSE_SO 0001: CPT_A1 0010: CMP_A1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_A_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_A_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C0344++0x03
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line.long 0x00 "CPT_B_INPUT_SEL,Capture B channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_B1 1000: CMP_B1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_B_SSE_SO 0001: CPT_B1 0010: CMP_B1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_B_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_B_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C0348++0x03
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line.long 0x00 "CPT_C_INPUT_SEL,Capture C channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_C1 1000: CMP_C1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_C_SSE_SO 0001: CPT_C1 0010: CMP_C1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_C_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_C_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C034C++0x03
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line.long 0x00 "CPT_D_INPUT_SEL,Capture D channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_D1 1000: CMP_D1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_D_SSE_SO 0001: CPT_D1 0010: CMP_D1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_D_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_D_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C0350++0x03
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line.long 0x00 "CMP_A_INPUT_SEL,Compare A channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C0354++0x03
|
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line.long 0x00 "CMP_B_INPUT_SEL,Compare B channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C0358++0x03
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line.long 0x00 "CMP_C_INPUT_SEL,Compare C channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C035C++0x03
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line.long 0x00 "CMP_D_INPUT_SEL,Compare D channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C0360++0x03
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line.long 0x00 "CNT_G0_INPUT_SEL,Counter G0 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C0364++0x03
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line.long 0x00 "CNT_G1_INPUT_SEL,Counter G1 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C0368++0x03
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line.long 0x00 "EXT_OUTPUT_SEL,External output source select register"
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bitfld.long 0x00 8.--11. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_A1 1000: CPT_B1 1001: CPT_C1 1010: CPT_D1 1011: CMP_A1 1100: SW_TRIG0.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04C036C++0x03
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line.long 0x00 "ETM_POL_INV,Event trigger polarity invert"
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bitfld.long 0x00 30. " EXT_DIR ,Polarity invert" "0,1"
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bitfld.long 0x00 29. " EXT_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 28. " EXT_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 27. " CNT_G1_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 26. "CNT_G1_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 25. " CNT_G0_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 24. " CNT_G0_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 23. " CMP_D_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 22. "CMP_D_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 21. " CMP_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 20. " CMP_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 19. " CMP_B_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 18. "CMP_B_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 17. " CMP_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 16. " CMP_A_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 15. " CPT_D_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 14. "CPT_D_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 13. " CPT_D_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 12. " CPT_D_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 11. " CPT_C_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 10. "CPT_C_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 9. " CPT_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 8. " CPT_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 7. " CPT_B_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 6. "CPT_B_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 5. " CPT_B_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 4. " CPT_B_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 3. " CPT_A_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 2. "CPT_A_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 1. " CPT_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 0. " CPT_A_SET ,Polarity invert" "0,1"
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group ad:0xF04C0370++0x03
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line.long 0x00 "CPT_SW_TRIG,Capture signal software trigger register"
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bitfld.long 0x00 11. " CPT_D_SIG ,Set high to generate SIG pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 10. " CPT_C_SIG ,Set high to generate SIG pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 9. " CPT_B_SIG ,Set high to generate SIG pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 8. " CPT_A_SIG ,Set high to generate SIG pulse signal for capture A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 7. "CPT_D_CLR ,Set high to generate CLR pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CPT_C_CLR ,Set high to generate CLR pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CPT_B_CLR ,Set high to generate CLR pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CPT_A_CLR ,Set high to generate CLR pulse signal for capture A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CPT_D_SET ,Set high to generate SET pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CPT_C_SET ,Set high to generate SET pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CPT_B_SET ,Set high to generate SET pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CPT_A_SET ,Set high to generate SET pulse signal for capture A channel. Auto clear after set." "0,1"
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group ad:0xF04C0374++0x03
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line.long 0x00 "CMP_SW_TRIG,Compare signal software trigger register"
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bitfld.long 0x00 7. " CMP_D_CLR ,Set high to generate CLR pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CMP_C_CLR ,Set high to generate CLR pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CMP_B_CLR ,Set high to generate CLR pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CMP_A_CLR ,Set high to generate CLR pulse signal for compare A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CMP_D_SET ,Set high to generate SET pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CMP_C_SET ,Set high to generate SET pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CMP_B_SET ,Set high to generate SET pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CMP_A_SET ,Set high to generate SET pulse signal for compare A channel. Auto clear after set." "0,1"
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group ad:0xF04C0378++0x03
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line.long 0x00 "CNT_EXT_SW_TRIG,Counter and external signal software trigger register"
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bitfld.long 0x00 5. " EXT_CLR ,Set high to generate CLR pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " EXT_SET ,Set high to generate SET pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 3. " CNT_G1_CLR ,Set high to generate CLR pulse signal for CNT_G1. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CNT_G1_SET ,Set high to generate SET pulse signal for CNT_G1. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 1. "CNT_G0_CLR ,Set high to generate CLR pulse signal for CNT_G0. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CNT_G0_SET ,Set high to generate SET pulse signal for CNT_G0. Auto clear after set." "0,1"
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group ad:0xF04C0380++0x03
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line.long 0x00 "SW_TRIG_CTRL,SW trigger event generation control"
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bitfld.long 0x00 15. " SW_TRIG3_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 14. " SW_TRIG3_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 13. " SW_TRIG3_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 12. " SW_TRIG3_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 11. "SW_TRIG2_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 10. " SW_TRIG2_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 9. " SW_TRIG2_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 8. " SW_TRIG2_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 7. "SW_TRIG1_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 6. " SW_TRIG1_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 5. " SW_TRIG1_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 4. " SW_TRIG1_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 3. "SW_TRIG0_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 2. " SW_TRIG0_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 1. " SW_TRIG0_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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group ad:0xF04C0384++0x03
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line.long 0x00 "SW_TRIG_STATUS,SW trigger outputs status"
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bitfld.long 0x00 3. " SW_TRIG3 ,SW trigger output" "0,1"
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bitfld.long 0x00 2. " SW_TRIG2 ,SW trigger output" "0,1"
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bitfld.long 0x00 1. " SW_TRIG1 ,SW trigger output" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0 ,SW trigger output" "0,1"
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group ad:0xF04C0388++0x03
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line.long 0x00 "SW_TRIG_PULSE0,SW trigger0 and trigger1 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG1_WIDTH ,Pulse width of SW trigger1"
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hexmask.long.word 0x00 0.--15. 1. " TRIG0_WIDTH ,Pulse width of SW trigger0"
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group ad:0xF04C038C++0x03
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line.long 0x00 "SW_TRIG_PULSE1,SW trigger2 and trigger3 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG3_WIDTH ,Pulse width of SW trigger3"
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hexmask.long.word 0x00 0.--15. 1. " TRIG2_WIDTH ,Pulse width of SW trigger2"
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group ad:0xF04C0390++0x03
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line.long 0x00 "CNT_G0_SNAP_SHOT_SEL,CNT_G0 snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04C0394++0x03
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line.long 0x00 "CNT_G1_SNAP_SHOT_SEL,CNT_G1 snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04C0398++0x03
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line.long 0x00 "LCNT_A_SNAP_SHOT_SEL,LCNT_A snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04C039C++0x03
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line.long 0x00 "LCNT_B_SNAP_SHOT_SEL,LCNT_B snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04C03A0++0x03
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line.long 0x00 "LCNT_C_SNAP_SHOT_SEL,LCNT_C snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04C03A4++0x03
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line.long 0x00 "LCNT_D_SNAP_SHOT_SEL,LCNT_D snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04C03A8++0x03
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line.long 0x00 "SNAP_SHOT_O_SEL,Snapshot output snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04C0400++0x03
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line.long 0x00 "CPT_A0_FLT,Filter setting for CPT_A0 input."
|
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
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group ad:0xF04C0404++0x03
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line.long 0x00 "CPT_B0_FLT,Filter setting for CPT_B0 input."
|
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04C0408++0x03
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line.long 0x00 "CPT_C0_FLT,Filter setting for CPT_C0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04C040C++0x03
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line.long 0x00 "CPT_D0_FLT,Filter setting for CPT_D0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04C0410++0x03
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line.long 0x00 "FAULT0_FLT,Filter setting for fault0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04C0414++0x03
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line.long 0x00 "FAULT1_FLT,Filter setting for fault1 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04C0418++0x03
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line.long 0x00 "FAULT2_FLT,Filter setting for fault2 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04C041C++0x03
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line.long 0x00 "FAULT3_FLT,Filter setting for fault3 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04C0420++0x03
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line.long 0x00 "SYNC_DIS,Synchronization DIsable control register"
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bitfld.long 0x00 15. " FAULT3 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 14. " FAULT2 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 13. " FAULT1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 12. " FAULT0 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 10. "SNAP_SHOT ,DIsable synchronization" "0,1"
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bitfld.long 0x00 9. " EXT_CLR ,DIsable synchronization" "0,1"
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bitfld.long 0x00 8. " EXT_SET ,DIsable synchronization" "0,1"
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bitfld.long 0x00 7. " CPT_D1 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 6. "CPT_C1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 5. " CPT_B1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 4. " CPT_A1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 3. " CPT_D0 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 2. "CPT_C0 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 1. " CPT_B0 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 0. " CPT_A0 ,DIsable synchronization" "0,1"
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group ad:0xF04C0440++0x03
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line.long 0x00 "CMP_A_FAULT_EVENT_CTRL,Compare A channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF04C0444++0x03
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line.long 0x00 "CMP_B_FAULT_EVENT_CTRL,Compare B channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
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group ad:0xF04C0448++0x03
|
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line.long 0x00 "CMP_C_FAULT_EVENT_CTRL,Compare C channel event control register"
|
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
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group ad:0xF04C044C++0x03
|
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line.long 0x00 "CMP_D_FAULT_EVENT_CTRL,Compare D channel event control register"
|
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04C0460++0x03
|
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line.long 0x00 "CMP_A_DTI_CTRL,Dead time insertion control register for compare A channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04C0464++0x03
|
|
line.long 0x00 "CMP_A_DTI_WID,Dead time insertion width register for compare A channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF04C0468++0x03
|
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line.long 0x00 "CMP_B_DTI_CTRL,Dead time insertion control register for compare B channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04C046C++0x03
|
|
line.long 0x00 "CMP_B_DTI_WID,Dead time insertion width register for compare B channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04C0470++0x03
|
|
line.long 0x00 "CMP_C_DTI_CTRL,Dead time insertion control register for compare C channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04C0474++0x03
|
|
line.long 0x00 "CMP_C_DTI_WID,Dead time insertion width register for compare C channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04C0478++0x03
|
|
line.long 0x00 "CMP_D_DTI_CTRL,Dead time insertion control register for compare D channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04C047C++0x03
|
|
line.long 0x00 "CMP_D_DTI_WID,Dead time insertion width register for compare D channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04C0500++0x03
|
|
line.long 0x00 "SIGNAL_STATUS,Signal status register"
|
|
bitfld.long 0x00 31. " CPT_D_CLR ,Capture D clear signal" "0,1"
|
|
bitfld.long 0x00 30. " CPT_D_SET ,Capture D set signal" "0,1"
|
|
bitfld.long 0x00 29. " CPT_D_DIR ,Capture D DIR signal" "0,1"
|
|
bitfld.long 0x00 28. " CPT_D_SIG ,Capture D SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "CPT_C_CLR ,Capture C clear signal" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_SET ,Capture C set signal" "0,1"
|
|
bitfld.long 0x00 25. " CPT_C_DIR ,Capture C DIR signal" "0,1"
|
|
bitfld.long 0x00 24. " CPT_C_SIG ,Capture C SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CPT_B_CLR ,Capture B clr signal" "0,1"
|
|
bitfld.long 0x00 22. " CPT_B_SET ,Capture B set signal" "0,1"
|
|
bitfld.long 0x00 21. " CPT_B_DIR ,Capture B DIR signal" "0,1"
|
|
bitfld.long 0x00 20. " CPT_B_SIG ,Capture B SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CPT_A_CLR ,Capture A clear signal" "0,1"
|
|
bitfld.long 0x00 18. " CPT_A_SET ,Capture A set signal" "0,1"
|
|
bitfld.long 0x00 17. " CPT_A_DIR ,Capture A DIR signal" "0,1"
|
|
bitfld.long 0x00 16. " CPT_A_SIG ,Capture A SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_CLR ,Compare D clear signal" "0,1"
|
|
bitfld.long 0x00 14. " CMP_D_SET ,Compare D set signal" "0,1"
|
|
bitfld.long 0x00 13. " CMP_C_CLR ,Compare C clear signal" "0,1"
|
|
bitfld.long 0x00 12. " CMP_C_SET ,Compare C set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_B_CLR ,Compare B clear signal" "0,1"
|
|
bitfld.long 0x00 10. " CMP_B_SET ,Compare B set signal" "0,1"
|
|
bitfld.long 0x00 9. " CMP_A_CLR ,Compare A clear signal" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A_SET ,Compare A set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D1 ,Compare D1 signal" "0,1"
|
|
bitfld.long 0x00 6. " CMP_D0 ,Compare D0 signal" "0,1"
|
|
bitfld.long 0x00 5. " CMP_C1 ,Compare C1 signal" "0,1"
|
|
bitfld.long 0x00 4. " CMP_C0 ,Compare C0 signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CMP_B1 ,Compare B1 signal" "0,1"
|
|
bitfld.long 0x00 2. " CMP_B0 ,Compare B0 signal" "0,1"
|
|
bitfld.long 0x00 1. " CMP_A1 ,Compare A1 signal" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A0 ,Compare A0 signal" "0,1"
|
|
group ad:0xF04C0FFC++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
tree.end
|
|
tree "ETIMER2"
|
|
width 28.
|
|
group ad:0xF04D0000++0x03
|
|
line.long 0x00 "INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,LCNT_D snapshot event happens" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,LCNT_C snapshot event happens" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,LCNT_B snapshot event happens" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,LCNT_A snapshot event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,CNT_G1 snapshot event happens" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,CNT_G0 snapshot event happens" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,CNT_LOCAL_D overflow" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,CNT_LOCAL_C overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,CNT_LOCAL_B overflow" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,CNT_LOCAL_A overflow" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,CNT_G1 overflow" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,CNT_G0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Compare D event happens" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Compare C event happens" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Compare B event happens" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Compare A event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Capture D event happens" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Capture C event happens" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Capture B event happens" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Capture A event happens" "0,1"
|
|
group ad:0xF04D0004++0x03
|
|
line.long 0x00 "INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Status enable" "0,1"
|
|
group ad:0xF04D0008++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt singal enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Singal enable" "0,1"
|
|
group ad:0xF04D000C++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA,Correctable error interrupt status register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,CPT D vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,CPT C vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,CPT B vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,CPT A vaule is not fetched" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,FIFO D overrun" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,FIFO C overrun" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,FIFO B overrun" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,FIFO A overrun" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04D0010++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA_EN,Correctable error interrupt status enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04D0014++0x03
|
|
line.long 0x00 "COR_ERR_INT_SIG_EN,Correctable error interrupt singal enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04D0018++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA,Uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,CPT D vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,CPT C vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,CPT B vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,CPT A vaule is not fetched" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,FIFO D overrun" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,FIFO C overrun" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,FIFO B overrun" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,FIFO A overrun" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04D001C++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04D0020++0x03
|
|
line.long 0x00 "UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt singal enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04D0024++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata corrctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04D0028++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04D002C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04D0030++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Cock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Cock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error." "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error." "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error." "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04D0034++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
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bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
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|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
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|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
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|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
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|
textline " "
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bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
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|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
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|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
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|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
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|
textline " "
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
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|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
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|
group ad:0xF04D0038++0x03
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|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
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|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error." "0,1"
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|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error." "0,1"
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|
bitfld.long 0x00 27. " INPUT_ERR ,Input singal error" "0,1"
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|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,CONFIG_DMA eoba error" "0,1"
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|
textline " "
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bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
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bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
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|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
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bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
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|
textline " "
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|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
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|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
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|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
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|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
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|
textline " "
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bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
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|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
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|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
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|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
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|
textline " "
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bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
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|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
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|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
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|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
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|
textline " "
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|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
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|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
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|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
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|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
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|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
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|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
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|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
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bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
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group ad:0xF04D003C++0x03
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line.long 0x00 "FUSA_UNC_ERR_INT_STA_1,Function safety correctable error interrupt status register"
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|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
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|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
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|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
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|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
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|
group ad:0xF04D0040++0x03
|
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line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN_1,Function safety correctable error interrupt status enable register"
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|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
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|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
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|
group ad:0xF04D0044++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN_1,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,CONFIG_DMA eobc error" "0,1"
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|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
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|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
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|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
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|
group ad:0xF04D004C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF04D0050++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF04D0054++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF04D005C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF04D0060++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,RAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
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|
group ad:0xF04D0064++0x03
|
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line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04D0068++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,RAM B rdata monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
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|
group ad:0xF04D006C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,RAM B rdata ECC monitorerror injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
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group ad:0xF04D0070++0x03
|
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line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
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|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
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|
group ad:0xF04D0074++0x03
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line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
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group ad:0xF04D0080++0x03
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line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
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bitfld.long 0x00 16.--18. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7"
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|
textline " "
|
|
bitfld.long 0x00 0.--2. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7"
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group ad:0xF04D0084++0x03
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line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
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bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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textline " "
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bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D0088++0x03
|
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line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
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bitfld.long 0x00 16.--19. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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textline " "
|
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bitfld.long 0x00 0.--3. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D008C++0x03
|
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line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
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bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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textline " "
|
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bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group ad:0xF04D0090++0x03
|
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line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
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bitfld.long 0x00 6. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
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bitfld.long 0x00 5. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
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bitfld.long 0x00 4. " CNT_OVF ,Counter overflow and snapshot interrupt error injection." "0,1"
|
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bitfld.long 0x00 3. " CHN_D ,Channel D interrupt error injection." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 2. "CHN_C ,Channel C interrupt error injection." "0,1"
|
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bitfld.long 0x00 1. " CHN_B ,Channel B interrupt error injection." "0,1"
|
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bitfld.long 0x00 0. " CHN_A ,Channel A interrupt error injection." "0,1"
|
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group ad:0xF04D0094++0x03
|
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line.long 0x00 "CLK_MON_CMP_ERR_INJ,Clock monitor compare error injection r"
|
|
bitfld.long 0x00 2.--3. " ERR1 ,Clock monitor 1" "0,1,2,3"
|
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bitfld.long 0x00 0.--1. " ERR0 ,Clock monitor 0" "0,1,2,3"
|
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group ad:0xF04D00A0++0x03
|
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line.long 0x00 "TIM_CLK_CONFIG,Timer clock select and DIvider configuration."
|
|
bitfld.long 0x00 31. " CLK_CHANGE_UPD ,Set this bit to make new DIV_NUM/SRC_CLK_SEL value effective. Will be auto cleared after new DIV_NUM/SRC_CLK_SEL is effective" "0,1"
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bitfld.long 0x00 16.--17. " SRC_CLK_SEL ,Clock source select. 00: High frequency(HF) clock, update to 400mhz. 01: Alternative High frequency(AHF) clock, update to 400mhz. 10: External clock. 11: Low power(LP) clock, typically from low speed on chip RCOSC." "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. " DIV_NUM ,DIvider number for timer clock."
|
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group ad:0xF04D00A4++0x03
|
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line.long 0x00 "CLK_MON_EN,Clock monitor enable register"
|
|
bitfld.long 0x00 2. " CMP_SET ,When enable or DIsable clock monitor, set this bit together. This bit is used to inDIcate configuration is completed." "0,1"
|
|
bitfld.long 0x00 1. " EN_N ,Active low. Enable clock monitor1" "0,1"
|
|
bitfld.long 0x00 0. " EN_P ,Active high.Enable clock monitor0" "0,1"
|
|
group ad:0xF04D00A8++0x03
|
|
line.long 0x00 "SW_RST,Software reset"
|
|
bitfld.long 0x00 5. " CNT_G1 ,Reset CNT_G1.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0 ,Reset CNT_G0.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Reset channel D. Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 2. " CHN_C ,Reset channel C.Will be auto cleared after reset complete." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CHN_B ,Reset channel B.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Reset channel A.Will be auto cleared after reset complete." "0,1"
|
|
group ad:0xF04D00B0++0x03
|
|
line.long 0x00 "CHN_DMA_CTRL,Channel DMA control register"
|
|
bitfld.long 0x00 19. " CHN_D_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 18. " CHN_C_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 17. " CHN_B_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 16. " CHN_A_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CHN_D_SIG_MASK ,Mask channel D dma request hardware output" "0,1"
|
|
bitfld.long 0x00 14. " CHN_C_SIG_MASK ,Mask channel C dma request hardware output" "0,1"
|
|
bitfld.long 0x00 13. " CHN_B_SIG_MASK ,Mask channel B dma request hardware output" "0,1"
|
|
bitfld.long 0x00 12. " CHN_A_SIG_MASK ,Mask channel A dma request hardware output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "CHN_D_SEL ,Select dma request working for CAPTURE D/COMPARE D channel 1x: Use for CPT_CMP delay mode D 01: Use for capture channel D. 00: Use for compare channel D." "0,1,2,3"
|
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bitfld.long 0x00 8.--9. " CHN_C_SEL ,Select dma request working for CAPTURE C/COMPARE C channel 1x: Use for CPT_CMP delay mode C 01: Use for capture channel C. 00: Use for compare channel C." "0,1,2,3"
|
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bitfld.long 0x00 6.--7. " CHN_B_SEL ,Select dma request working for CAPTURE B/COMPARE B channel 1x: Use for CPT_CMP delay mode B 01: Use for capture channel B. 00: Use for compare channel B." "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CHN_A_SEL ,Select dma request working for CAPTURE A/COMPARE A channel 1x: Use for CPT_CMP delay mode A 01: Use for capture channel A. 00: Use for compare channel A." "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CHN_D_EN ,Enable dma request for CAPTURE D/COMPARE D channel accorDIng to channel D FIFO WML." "0,1"
|
|
bitfld.long 0x00 2. " CHN_C_EN ,Enable dma request for CAPTURE C/COMPARE C channel accorDIng to channel C FIFO WML." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B_EN ,Enable dma request for CAPTURE B/COMPARE B channel accorDIng to channel B FIFO WML." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A_EN ,Enable dma request for CAPTURE A/COMPARE A channel accorDIng to channle A FIFO WML." "0,1"
|
|
group ad:0xF04D00B4++0x03
|
|
line.long 0x00 "DMA_WML,DMA watermark leverl register"
|
|
bitfld.long 0x00 24.--27. " CHN_D ,Waterwark level setting for channel D DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 16.--19. " CHN_C ,Waterwark level setting for channel C DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CHN_B ,Waterwark level setting for channel B DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CHN_A ,Waterwark level setting for channel A DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04D00B8++0x03
|
|
line.long 0x00 "CONFIG_DMA_CTL,Configuration dma control register"
|
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hexmask.long.word 0x00 2.--15. 1. " TRIG_SEL ,Select source to trigger dma request. 1. CMP_A_CE 2. CMP_B_CE 3. CMP_C_CE 4. CMP_D_CE 5. CPT_A_CE 6. CPT_B_CE 7. CPT_C_CE 8. CPT_D_CE 9. CNT_G0_CE 10. CNT_G1_CE 11. LCNT_A_CE 12. LCNT_B_CE 13. LCNT_C_CE 14. LCNT_D_CE.."
|
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bitfld.long 0x00 1. " SIG_MASK ,Mask configuration dma request hardware output" "0,1"
|
|
bitfld.long 0x00 0. " EN ,DMA enable for register configuration" "0,1"
|
|
group ad:0xF04D00BC++0x03
|
|
line.long 0x00 "FIFO_REQ_STATUS,FIFO request status"
|
|
bitfld.long 0x00 3. " CHN_D ,Channel D FIFO reach water mark level" "0,1"
|
|
bitfld.long 0x00 2. " CHN_C ,Channel C FIFO reach water mark level" "0,1"
|
|
bitfld.long 0x00 1. " CHN_B ,Channel B FIFO reach water mark level" "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Channel A FIFO reach water mark level" "0,1"
|
|
group ad:0xF04D00C0++0x03
|
|
line.long 0x00 "FIFO_A,FIFO_entry for capture and compare channel A"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04D00C4++0x03
|
|
line.long 0x00 "FIFO_B,FIFO_entry for capture and compare channel B"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04D00C8++0x03
|
|
line.long 0x00 "FIFO_C,FIFO_entry for capture and compare channel C"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04D00CC++0x03
|
|
line.long 0x00 "FIFO_D,FIFO_entry for capture and compare channel D"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04D00D0++0x03
|
|
line.long 0x00 "FIFO_STA,FIFO status."
|
|
bitfld.long 0x00 31. " FIFO_ERR_D ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 26.--30. " FIFO_ENTRIES_D ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 25. " FIFO_EMPTY_D ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 24. " FIFO_FULL_D ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "FIFO_ERR_C ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 18.--22. " FIFO_ENTRIES_C ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17. " FIFO_EMPTY_C ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 16. " FIFO_FULL_C ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "FIFO_ERR_B ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 10.--14. " FIFO_ENTRIES_B ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " FIFO_EMPTY_B ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 8. " FIFO_FULL_B ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_ERR_A ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 2.--6. " FIFO_ENTRIES_A ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " FIFO_EMPTY_A ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 0. " FIFO_FULL_A ,InDIcate FIFO is full." "0,1"
|
|
group ad:0xF04D0100++0x03
|
|
line.long 0x00 "CNT_G0_INIT,Counter G0 initial value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0104++0x03
|
|
line.long 0x00 "CNT_G0_OVF,Counter G0 overflow value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0108++0x03
|
|
line.long 0x00 "CNT_G0_CFG,CNT_G0 configuration register."
|
|
bitfld.long 0x00 31. " CASCADE_MODE ,When this bit is set, CNT_G1 only increase when CNT_G0 is overflowed. In this setup, CNT_G0 can work as a 64 bit timer if CNT_G0_OVF_VAL is 32'hffffffff." "0,1"
|
|
bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04D010C++0x03
|
|
line.long 0x00 "CNT_G0_EN,CNT_G0 enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
|
group ad:0xF04D0110++0x03
|
|
line.long 0x00 "CNT_G0,CNT_G0 TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D0114++0x03
|
|
line.long 0x00 "CNT_G0_HOLD,CNT_G0 Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04D0118++0x03
|
|
line.long 0x00 "CNT_G0_DIFF,CNT_G0 DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D0120++0x03
|
|
line.long 0x00 "CNT_G1_INIT,Counter G1 initial value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0124++0x03
|
|
line.long 0x00 "CNT_G1_OVF,Counter G1 overflow value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0128++0x03
|
|
line.long 0x00 "CNT_G1_CFG,CNT_G1 configuration register."
|
|
bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW" "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04D012C++0x03
|
|
line.long 0x00 "CNT_G1_EN,CNT_G1 enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
|
group ad:0xF04D0130++0x03
|
|
line.long 0x00 "CNT_G1,CNT_G1 TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D0134++0x03
|
|
line.long 0x00 "CNT_G1_HOLD,CNT_G1 Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04D0138++0x03
|
|
line.long 0x00 "CNT_G1_DIFF,CNT_G1 DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D0140++0x03
|
|
line.long 0x00 "LCNT_A_INIT,Local counter A initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0144++0x03
|
|
line.long 0x00 "LCNT_A_OVF,Local counter A overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0148++0x03
|
|
line.long 0x00 "LCNT_A_CFG,Local counter A configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04D014C++0x03
|
|
line.long 0x00 "LCNT_A_EN,Local counter A enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
|
|
group ad:0xF04D0150++0x03
|
|
line.long 0x00 "LCNT_A,LCNT_A TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D0154++0x03
|
|
line.long 0x00 "LCNT_A_HOLD,LCNT_A Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04D0158++0x03
|
|
line.long 0x00 "LCNT_A_DIFF,LCNT_A DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D0160++0x03
|
|
line.long 0x00 "LCNT_B_INIT,Local counter B initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0164++0x03
|
|
line.long 0x00 "LCNT_B_OVF,Local counter B overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0168++0x03
|
|
line.long 0x00 "LCNT_B_CFG,Local counter B configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04D016C++0x03
|
|
line.long 0x00 "LCNT_B_EN,Local counter B enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
|
|
group ad:0xF04D0170++0x03
|
|
line.long 0x00 "LCNT_B,LCNT_B TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D0174++0x03
|
|
line.long 0x00 "LCNT_B_HOLD,LCNT_B Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04D0178++0x03
|
|
line.long 0x00 "LCNT_B_DIFF,LCNT_B DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D0180++0x03
|
|
line.long 0x00 "LCNT_C_INIT,Local counter C initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0184++0x03
|
|
line.long 0x00 "LCNT_C_OVF,Local counter C overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D0188++0x03
|
|
line.long 0x00 "LCNT_C_CFG,Local counter C configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04D018C++0x03
|
|
line.long 0x00 "LCNT_C_EN,Local counter C enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
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|
group ad:0xF04D0190++0x03
|
|
line.long 0x00 "LCNT_C,LCNT_C TIMER"
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|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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|
group ad:0xF04D0194++0x03
|
|
line.long 0x00 "LCNT_C_HOLD,LCNT_C Hold Register"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
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|
group ad:0xF04D0198++0x03
|
|
line.long 0x00 "LCNT_C_DIFF,LCNT_C DIff Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D01A0++0x03
|
|
line.long 0x00 "LCNT_D_INIT,Local counter D initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D01A4++0x03
|
|
line.long 0x00 "LCNT_D_OVF,Local counter D overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04D01A8++0x03
|
|
line.long 0x00 "LCNT_D_CFG,Local counter D configuration register."
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|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
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|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
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|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
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|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
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|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04D01AC++0x03
|
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line.long 0x00 "LCNT_D_EN,Local counter D enable register"
|
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
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|
group ad:0xF04D01B0++0x03
|
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line.long 0x00 "LCNT_D,LCNT_D TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04D01B4++0x03
|
|
line.long 0x00 "LCNT_D_HOLD,LCNT_D Hold Register"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
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group ad:0xF04D01B8++0x03
|
|
line.long 0x00 "LCNT_D_DIFF,LCNT_D DIff Register"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
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group ad:0xF04D01C0++0x03
|
|
line.long 0x00 "CPT_A_CPT0_CNT0,Capture A capture 0 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
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group ad:0xF04D01C4++0x03
|
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line.long 0x00 "CPT_A_CPT0_CNT1,Capture A capture 0 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
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group ad:0xF04D01C8++0x03
|
|
line.long 0x00 "CPT_A_CPT1_CNT0,Capture A capture 1 counter 0 Register"
|
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
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group ad:0xF04D01CC++0x03
|
|
line.long 0x00 "CPT_A_CPT1_CNT1,Capture A capture 1 counter 1 Register"
|
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
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group ad:0xF04D01D0++0x03
|
|
line.long 0x00 "CPT_B_CPT0_CNT0,Capture B capture 0 counter 0 Register"
|
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01D4++0x03
|
|
line.long 0x00 "CPT_B_CPT0_CNT1,Capture B capture 0 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
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group ad:0xF04D01D8++0x03
|
|
line.long 0x00 "CPT_B_CPT1_CNT0,Capture B capture 1 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01DC++0x03
|
|
line.long 0x00 "CPT_B_CPT1_CNT1,Capture B capture 1 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01E0++0x03
|
|
line.long 0x00 "CPT_C_CPT0_CNT0,Capture C capture 0 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01E4++0x03
|
|
line.long 0x00 "CPT_C_CPT0_CNT1,Capture C capture 0 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01E8++0x03
|
|
line.long 0x00 "CPT_C_CPT1_CNT0,Capture C capture 1 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01EC++0x03
|
|
line.long 0x00 "CPT_C_CPT1_CNT1,Capture C capture 1 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01F0++0x03
|
|
line.long 0x00 "CPT_D_CPT0_CNT0,Capture D capture 0 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01F4++0x03
|
|
line.long 0x00 "CPT_D_CPT0_CNT1,Capture D capture 0 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01F8++0x03
|
|
line.long 0x00 "CPT_D_CPT1_CNT0,Capture D capture 1 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D01FC++0x03
|
|
line.long 0x00 "CPT_D_CPT1_CNT1,Capture D capture 1 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04D0200++0x03
|
|
line.long 0x00 "CPT_A_CONFIG,Capture A channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
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|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
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bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04D0204++0x03
|
|
line.long 0x00 "CPT_B_CONFIG,Capture B channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04D0208++0x03
|
|
line.long 0x00 "CPT_C_CONFIG,Capture C channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04D020C++0x03
|
|
line.long 0x00 "CPT_D_CONFIG,Capture D channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04D0210++0x03
|
|
line.long 0x00 "CPT_CTRL,Capture control register"
|
|
bitfld.long 0x00 7. " CPT_D_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
|
|
bitfld.long 0x00 6. " CPT_C_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
|
|
bitfld.long 0x00 5. " CPT_B_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
|
|
bitfld.long 0x00 4. " CPT_A_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
bitfld.long 0x00 2. " CPT_C_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
bitfld.long 0x00 1. " CPT_B_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
bitfld.long 0x00 0. " CPT_A_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
group ad:0xF04D0220++0x03
|
|
line.long 0x00 "CMP_A_CONFIG,Compare A channel configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
|
|
bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
|
bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
|
|
bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
|
|
group ad:0xF04D0224++0x03
|
|
line.long 0x00 "CMP_A_EVENT_OUT_MODE,Compare A channel event output mode register"
|
|
bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF04D0228++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID0,Compare A channel output pulse width register0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
|
|
group ad:0xF04D022C++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID1,Compare A channel output pulse width register1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
|
|
group ad:0xF04D0230++0x03
|
|
line.long 0x00 "CMP_A_00_VAL,Compare value for compare A channel cmp00 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04D0234++0x03
|
|
line.long 0x00 "CMP_A_01_VAL,Compare value for compare A channel cmp01 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04D0238++0x03
|
|
line.long 0x00 "CMP_A_10_VAL,Compare value for compare A channel cmp10 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04D023C++0x03
|
|
line.long 0x00 "CMP_A_11_VAL,Compare value for compare A channel cmp11 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04D0240++0x03
|
|
line.long 0x00 "CMP_A_DITHER,Compare A channel DIther register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04D0244++0x03
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line.long 0x00 "CMP_A_OFFSET,Compare A offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04D0248++0x03
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line.long 0x00 "CMP_A_EID,Compare A channel event ID register"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,CMP11 event ID"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,CMP10 event ID"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,CMP01 event ID"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,CMP00 event ID"
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group ad:0xF04D0250++0x03
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line.long 0x00 "CMP_B_CONFIG,Compare B channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use.In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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|
textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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|
bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04D0254++0x03
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line.long 0x00 "CMP_B_EVENT_OUT_MODE,Compare B channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04D0258++0x03
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line.long 0x00 "CMP_B_PULSE_WID0,Compare B channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04D025C++0x03
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line.long 0x00 "CMP_B_PULSE_WID1,Compare B channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04D0260++0x03
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line.long 0x00 "CMP_B_00_VAL,Compare value for compare B channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04D0264++0x03
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line.long 0x00 "CMP_B_01_VAL,Compare value for compare B channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04D0268++0x03
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line.long 0x00 "CMP_B_10_VAL,Compare value for compare B channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04D026C++0x03
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line.long 0x00 "CMP_B_11_VAL,Compare value for compare B channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04D0270++0x03
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line.long 0x00 "CMP_B_DITHER,Compare B channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04D0274++0x03
|
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line.long 0x00 "CMP_B_OFFSET,Compare B offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04D0280++0x03
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line.long 0x00 "CMP_C_CONFIG,Compare C channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04D0284++0x03
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line.long 0x00 "CMP_C_EVENT_OUT_MODE,Compare C channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04D0288++0x03
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line.long 0x00 "CMP_C_PULSE_WID0,Compare C channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04D028C++0x03
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line.long 0x00 "CMP_C_PULSE_WID1,Compare C channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04D0290++0x03
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line.long 0x00 "CMP_C_00_VAL,Compare value for compare C channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04D0294++0x03
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line.long 0x00 "CMP_C_01_VAL,Compare value for compare C channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04D0298++0x03
|
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line.long 0x00 "CMP_C_10_VAL,Compare value for compare C channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04D029C++0x03
|
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line.long 0x00 "CMP_C_11_VAL,Compare value for compare C channel cmp11 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04D02A0++0x03
|
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line.long 0x00 "CMP_C_DITHER,Compare C channel DIther register"
|
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04D02A4++0x03
|
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line.long 0x00 "CMP_C_OFFSET,Compare C offset value register"
|
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
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group ad:0xF04D02B0++0x03
|
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line.long 0x00 "CMP_D_CONFIG,Compare D channel configuration register"
|
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
|
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
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textline " "
|
|
bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04D02B4++0x03
|
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line.long 0x00 "CMP_D_EVENT_OUT_MODE,Compare D channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
|
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04D02B8++0x03
|
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line.long 0x00 "CMP_D_PULSE_WID0,Compare D channel output pulse width register0"
|
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
|
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
|
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04D02BC++0x03
|
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line.long 0x00 "CMP_D_PULSE_WID1,Compare D channel output pulse width register1"
|
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
|
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group ad:0xF04D02C0++0x03
|
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line.long 0x00 "CMP_D_00_VAL,Compare value for compare D channel cmp00 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
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group ad:0xF04D02C4++0x03
|
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line.long 0x00 "CMP_D_01_VAL,Compare value for compare D channel cmp01 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
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group ad:0xF04D02C8++0x03
|
|
line.long 0x00 "CMP_D_10_VAL,Compare value for compare D channel cmp10 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
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group ad:0xF04D02CC++0x03
|
|
line.long 0x00 "CMP_D_11_VAL,Compare value for compare D channel cmp11 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
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group ad:0xF04D02D0++0x03
|
|
line.long 0x00 "CMP_D_DITHER,Compare D channel DIther register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
|
|
group ad:0xF04D02D4++0x03
|
|
line.long 0x00 "CMP_D_OFFSET,Compare D offset value register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
|
group ad:0xF04D02E0++0x03
|
|
line.long 0x00 "CMP_CTRL,Compare control register"
|
|
bitfld.long 0x00 28. " CMP_A_EID_UPD ,Update EID value. Will be auto clear after completing update EID value." "0,1"
|
|
bitfld.long 0x00 27. " CMP_D1_INIT_UPD ,Update cmp_d1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 26. " CMP_D0_INIT_UPD ,Update cmp_d0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 25. " CMP_C1_INIT_UPD ,Update cmp_c1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 24. "CMP_C0_INIT_UPD ,Update cmp_c0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 23. " CMP_B1_INIT_UPD ,Update cmp_b1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 22. " CMP_B0_INIT_UPD ,Update cmp_b0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 21. " CMP_A1_INIT_UPD ,Update cmp_a1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 20. "CMP_A0_INIT_UPD ,Update cmp_a0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 19. " CMP_D1_INIT_STATUS ,cmp_d1 output initial status" "0,1"
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bitfld.long 0x00 18. " CMP_D0_INIT_STATUS ,cmp_d0 output initial status" "0,1"
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bitfld.long 0x00 17. " CMP_C1_INIT_STATUS ,cmp_c1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 16. "CMP_C0_INIT_STATUS ,cmp_c0 output initial status" "0,1"
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bitfld.long 0x00 15. " CMP_B1_INIT_STATUS ,cmp_b1 output initial status" "0,1"
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bitfld.long 0x00 14. " CMP_B0_INIT_STATUS ,cmp_b0 output initial status" "0,1"
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bitfld.long 0x00 13. " CMP_A1_INIT_STATUS ,cmp_a1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 12. "CMP_A0_INIT_STATUS ,cmp_a0 output initial status" "0,1"
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bitfld.long 0x00 11. " CMP_D_VAL_UPD ,Update all the compare value registers for compare D channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 10. " CMP_C_VAL_UPD ,Update all the compare value registers for compare C channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 9. " CMP_B_VAL_UPD ,Update all the compare value registers for compare B channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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textline " "
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bitfld.long 0x00 8. "CMP_A_VAL_UPD ,Update all the compare value registers for compare A channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 7. " CMP_D_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CMP_C_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 5. " CMP_B_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour.." "0,1"
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textline " "
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bitfld.long 0x00 4. "CMP_A_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 3. " CMP_D_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 2. " CMP_C_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 1. " CMP_B_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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textline " "
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bitfld.long 0x00 0. "CMP_A_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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group ad:0xF04D0300++0x03
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line.long 0x00 "CPT_A_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_A0 signals into one signal for capture channel A"
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bitfld.long 0x00 26. " QUAD_INDEX_POL ,When this bit is set, INDEX signal polarity is changed." "0,1"
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bitfld.long 0x00 25. " QUAD_HOME_POL ,When this bit is set, HOME signal polarity is changed." "0,1"
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bitfld.long 0x00 21.--24. " QUAD_CLR_SEL ,In quadrature mode, the counter CLR event can be configured to be initiated by HOME or INDEX input 0000: HOME high 0001: INDEX high 0010: HOME high and {PHASE_B, PHASE_A} = 2'b00; 0011: HOME high and {PHASE_B, PHASE_A} = 2'.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 17.--20. " QUAD_SET_SEL ,In quadrature mode, the counter SET event can be configured to be initiated by HOME or INDEX input 0000: HOME high 0001: INDEX high 0010: HOME high and {PHASE_B, PHASE_A} = 2'b00; 0011: HOME high and {PHASE_B, PHASE_A} = 2'.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 16. "QUAD_MODE_EN ,Quadrature mode enable" "0,1"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04D0304++0x03
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line.long 0x00 "CPT_A_SSE_REG,Signal synthesis for CAPTURE A"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04D0308++0x03
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line.long 0x00 "CPT_B_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_B0 signals into one signal for capture channel B"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04D030C++0x03
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line.long 0x00 "CPT_B_SSE_REG,Signal synthesis for CAPTURE B"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04D0310++0x03
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line.long 0x00 "CPT_C_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_C0 signals into one signal for capture channel C"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04D0314++0x03
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line.long 0x00 "CPT_C_SSE_REG,Signal synthesis for CAPTURE C"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04D0318++0x03
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line.long 0x00 "CPT_D_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_D0 signals into one signal for capture channel D"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04D031C++0x03
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line.long 0x00 "CPT_D_SSE_REG,Signal synthesis for CAPTURE D"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04D0320++0x03
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line.long 0x00 "CMP_A_SSE_CTRL,Synthesis CMP_A0,CMP_B0,CMP_C0 and CMP_D0 outputs and CPT_A_SSE SO signals into one signal for compare channel A"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_A_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04D0324++0x03
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line.long 0x00 "CMP_A_SSE_REG,Signal synthesis for compare A output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04D0328++0x03
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line.long 0x00 "CMP_B_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_B_SSE SO signals into one signal for compare channel B"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_B_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04D032C++0x03
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line.long 0x00 "CMP_B_SSE_REG,Signal synthesis for compare B output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04D0330++0x03
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line.long 0x00 "CMP_C_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_C_SSE SO signals into one signal for compare channel C"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_C_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04D0334++0x03
|
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line.long 0x00 "CMP_C_SSE_REG,Signal synthesis for compare C output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04D0338++0x03
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line.long 0x00 "CMP_D_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_D_SSE SO signals into one signal for compare channel D"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_D_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04D033C++0x03
|
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line.long 0x00 "CMP_D_SSE_REG,Signal synthesis for compare D output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04D0340++0x03
|
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line.long 0x00 "CPT_A_INPUT_SEL,Capture A channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_A1 1000: CMP_A1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_A_SSE_SO 0001: CPT_A1 0010: CMP_A1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_A_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_A_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D0344++0x03
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line.long 0x00 "CPT_B_INPUT_SEL,Capture B channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_B1 1000: CMP_B1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_B_SSE_SO 0001: CPT_B1 0010: CMP_B1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_B_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_B_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D0348++0x03
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line.long 0x00 "CPT_C_INPUT_SEL,Capture C channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_C1 1000: CMP_C1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_C_SSE_SO 0001: CPT_C1 0010: CMP_C1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_C_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_C_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D034C++0x03
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line.long 0x00 "CPT_D_INPUT_SEL,Capture D channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_D1 1000: CMP_D1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_D_SSE_SO 0001: CPT_D1 0010: CMP_D1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_D_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_D_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D0350++0x03
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line.long 0x00 "CMP_A_INPUT_SEL,Compare A channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D0354++0x03
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line.long 0x00 "CMP_B_INPUT_SEL,Compare B channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D0358++0x03
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line.long 0x00 "CMP_C_INPUT_SEL,Compare C channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D035C++0x03
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line.long 0x00 "CMP_D_INPUT_SEL,Compare D channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D0360++0x03
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line.long 0x00 "CNT_G0_INPUT_SEL,Counter G0 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D0364++0x03
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line.long 0x00 "CNT_G1_INPUT_SEL,Counter G1 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D0368++0x03
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line.long 0x00 "EXT_OUTPUT_SEL,External output source select register"
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bitfld.long 0x00 8.--11. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_A1 1000: CPT_B1 1001: CPT_C1 1010: CPT_D1 1011: CMP_A1 1100: SW_TRIG0.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04D036C++0x03
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line.long 0x00 "ETM_POL_INV,Event trigger polarity invert"
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bitfld.long 0x00 30. " EXT_DIR ,Polarity invert" "0,1"
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bitfld.long 0x00 29. " EXT_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 28. " EXT_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 27. " CNT_G1_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 26. "CNT_G1_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 25. " CNT_G0_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 24. " CNT_G0_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 23. " CMP_D_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 22. "CMP_D_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 21. " CMP_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 20. " CMP_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 19. " CMP_B_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 18. "CMP_B_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 17. " CMP_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 16. " CMP_A_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 15. " CPT_D_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 14. "CPT_D_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 13. " CPT_D_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 12. " CPT_D_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 11. " CPT_C_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 10. "CPT_C_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 9. " CPT_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 8. " CPT_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 7. " CPT_B_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 6. "CPT_B_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 5. " CPT_B_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 4. " CPT_B_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 3. " CPT_A_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 2. "CPT_A_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 1. " CPT_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 0. " CPT_A_SET ,Polarity invert" "0,1"
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group ad:0xF04D0370++0x03
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line.long 0x00 "CPT_SW_TRIG,Capture signal software trigger register"
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bitfld.long 0x00 11. " CPT_D_SIG ,Set high to generate SIG pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 10. " CPT_C_SIG ,Set high to generate SIG pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 9. " CPT_B_SIG ,Set high to generate SIG pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 8. " CPT_A_SIG ,Set high to generate SIG pulse signal for capture A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 7. "CPT_D_CLR ,Set high to generate CLR pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CPT_C_CLR ,Set high to generate CLR pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CPT_B_CLR ,Set high to generate CLR pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CPT_A_CLR ,Set high to generate CLR pulse signal for capture A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CPT_D_SET ,Set high to generate SET pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CPT_C_SET ,Set high to generate SET pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CPT_B_SET ,Set high to generate SET pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CPT_A_SET ,Set high to generate SET pulse signal for capture A channel. Auto clear after set." "0,1"
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group ad:0xF04D0374++0x03
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line.long 0x00 "CMP_SW_TRIG,Compare signal software trigger register"
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bitfld.long 0x00 7. " CMP_D_CLR ,Set high to generate CLR pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CMP_C_CLR ,Set high to generate CLR pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CMP_B_CLR ,Set high to generate CLR pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CMP_A_CLR ,Set high to generate CLR pulse signal for compare A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CMP_D_SET ,Set high to generate SET pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CMP_C_SET ,Set high to generate SET pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CMP_B_SET ,Set high to generate SET pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CMP_A_SET ,Set high to generate SET pulse signal for compare A channel. Auto clear after set." "0,1"
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group ad:0xF04D0378++0x03
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line.long 0x00 "CNT_EXT_SW_TRIG,Counter and external signal software trigger register"
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bitfld.long 0x00 5. " EXT_CLR ,Set high to generate CLR pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " EXT_SET ,Set high to generate SET pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 3. " CNT_G1_CLR ,Set high to generate CLR pulse signal for CNT_G1. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CNT_G1_SET ,Set high to generate SET pulse signal for CNT_G1. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 1. "CNT_G0_CLR ,Set high to generate CLR pulse signal for CNT_G0. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CNT_G0_SET ,Set high to generate SET pulse signal for CNT_G0. Auto clear after set." "0,1"
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group ad:0xF04D0380++0x03
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line.long 0x00 "SW_TRIG_CTRL,SW trigger event generation control"
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bitfld.long 0x00 15. " SW_TRIG3_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 14. " SW_TRIG3_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 13. " SW_TRIG3_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 12. " SW_TRIG3_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 11. "SW_TRIG2_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 10. " SW_TRIG2_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 9. " SW_TRIG2_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 8. " SW_TRIG2_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 7. "SW_TRIG1_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 6. " SW_TRIG1_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 5. " SW_TRIG1_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 4. " SW_TRIG1_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 3. "SW_TRIG0_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 2. " SW_TRIG0_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 1. " SW_TRIG0_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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group ad:0xF04D0384++0x03
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line.long 0x00 "SW_TRIG_STATUS,SW trigger outputs status"
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bitfld.long 0x00 3. " SW_TRIG3 ,SW trigger output" "0,1"
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bitfld.long 0x00 2. " SW_TRIG2 ,SW trigger output" "0,1"
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bitfld.long 0x00 1. " SW_TRIG1 ,SW trigger output" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0 ,SW trigger output" "0,1"
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group ad:0xF04D0388++0x03
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line.long 0x00 "SW_TRIG_PULSE0,SW trigger0 and trigger1 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG1_WIDTH ,Pulse width of SW trigger1"
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hexmask.long.word 0x00 0.--15. 1. " TRIG0_WIDTH ,Pulse width of SW trigger0"
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group ad:0xF04D038C++0x03
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line.long 0x00 "SW_TRIG_PULSE1,SW trigger2 and trigger3 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG3_WIDTH ,Pulse width of SW trigger3"
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hexmask.long.word 0x00 0.--15. 1. " TRIG2_WIDTH ,Pulse width of SW trigger2"
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group ad:0xF04D0390++0x03
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line.long 0x00 "CNT_G0_SNAP_SHOT_SEL,CNT_G0 snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04D0394++0x03
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line.long 0x00 "CNT_G1_SNAP_SHOT_SEL,CNT_G1 snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04D0398++0x03
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line.long 0x00 "LCNT_A_SNAP_SHOT_SEL,LCNT_A snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04D039C++0x03
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line.long 0x00 "LCNT_B_SNAP_SHOT_SEL,LCNT_B snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04D03A0++0x03
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line.long 0x00 "LCNT_C_SNAP_SHOT_SEL,LCNT_C snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04D03A4++0x03
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line.long 0x00 "LCNT_D_SNAP_SHOT_SEL,LCNT_D snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04D03A8++0x03
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line.long 0x00 "SNAP_SHOT_O_SEL,Snapshot output snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04D0400++0x03
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line.long 0x00 "CPT_A0_FLT,Filter setting for CPT_A0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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|
textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04D0404++0x03
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line.long 0x00 "CPT_B0_FLT,Filter setting for CPT_B0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04D0408++0x03
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line.long 0x00 "CPT_C0_FLT,Filter setting for CPT_C0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04D040C++0x03
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line.long 0x00 "CPT_D0_FLT,Filter setting for CPT_D0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04D0410++0x03
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line.long 0x00 "FAULT0_FLT,Filter setting for fault0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04D0414++0x03
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line.long 0x00 "FAULT1_FLT,Filter setting for fault1 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04D0418++0x03
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line.long 0x00 "FAULT2_FLT,Filter setting for fault2 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04D041C++0x03
|
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line.long 0x00 "FAULT3_FLT,Filter setting for fault3 input."
|
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04D0420++0x03
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line.long 0x00 "SYNC_DIS,Synchronization DIsable control register"
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bitfld.long 0x00 15. " FAULT3 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 14. " FAULT2 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 13. " FAULT1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 12. " FAULT0 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 10. "SNAP_SHOT ,DIsable synchronization" "0,1"
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bitfld.long 0x00 9. " EXT_CLR ,DIsable synchronization" "0,1"
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bitfld.long 0x00 8. " EXT_SET ,DIsable synchronization" "0,1"
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bitfld.long 0x00 7. " CPT_D1 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 6. "CPT_C1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 5. " CPT_B1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 4. " CPT_A1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 3. " CPT_D0 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 2. "CPT_C0 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 1. " CPT_B0 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 0. " CPT_A0 ,DIsable synchronization" "0,1"
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group ad:0xF04D0440++0x03
|
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line.long 0x00 "CMP_A_FAULT_EVENT_CTRL,Compare A channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
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group ad:0xF04D0444++0x03
|
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line.long 0x00 "CMP_B_FAULT_EVENT_CTRL,Compare B channel event control register"
|
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04D0448++0x03
|
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line.long 0x00 "CMP_C_FAULT_EVENT_CTRL,Compare C channel event control register"
|
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04D044C++0x03
|
|
line.long 0x00 "CMP_D_FAULT_EVENT_CTRL,Compare D channel event control register"
|
|
bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04D0460++0x03
|
|
line.long 0x00 "CMP_A_DTI_CTRL,Dead time insertion control register for compare A channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04D0464++0x03
|
|
line.long 0x00 "CMP_A_DTI_WID,Dead time insertion width register for compare A channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04D0468++0x03
|
|
line.long 0x00 "CMP_B_DTI_CTRL,Dead time insertion control register for compare B channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04D046C++0x03
|
|
line.long 0x00 "CMP_B_DTI_WID,Dead time insertion width register for compare B channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04D0470++0x03
|
|
line.long 0x00 "CMP_C_DTI_CTRL,Dead time insertion control register for compare C channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04D0474++0x03
|
|
line.long 0x00 "CMP_C_DTI_WID,Dead time insertion width register for compare C channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04D0478++0x03
|
|
line.long 0x00 "CMP_D_DTI_CTRL,Dead time insertion control register for compare D channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04D047C++0x03
|
|
line.long 0x00 "CMP_D_DTI_WID,Dead time insertion width register for compare D channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04D0500++0x03
|
|
line.long 0x00 "SIGNAL_STATUS,Signal status register"
|
|
bitfld.long 0x00 31. " CPT_D_CLR ,Capture D clear signal" "0,1"
|
|
bitfld.long 0x00 30. " CPT_D_SET ,Capture D set signal" "0,1"
|
|
bitfld.long 0x00 29. " CPT_D_DIR ,Capture D DIR signal" "0,1"
|
|
bitfld.long 0x00 28. " CPT_D_SIG ,Capture D SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "CPT_C_CLR ,Capture C clear signal" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_SET ,Capture C set signal" "0,1"
|
|
bitfld.long 0x00 25. " CPT_C_DIR ,Capture C DIR signal" "0,1"
|
|
bitfld.long 0x00 24. " CPT_C_SIG ,Capture C SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CPT_B_CLR ,Capture B clr signal" "0,1"
|
|
bitfld.long 0x00 22. " CPT_B_SET ,Capture B set signal" "0,1"
|
|
bitfld.long 0x00 21. " CPT_B_DIR ,Capture B DIR signal" "0,1"
|
|
bitfld.long 0x00 20. " CPT_B_SIG ,Capture B SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CPT_A_CLR ,Capture A clear signal" "0,1"
|
|
bitfld.long 0x00 18. " CPT_A_SET ,Capture A set signal" "0,1"
|
|
bitfld.long 0x00 17. " CPT_A_DIR ,Capture A DIR signal" "0,1"
|
|
bitfld.long 0x00 16. " CPT_A_SIG ,Capture A SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_CLR ,Compare D clear signal" "0,1"
|
|
bitfld.long 0x00 14. " CMP_D_SET ,Compare D set signal" "0,1"
|
|
bitfld.long 0x00 13. " CMP_C_CLR ,Compare C clear signal" "0,1"
|
|
bitfld.long 0x00 12. " CMP_C_SET ,Compare C set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_B_CLR ,Compare B clear signal" "0,1"
|
|
bitfld.long 0x00 10. " CMP_B_SET ,Compare B set signal" "0,1"
|
|
bitfld.long 0x00 9. " CMP_A_CLR ,Compare A clear signal" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A_SET ,Compare A set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D1 ,Compare D1 signal" "0,1"
|
|
bitfld.long 0x00 6. " CMP_D0 ,Compare D0 signal" "0,1"
|
|
bitfld.long 0x00 5. " CMP_C1 ,Compare C1 signal" "0,1"
|
|
bitfld.long 0x00 4. " CMP_C0 ,Compare C0 signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CMP_B1 ,Compare B1 signal" "0,1"
|
|
bitfld.long 0x00 2. " CMP_B0 ,Compare B0 signal" "0,1"
|
|
bitfld.long 0x00 1. " CMP_A1 ,Compare A1 signal" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A0 ,Compare A0 signal" "0,1"
|
|
group ad:0xF04D0FFC++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
tree.end
|
|
tree "ETIMER3"
|
|
width 28.
|
|
group ad:0xF04E0000++0x03
|
|
line.long 0x00 "INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,LCNT_D snapshot event happens" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,LCNT_C snapshot event happens" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,LCNT_B snapshot event happens" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,LCNT_A snapshot event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,CNT_G1 snapshot event happens" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,CNT_G0 snapshot event happens" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,CNT_LOCAL_D overflow" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,CNT_LOCAL_C overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,CNT_LOCAL_B overflow" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,CNT_LOCAL_A overflow" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,CNT_G1 overflow" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,CNT_G0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Compare D event happens" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Compare C event happens" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Compare B event happens" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Compare A event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Capture D event happens" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Capture C event happens" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Capture B event happens" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Capture A event happens" "0,1"
|
|
group ad:0xF04E0004++0x03
|
|
line.long 0x00 "INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Status enable" "0,1"
|
|
group ad:0xF04E0008++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt singal enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Singal enable" "0,1"
|
|
group ad:0xF04E000C++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA,Correctable error interrupt status register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,CPT D vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,CPT C vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,CPT B vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,CPT A vaule is not fetched" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,FIFO D overrun" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,FIFO C overrun" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,FIFO B overrun" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,FIFO A overrun" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04E0010++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA_EN,Correctable error interrupt status enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04E0014++0x03
|
|
line.long 0x00 "COR_ERR_INT_SIG_EN,Correctable error interrupt singal enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04E0018++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA,Uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,CPT D vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,CPT C vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,CPT B vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,CPT A vaule is not fetched" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,FIFO D overrun" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,FIFO C overrun" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,FIFO B overrun" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,FIFO A overrun" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04E001C++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04E0020++0x03
|
|
line.long 0x00 "UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt singal enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04E0024++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata corrctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04E0028++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04E002C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04E0030++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Cock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Cock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error." "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error." "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error." "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04E0034++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04E0038++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error." "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error." "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,CONFIG_DMA eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04E003C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_1,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04E0040++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN_1,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04E0044++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN_1,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,CONFIG_DMA eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04E004C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF04E0050++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF04E0054++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF04E005C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF04E0060++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,RAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04E0064++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04E0068++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,RAM B rdata monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04E006C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,RAM B rdata ECC monitorerror injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04E0070++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF04E0074++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF04E0080++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 16.--18. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF04E0084++0x03
|
|
line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04E0088++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04E008C++0x03
|
|
line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04E0090++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 6. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
|
bitfld.long 0x00 5. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
|
bitfld.long 0x00 4. " CNT_OVF ,Counter overflow and snapshot interrupt error injection." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Channel D interrupt error injection." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CHN_C ,Channel C interrupt error injection." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B ,Channel B interrupt error injection." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Channel A interrupt error injection." "0,1"
|
|
group ad:0xF04E0094++0x03
|
|
line.long 0x00 "CLK_MON_CMP_ERR_INJ,Clock monitor compare error injection r"
|
|
bitfld.long 0x00 2.--3. " ERR1 ,Clock monitor 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ERR0 ,Clock monitor 0" "0,1,2,3"
|
|
group ad:0xF04E00A0++0x03
|
|
line.long 0x00 "TIM_CLK_CONFIG,Timer clock select and DIvider configuration."
|
|
bitfld.long 0x00 31. " CLK_CHANGE_UPD ,Set this bit to make new DIV_NUM/SRC_CLK_SEL value effective. Will be auto cleared after new DIV_NUM/SRC_CLK_SEL is effective" "0,1"
|
|
bitfld.long 0x00 16.--17. " SRC_CLK_SEL ,Clock source select. 00: High frequency(HF) clock, update to 400mhz. 01: Alternative High frequency(AHF) clock, update to 400mhz. 10: External clock. 11: Low power(LP) clock, typically from low speed on chip RCOSC." "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV_NUM ,DIvider number for timer clock."
|
|
group ad:0xF04E00A4++0x03
|
|
line.long 0x00 "CLK_MON_EN,Clock monitor enable register"
|
|
bitfld.long 0x00 2. " CMP_SET ,When enable or DIsable clock monitor, set this bit together. This bit is used to inDIcate configuration is completed." "0,1"
|
|
bitfld.long 0x00 1. " EN_N ,Active low. Enable clock monitor1" "0,1"
|
|
bitfld.long 0x00 0. " EN_P ,Active high.Enable clock monitor0" "0,1"
|
|
group ad:0xF04E00A8++0x03
|
|
line.long 0x00 "SW_RST,Software reset"
|
|
bitfld.long 0x00 5. " CNT_G1 ,Reset CNT_G1.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0 ,Reset CNT_G0.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Reset channel D. Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 2. " CHN_C ,Reset channel C.Will be auto cleared after reset complete." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CHN_B ,Reset channel B.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Reset channel A.Will be auto cleared after reset complete." "0,1"
|
|
group ad:0xF04E00B0++0x03
|
|
line.long 0x00 "CHN_DMA_CTRL,Channel DMA control register"
|
|
bitfld.long 0x00 19. " CHN_D_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 18. " CHN_C_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 17. " CHN_B_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 16. " CHN_A_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CHN_D_SIG_MASK ,Mask channel D dma request hardware output" "0,1"
|
|
bitfld.long 0x00 14. " CHN_C_SIG_MASK ,Mask channel C dma request hardware output" "0,1"
|
|
bitfld.long 0x00 13. " CHN_B_SIG_MASK ,Mask channel B dma request hardware output" "0,1"
|
|
bitfld.long 0x00 12. " CHN_A_SIG_MASK ,Mask channel A dma request hardware output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "CHN_D_SEL ,Select dma request working for CAPTURE D/COMPARE D channel 1x: Use for CPT_CMP delay mode D 01: Use for capture channel D. 00: Use for compare channel D." "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " CHN_C_SEL ,Select dma request working for CAPTURE C/COMPARE C channel 1x: Use for CPT_CMP delay mode C 01: Use for capture channel C. 00: Use for compare channel C." "0,1,2,3"
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bitfld.long 0x00 6.--7. " CHN_B_SEL ,Select dma request working for CAPTURE B/COMPARE B channel 1x: Use for CPT_CMP delay mode B 01: Use for capture channel B. 00: Use for compare channel B." "0,1,2,3"
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bitfld.long 0x00 4.--5. " CHN_A_SEL ,Select dma request working for CAPTURE A/COMPARE A channel 1x: Use for CPT_CMP delay mode A 01: Use for capture channel A. 00: Use for compare channel A." "0,1,2,3"
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|
textline " "
|
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bitfld.long 0x00 3. "CHN_D_EN ,Enable dma request for CAPTURE D/COMPARE D channel accorDIng to channel D FIFO WML." "0,1"
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bitfld.long 0x00 2. " CHN_C_EN ,Enable dma request for CAPTURE C/COMPARE C channel accorDIng to channel C FIFO WML." "0,1"
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bitfld.long 0x00 1. " CHN_B_EN ,Enable dma request for CAPTURE B/COMPARE B channel accorDIng to channel B FIFO WML." "0,1"
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bitfld.long 0x00 0. " CHN_A_EN ,Enable dma request for CAPTURE A/COMPARE A channel accorDIng to channle A FIFO WML." "0,1"
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group ad:0xF04E00B4++0x03
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line.long 0x00 "DMA_WML,DMA watermark leverl register"
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bitfld.long 0x00 24.--27. " CHN_D ,Waterwark level setting for channel D DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CHN_C ,Waterwark level setting for channel C DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " CHN_B ,Waterwark level setting for channel B DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " CHN_A ,Waterwark level setting for channel A DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E00B8++0x03
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line.long 0x00 "CONFIG_DMA_CTL,Configuration dma control register"
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hexmask.long.word 0x00 2.--15. 1. " TRIG_SEL ,Select source to trigger dma request. 1. CMP_A_CE 2. CMP_B_CE 3. CMP_C_CE 4. CMP_D_CE 5. CPT_A_CE 6. CPT_B_CE 7. CPT_C_CE 8. CPT_D_CE 9. CNT_G0_CE 10. CNT_G1_CE 11. LCNT_A_CE 12. LCNT_B_CE 13. LCNT_C_CE 14. LCNT_D_CE.."
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bitfld.long 0x00 1. " SIG_MASK ,Mask configuration dma request hardware output" "0,1"
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bitfld.long 0x00 0. " EN ,DMA enable for register configuration" "0,1"
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group ad:0xF04E00BC++0x03
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line.long 0x00 "FIFO_REQ_STATUS,FIFO request status"
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bitfld.long 0x00 3. " CHN_D ,Channel D FIFO reach water mark level" "0,1"
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bitfld.long 0x00 2. " CHN_C ,Channel C FIFO reach water mark level" "0,1"
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bitfld.long 0x00 1. " CHN_B ,Channel B FIFO reach water mark level" "0,1"
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bitfld.long 0x00 0. " CHN_A ,Channel A FIFO reach water mark level" "0,1"
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group ad:0xF04E00C0++0x03
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line.long 0x00 "FIFO_A,FIFO_entry for capture and compare channel A"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04E00C4++0x03
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line.long 0x00 "FIFO_B,FIFO_entry for capture and compare channel B"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04E00C8++0x03
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line.long 0x00 "FIFO_C,FIFO_entry for capture and compare channel C"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04E00CC++0x03
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line.long 0x00 "FIFO_D,FIFO_entry for capture and compare channel D"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04E00D0++0x03
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line.long 0x00 "FIFO_STA,FIFO status."
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bitfld.long 0x00 31. " FIFO_ERR_D ,InDIcate FIFO underrun or overrun." "0,1"
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bitfld.long 0x00 26.--30. " FIFO_ENTRIES_D ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 25. " FIFO_EMPTY_D ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 24. " FIFO_FULL_D ,InDIcate FIFO is full." "0,1"
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textline " "
|
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bitfld.long 0x00 23. "FIFO_ERR_C ,InDIcate FIFO underrun or overrun." "0,1"
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bitfld.long 0x00 18.--22. " FIFO_ENTRIES_C ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 17. " FIFO_EMPTY_C ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 16. " FIFO_FULL_C ,InDIcate FIFO is full." "0,1"
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textline " "
|
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bitfld.long 0x00 15. "FIFO_ERR_B ,InDIcate FIFO underrun or overrun." "0,1"
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bitfld.long 0x00 10.--14. " FIFO_ENTRIES_B ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 9. " FIFO_EMPTY_B ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 8. " FIFO_FULL_B ,InDIcate FIFO is full." "0,1"
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textline " "
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bitfld.long 0x00 7. "FIFO_ERR_A ,InDIcate FIFO underrun or overrun." "0,1"
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bitfld.long 0x00 2.--6. " FIFO_ENTRIES_A ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 1. " FIFO_EMPTY_A ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 0. " FIFO_FULL_A ,InDIcate FIFO is full." "0,1"
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group ad:0xF04E0100++0x03
|
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line.long 0x00 "CNT_G0_INIT,Counter G0 initial value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04E0104++0x03
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line.long 0x00 "CNT_G0_OVF,Counter G0 overflow value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04E0108++0x03
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line.long 0x00 "CNT_G0_CFG,CNT_G0 configuration register."
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bitfld.long 0x00 31. " CASCADE_MODE ,When this bit is set, CNT_G1 only increase when CNT_G0 is overflowed. In this setup, CNT_G0 can work as a 64 bit timer if CNT_G0_OVF_VAL is 32'hffffffff." "0,1"
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bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
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hexmask.long.byte 0x00 8.--15. 1. " INTERVAL ,Count enable interval."
|
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 3.--4. "SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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bitfld.long 0x00 1.--2. " SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04E010C++0x03
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line.long 0x00 "CNT_G0_EN,CNT_G0 enable register"
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
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group ad:0xF04E0110++0x03
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line.long 0x00 "CNT_G0,CNT_G0 TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04E0114++0x03
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line.long 0x00 "CNT_G0_HOLD,CNT_G0 Hold Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
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group ad:0xF04E0118++0x03
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line.long 0x00 "CNT_G0_DIFF,CNT_G0 DIff Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04E0120++0x03
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line.long 0x00 "CNT_G1_INIT,Counter G1 initial value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04E0124++0x03
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line.long 0x00 "CNT_G1_OVF,Counter G1 overflow value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04E0128++0x03
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line.long 0x00 "CNT_G1_CFG,CNT_G1 configuration register."
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bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW" "0,1"
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bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
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textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04E012C++0x03
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line.long 0x00 "CNT_G1_EN,CNT_G1 enable register"
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
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group ad:0xF04E0130++0x03
|
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line.long 0x00 "CNT_G1,CNT_G1 TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04E0134++0x03
|
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line.long 0x00 "CNT_G1_HOLD,CNT_G1 Hold Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
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group ad:0xF04E0138++0x03
|
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line.long 0x00 "CNT_G1_DIFF,CNT_G1 DIff Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
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group ad:0xF04E0140++0x03
|
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line.long 0x00 "LCNT_A_INIT,Local counter A initial value register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF04E0144++0x03
|
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line.long 0x00 "LCNT_A_OVF,Local counter A overflow value register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF04E0148++0x03
|
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line.long 0x00 "LCNT_A_CFG,Local counter A configuration register."
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bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
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bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
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bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
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bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
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bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
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bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
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textline " "
|
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bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04E014C++0x03
|
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line.long 0x00 "LCNT_A_EN,Local counter A enable register"
|
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
|
|
group ad:0xF04E0150++0x03
|
|
line.long 0x00 "LCNT_A,LCNT_A TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04E0154++0x03
|
|
line.long 0x00 "LCNT_A_HOLD,LCNT_A Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04E0158++0x03
|
|
line.long 0x00 "LCNT_A_DIFF,LCNT_A DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04E0160++0x03
|
|
line.long 0x00 "LCNT_B_INIT,Local counter B initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04E0164++0x03
|
|
line.long 0x00 "LCNT_B_OVF,Local counter B overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04E0168++0x03
|
|
line.long 0x00 "LCNT_B_CFG,Local counter B configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04E016C++0x03
|
|
line.long 0x00 "LCNT_B_EN,Local counter B enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
|
|
group ad:0xF04E0170++0x03
|
|
line.long 0x00 "LCNT_B,LCNT_B TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04E0174++0x03
|
|
line.long 0x00 "LCNT_B_HOLD,LCNT_B Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04E0178++0x03
|
|
line.long 0x00 "LCNT_B_DIFF,LCNT_B DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04E0180++0x03
|
|
line.long 0x00 "LCNT_C_INIT,Local counter C initial value register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04E0184++0x03
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line.long 0x00 "LCNT_C_OVF,Local counter C overflow value register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04E0188++0x03
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line.long 0x00 "LCNT_C_CFG,Local counter C configuration register."
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bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
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bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
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bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
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bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
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|
textline " "
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bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
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bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
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bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
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bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
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textline " "
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bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
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bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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textline " "
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04E018C++0x03
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line.long 0x00 "LCNT_C_EN,Local counter C enable register"
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
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group ad:0xF04E0190++0x03
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line.long 0x00 "LCNT_C,LCNT_C TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04E0194++0x03
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line.long 0x00 "LCNT_C_HOLD,LCNT_C Hold Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
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group ad:0xF04E0198++0x03
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line.long 0x00 "LCNT_C_DIFF,LCNT_C DIff Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04E01A0++0x03
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line.long 0x00 "LCNT_D_INIT,Local counter D initial value register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04E01A4++0x03
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line.long 0x00 "LCNT_D_OVF,Local counter D overflow value register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04E01A8++0x03
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line.long 0x00 "LCNT_D_CFG,Local counter D configuration register."
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bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
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bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
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bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
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bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
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textline " "
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bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
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bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
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bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
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bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
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textline " "
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bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
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bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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textline " "
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04E01AC++0x03
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line.long 0x00 "LCNT_D_EN,Local counter D enable register"
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
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group ad:0xF04E01B0++0x03
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line.long 0x00 "LCNT_D,LCNT_D TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04E01B4++0x03
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line.long 0x00 "LCNT_D_HOLD,LCNT_D Hold Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
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group ad:0xF04E01B8++0x03
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line.long 0x00 "LCNT_D_DIFF,LCNT_D DIff Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04E01C0++0x03
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line.long 0x00 "CPT_A_CPT0_CNT0,Capture A capture 0 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01C4++0x03
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line.long 0x00 "CPT_A_CPT0_CNT1,Capture A capture 0 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01C8++0x03
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line.long 0x00 "CPT_A_CPT1_CNT0,Capture A capture 1 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01CC++0x03
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line.long 0x00 "CPT_A_CPT1_CNT1,Capture A capture 1 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01D0++0x03
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line.long 0x00 "CPT_B_CPT0_CNT0,Capture B capture 0 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01D4++0x03
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line.long 0x00 "CPT_B_CPT0_CNT1,Capture B capture 0 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01D8++0x03
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line.long 0x00 "CPT_B_CPT1_CNT0,Capture B capture 1 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01DC++0x03
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line.long 0x00 "CPT_B_CPT1_CNT1,Capture B capture 1 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01E0++0x03
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line.long 0x00 "CPT_C_CPT0_CNT0,Capture C capture 0 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01E4++0x03
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line.long 0x00 "CPT_C_CPT0_CNT1,Capture C capture 0 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01E8++0x03
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line.long 0x00 "CPT_C_CPT1_CNT0,Capture C capture 1 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01EC++0x03
|
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line.long 0x00 "CPT_C_CPT1_CNT1,Capture C capture 1 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01F0++0x03
|
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line.long 0x00 "CPT_D_CPT0_CNT0,Capture D capture 0 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01F4++0x03
|
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line.long 0x00 "CPT_D_CPT0_CNT1,Capture D capture 0 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01F8++0x03
|
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line.long 0x00 "CPT_D_CPT1_CNT0,Capture D capture 1 counter 0 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E01FC++0x03
|
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line.long 0x00 "CPT_D_CPT1_CNT1,Capture D capture 1 counter 1 Register"
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
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group ad:0xF04E0200++0x03
|
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line.long 0x00 "CPT_A_CONFIG,Capture A channel configuration register"
|
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bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
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bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
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bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
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textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
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bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
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group ad:0xF04E0204++0x03
|
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line.long 0x00 "CPT_B_CONFIG,Capture B channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04E0208++0x03
|
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line.long 0x00 "CPT_C_CONFIG,Capture C channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04E020C++0x03
|
|
line.long 0x00 "CPT_D_CONFIG,Capture D channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04E0210++0x03
|
|
line.long 0x00 "CPT_CTRL,Capture control register"
|
|
bitfld.long 0x00 7. " CPT_D_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CPT_C_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
|
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bitfld.long 0x00 5. " CPT_B_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
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bitfld.long 0x00 4. " CPT_A_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
bitfld.long 0x00 2. " CPT_C_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
bitfld.long 0x00 1. " CPT_B_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
bitfld.long 0x00 0. " CPT_A_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
|
|
group ad:0xF04E0220++0x03
|
|
line.long 0x00 "CMP_A_CONFIG,Compare A channel configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
|
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
|
bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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|
bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
|
|
bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
|
|
group ad:0xF04E0224++0x03
|
|
line.long 0x00 "CMP_A_EVENT_OUT_MODE,Compare A channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04E0228++0x03
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line.long 0x00 "CMP_A_PULSE_WID0,Compare A channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04E022C++0x03
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line.long 0x00 "CMP_A_PULSE_WID1,Compare A channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04E0230++0x03
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line.long 0x00 "CMP_A_00_VAL,Compare value for compare A channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E0234++0x03
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line.long 0x00 "CMP_A_01_VAL,Compare value for compare A channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E0238++0x03
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line.long 0x00 "CMP_A_10_VAL,Compare value for compare A channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E023C++0x03
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line.long 0x00 "CMP_A_11_VAL,Compare value for compare A channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E0240++0x03
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line.long 0x00 "CMP_A_DITHER,Compare A channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04E0244++0x03
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line.long 0x00 "CMP_A_OFFSET,Compare A offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04E0248++0x03
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line.long 0x00 "CMP_A_EID,Compare A channel event ID register"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,CMP11 event ID"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,CMP10 event ID"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,CMP01 event ID"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,CMP00 event ID"
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group ad:0xF04E0250++0x03
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line.long 0x00 "CMP_B_CONFIG,Compare B channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use.In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04E0254++0x03
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line.long 0x00 "CMP_B_EVENT_OUT_MODE,Compare B channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04E0258++0x03
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line.long 0x00 "CMP_B_PULSE_WID0,Compare B channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04E025C++0x03
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line.long 0x00 "CMP_B_PULSE_WID1,Compare B channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04E0260++0x03
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line.long 0x00 "CMP_B_00_VAL,Compare value for compare B channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E0264++0x03
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line.long 0x00 "CMP_B_01_VAL,Compare value for compare B channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E0268++0x03
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line.long 0x00 "CMP_B_10_VAL,Compare value for compare B channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E026C++0x03
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line.long 0x00 "CMP_B_11_VAL,Compare value for compare B channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E0270++0x03
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line.long 0x00 "CMP_B_DITHER,Compare B channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04E0274++0x03
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line.long 0x00 "CMP_B_OFFSET,Compare B offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04E0280++0x03
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line.long 0x00 "CMP_C_CONFIG,Compare C channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04E0284++0x03
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line.long 0x00 "CMP_C_EVENT_OUT_MODE,Compare C channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04E0288++0x03
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line.long 0x00 "CMP_C_PULSE_WID0,Compare C channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04E028C++0x03
|
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line.long 0x00 "CMP_C_PULSE_WID1,Compare C channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04E0290++0x03
|
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line.long 0x00 "CMP_C_00_VAL,Compare value for compare C channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E0294++0x03
|
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line.long 0x00 "CMP_C_01_VAL,Compare value for compare C channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E0298++0x03
|
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line.long 0x00 "CMP_C_10_VAL,Compare value for compare C channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E029C++0x03
|
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line.long 0x00 "CMP_C_11_VAL,Compare value for compare C channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E02A0++0x03
|
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line.long 0x00 "CMP_C_DITHER,Compare C channel DIther register"
|
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04E02A4++0x03
|
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line.long 0x00 "CMP_C_OFFSET,Compare C offset value register"
|
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
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group ad:0xF04E02B0++0x03
|
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line.long 0x00 "CMP_D_CONFIG,Compare D channel configuration register"
|
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
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textline " "
|
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
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textline " "
|
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
|
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group ad:0xF04E02B4++0x03
|
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line.long 0x00 "CMP_D_EVENT_OUT_MODE,Compare D channel event output mode register"
|
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04E02B8++0x03
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line.long 0x00 "CMP_D_PULSE_WID0,Compare D channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04E02BC++0x03
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line.long 0x00 "CMP_D_PULSE_WID1,Compare D channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04E02C0++0x03
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line.long 0x00 "CMP_D_00_VAL,Compare value for compare D channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E02C4++0x03
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line.long 0x00 "CMP_D_01_VAL,Compare value for compare D channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E02C8++0x03
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line.long 0x00 "CMP_D_10_VAL,Compare value for compare D channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E02CC++0x03
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line.long 0x00 "CMP_D_11_VAL,Compare value for compare D channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04E02D0++0x03
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line.long 0x00 "CMP_D_DITHER,Compare D channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04E02D4++0x03
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line.long 0x00 "CMP_D_OFFSET,Compare D offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04E02E0++0x03
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line.long 0x00 "CMP_CTRL,Compare control register"
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bitfld.long 0x00 28. " CMP_A_EID_UPD ,Update EID value. Will be auto clear after completing update EID value." "0,1"
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bitfld.long 0x00 27. " CMP_D1_INIT_UPD ,Update cmp_d1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 26. " CMP_D0_INIT_UPD ,Update cmp_d0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 25. " CMP_C1_INIT_UPD ,Update cmp_c1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 24. "CMP_C0_INIT_UPD ,Update cmp_c0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 23. " CMP_B1_INIT_UPD ,Update cmp_b1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 22. " CMP_B0_INIT_UPD ,Update cmp_b0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 21. " CMP_A1_INIT_UPD ,Update cmp_a1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 20. "CMP_A0_INIT_UPD ,Update cmp_a0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 19. " CMP_D1_INIT_STATUS ,cmp_d1 output initial status" "0,1"
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bitfld.long 0x00 18. " CMP_D0_INIT_STATUS ,cmp_d0 output initial status" "0,1"
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bitfld.long 0x00 17. " CMP_C1_INIT_STATUS ,cmp_c1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 16. "CMP_C0_INIT_STATUS ,cmp_c0 output initial status" "0,1"
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bitfld.long 0x00 15. " CMP_B1_INIT_STATUS ,cmp_b1 output initial status" "0,1"
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bitfld.long 0x00 14. " CMP_B0_INIT_STATUS ,cmp_b0 output initial status" "0,1"
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bitfld.long 0x00 13. " CMP_A1_INIT_STATUS ,cmp_a1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 12. "CMP_A0_INIT_STATUS ,cmp_a0 output initial status" "0,1"
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bitfld.long 0x00 11. " CMP_D_VAL_UPD ,Update all the compare value registers for compare D channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 10. " CMP_C_VAL_UPD ,Update all the compare value registers for compare C channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 9. " CMP_B_VAL_UPD ,Update all the compare value registers for compare B channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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textline " "
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bitfld.long 0x00 8. "CMP_A_VAL_UPD ,Update all the compare value registers for compare A channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 7. " CMP_D_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CMP_C_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 5. " CMP_B_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour.." "0,1"
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textline " "
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bitfld.long 0x00 4. "CMP_A_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 3. " CMP_D_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 2. " CMP_C_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 1. " CMP_B_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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textline " "
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bitfld.long 0x00 0. "CMP_A_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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group ad:0xF04E0300++0x03
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line.long 0x00 "CPT_A_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_A0 signals into one signal for capture channel A"
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bitfld.long 0x00 26. " QUAD_INDEX_POL ,When this bit is set, INDEX signal polarity is changed." "0,1"
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bitfld.long 0x00 25. " QUAD_HOME_POL ,When this bit is set, HOME signal polarity is changed." "0,1"
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bitfld.long 0x00 21.--24. " QUAD_CLR_SEL ,In quadrature mode, the counter CLR event can be configured to be initiated by HOME or INDEX input 0000: HOME high 0001: INDEX high 0010: HOME high and {PHASE_B, PHASE_A} = 2'b00; 0011: HOME high and {PHASE_B, PHASE_A} = 2'.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 17.--20. " QUAD_SET_SEL ,In quadrature mode, the counter SET event can be configured to be initiated by HOME or INDEX input 0000: HOME high 0001: INDEX high 0010: HOME high and {PHASE_B, PHASE_A} = 2'b00; 0011: HOME high and {PHASE_B, PHASE_A} = 2'.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 16. "QUAD_MODE_EN ,Quadrature mode enable" "0,1"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04E0304++0x03
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line.long 0x00 "CPT_A_SSE_REG,Signal synthesis for CAPTURE A"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04E0308++0x03
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line.long 0x00 "CPT_B_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_B0 signals into one signal for capture channel B"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04E030C++0x03
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line.long 0x00 "CPT_B_SSE_REG,Signal synthesis for CAPTURE B"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04E0310++0x03
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line.long 0x00 "CPT_C_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_C0 signals into one signal for capture channel C"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04E0314++0x03
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line.long 0x00 "CPT_C_SSE_REG,Signal synthesis for CAPTURE C"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04E0318++0x03
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line.long 0x00 "CPT_D_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_D0 signals into one signal for capture channel D"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04E031C++0x03
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line.long 0x00 "CPT_D_SSE_REG,Signal synthesis for CAPTURE D"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04E0320++0x03
|
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line.long 0x00 "CMP_A_SSE_CTRL,Synthesis CMP_A0,CMP_B0,CMP_C0 and CMP_D0 outputs and CPT_A_SSE SO signals into one signal for compare channel A"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_A_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04E0324++0x03
|
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line.long 0x00 "CMP_A_SSE_REG,Signal synthesis for compare A output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04E0328++0x03
|
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line.long 0x00 "CMP_B_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_B_SSE SO signals into one signal for compare channel B"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
|
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_B_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04E032C++0x03
|
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line.long 0x00 "CMP_B_SSE_REG,Signal synthesis for compare B output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04E0330++0x03
|
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line.long 0x00 "CMP_C_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_C_SSE SO signals into one signal for compare channel C"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
|
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_C_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
|
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
|
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
|
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group ad:0xF04E0334++0x03
|
|
line.long 0x00 "CMP_C_SSE_REG,Signal synthesis for compare C output"
|
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04E0338++0x03
|
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line.long 0x00 "CMP_D_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_D_SSE SO signals into one signal for compare channel D"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
|
|
bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_D_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
|
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
|
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
|
|
group ad:0xF04E033C++0x03
|
|
line.long 0x00 "CMP_D_SSE_REG,Signal synthesis for compare D output"
|
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04E0340++0x03
|
|
line.long 0x00 "CPT_A_INPUT_SEL,Capture A channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_A1 1000: CMP_A1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_A_SSE_SO 0001: CPT_A1 0010: CMP_A1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_A_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_A_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E0344++0x03
|
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line.long 0x00 "CPT_B_INPUT_SEL,Capture B channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_B1 1000: CMP_B1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_B_SSE_SO 0001: CPT_B1 0010: CMP_B1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_B_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_B_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E0348++0x03
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line.long 0x00 "CPT_C_INPUT_SEL,Capture C channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_C1 1000: CMP_C1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_C_SSE_SO 0001: CPT_C1 0010: CMP_C1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_C_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_C_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E034C++0x03
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line.long 0x00 "CPT_D_INPUT_SEL,Capture D channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_D1 1000: CMP_D1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_D_SSE_SO 0001: CPT_D1 0010: CMP_D1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_D_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_D_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E0350++0x03
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line.long 0x00 "CMP_A_INPUT_SEL,Compare A channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E0354++0x03
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line.long 0x00 "CMP_B_INPUT_SEL,Compare B channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E0358++0x03
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line.long 0x00 "CMP_C_INPUT_SEL,Compare C channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E035C++0x03
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line.long 0x00 "CMP_D_INPUT_SEL,Compare D channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E0360++0x03
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line.long 0x00 "CNT_G0_INPUT_SEL,Counter G0 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E0364++0x03
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line.long 0x00 "CNT_G1_INPUT_SEL,Counter G1 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E0368++0x03
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line.long 0x00 "EXT_OUTPUT_SEL,External output source select register"
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bitfld.long 0x00 8.--11. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_A1 1000: CPT_B1 1001: CPT_C1 1010: CPT_D1 1011: CMP_A1 1100: SW_TRIG0.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04E036C++0x03
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line.long 0x00 "ETM_POL_INV,Event trigger polarity invert"
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bitfld.long 0x00 30. " EXT_DIR ,Polarity invert" "0,1"
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bitfld.long 0x00 29. " EXT_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 28. " EXT_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 27. " CNT_G1_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 26. "CNT_G1_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 25. " CNT_G0_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 24. " CNT_G0_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 23. " CMP_D_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 22. "CMP_D_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 21. " CMP_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 20. " CMP_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 19. " CMP_B_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 18. "CMP_B_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 17. " CMP_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 16. " CMP_A_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 15. " CPT_D_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 14. "CPT_D_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 13. " CPT_D_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 12. " CPT_D_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 11. " CPT_C_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 10. "CPT_C_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 9. " CPT_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 8. " CPT_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 7. " CPT_B_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 6. "CPT_B_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 5. " CPT_B_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 4. " CPT_B_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 3. " CPT_A_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 2. "CPT_A_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 1. " CPT_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 0. " CPT_A_SET ,Polarity invert" "0,1"
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group ad:0xF04E0370++0x03
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line.long 0x00 "CPT_SW_TRIG,Capture signal software trigger register"
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bitfld.long 0x00 11. " CPT_D_SIG ,Set high to generate SIG pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 10. " CPT_C_SIG ,Set high to generate SIG pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 9. " CPT_B_SIG ,Set high to generate SIG pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 8. " CPT_A_SIG ,Set high to generate SIG pulse signal for capture A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 7. "CPT_D_CLR ,Set high to generate CLR pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CPT_C_CLR ,Set high to generate CLR pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CPT_B_CLR ,Set high to generate CLR pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CPT_A_CLR ,Set high to generate CLR pulse signal for capture A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CPT_D_SET ,Set high to generate SET pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CPT_C_SET ,Set high to generate SET pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CPT_B_SET ,Set high to generate SET pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CPT_A_SET ,Set high to generate SET pulse signal for capture A channel. Auto clear after set." "0,1"
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group ad:0xF04E0374++0x03
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line.long 0x00 "CMP_SW_TRIG,Compare signal software trigger register"
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bitfld.long 0x00 7. " CMP_D_CLR ,Set high to generate CLR pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CMP_C_CLR ,Set high to generate CLR pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CMP_B_CLR ,Set high to generate CLR pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CMP_A_CLR ,Set high to generate CLR pulse signal for compare A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CMP_D_SET ,Set high to generate SET pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CMP_C_SET ,Set high to generate SET pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CMP_B_SET ,Set high to generate SET pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CMP_A_SET ,Set high to generate SET pulse signal for compare A channel. Auto clear after set." "0,1"
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group ad:0xF04E0378++0x03
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line.long 0x00 "CNT_EXT_SW_TRIG,Counter and external signal software trigger register"
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bitfld.long 0x00 5. " EXT_CLR ,Set high to generate CLR pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " EXT_SET ,Set high to generate SET pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 3. " CNT_G1_CLR ,Set high to generate CLR pulse signal for CNT_G1. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CNT_G1_SET ,Set high to generate SET pulse signal for CNT_G1. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 1. "CNT_G0_CLR ,Set high to generate CLR pulse signal for CNT_G0. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CNT_G0_SET ,Set high to generate SET pulse signal for CNT_G0. Auto clear after set." "0,1"
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group ad:0xF04E0380++0x03
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line.long 0x00 "SW_TRIG_CTRL,SW trigger event generation control"
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bitfld.long 0x00 15. " SW_TRIG3_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 14. " SW_TRIG3_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 13. " SW_TRIG3_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 12. " SW_TRIG3_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 11. "SW_TRIG2_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 10. " SW_TRIG2_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 9. " SW_TRIG2_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 8. " SW_TRIG2_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 7. "SW_TRIG1_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 6. " SW_TRIG1_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 5. " SW_TRIG1_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 4. " SW_TRIG1_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "SW_TRIG0_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 2. " SW_TRIG0_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 1. " SW_TRIG0_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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group ad:0xF04E0384++0x03
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line.long 0x00 "SW_TRIG_STATUS,SW trigger outputs status"
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bitfld.long 0x00 3. " SW_TRIG3 ,SW trigger output" "0,1"
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bitfld.long 0x00 2. " SW_TRIG2 ,SW trigger output" "0,1"
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bitfld.long 0x00 1. " SW_TRIG1 ,SW trigger output" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0 ,SW trigger output" "0,1"
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group ad:0xF04E0388++0x03
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line.long 0x00 "SW_TRIG_PULSE0,SW trigger0 and trigger1 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG1_WIDTH ,Pulse width of SW trigger1"
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hexmask.long.word 0x00 0.--15. 1. " TRIG0_WIDTH ,Pulse width of SW trigger0"
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group ad:0xF04E038C++0x03
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line.long 0x00 "SW_TRIG_PULSE1,SW trigger2 and trigger3 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG3_WIDTH ,Pulse width of SW trigger3"
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hexmask.long.word 0x00 0.--15. 1. " TRIG2_WIDTH ,Pulse width of SW trigger2"
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group ad:0xF04E0390++0x03
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line.long 0x00 "CNT_G0_SNAP_SHOT_SEL,CNT_G0 snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04E0394++0x03
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line.long 0x00 "CNT_G1_SNAP_SHOT_SEL,CNT_G1 snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04E0398++0x03
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line.long 0x00 "LCNT_A_SNAP_SHOT_SEL,LCNT_A snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04E039C++0x03
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line.long 0x00 "LCNT_B_SNAP_SHOT_SEL,LCNT_B snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04E03A0++0x03
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line.long 0x00 "LCNT_C_SNAP_SHOT_SEL,LCNT_C snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04E03A4++0x03
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line.long 0x00 "LCNT_D_SNAP_SHOT_SEL,LCNT_D snapshot source select"
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|
hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04E03A8++0x03
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line.long 0x00 "SNAP_SHOT_O_SEL,Snapshot output snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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|
group ad:0xF04E0400++0x03
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|
line.long 0x00 "CPT_A0_FLT,Filter setting for CPT_A0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04E0404++0x03
|
|
line.long 0x00 "CPT_B0_FLT,Filter setting for CPT_B0 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04E0408++0x03
|
|
line.long 0x00 "CPT_C0_FLT,Filter setting for CPT_C0 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04E040C++0x03
|
|
line.long 0x00 "CPT_D0_FLT,Filter setting for CPT_D0 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04E0410++0x03
|
|
line.long 0x00 "FAULT0_FLT,Filter setting for fault0 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04E0414++0x03
|
|
line.long 0x00 "FAULT1_FLT,Filter setting for fault1 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04E0418++0x03
|
|
line.long 0x00 "FAULT2_FLT,Filter setting for fault2 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04E041C++0x03
|
|
line.long 0x00 "FAULT3_FLT,Filter setting for fault3 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04E0420++0x03
|
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line.long 0x00 "SYNC_DIS,Synchronization DIsable control register"
|
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bitfld.long 0x00 15. " FAULT3 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 14. " FAULT2 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 13. " FAULT1 ,DIsable synchronization" "0,1"
|
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bitfld.long 0x00 12. " FAULT0 ,DIsable synchronization" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "SNAP_SHOT ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 9. " EXT_CLR ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 8. " EXT_SET ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 7. " CPT_D1 ,DIsable synchronization" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "CPT_C1 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 5. " CPT_B1 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 4. " CPT_A1 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 3. " CPT_D0 ,DIsable synchronization" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CPT_C0 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B0 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A0 ,DIsable synchronization" "0,1"
|
|
group ad:0xF04E0440++0x03
|
|
line.long 0x00 "CMP_A_FAULT_EVENT_CTRL,Compare A channel event control register"
|
|
bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04E0444++0x03
|
|
line.long 0x00 "CMP_B_FAULT_EVENT_CTRL,Compare B channel event control register"
|
|
bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04E0448++0x03
|
|
line.long 0x00 "CMP_C_FAULT_EVENT_CTRL,Compare C channel event control register"
|
|
bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04E044C++0x03
|
|
line.long 0x00 "CMP_D_FAULT_EVENT_CTRL,Compare D channel event control register"
|
|
bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04E0460++0x03
|
|
line.long 0x00 "CMP_A_DTI_CTRL,Dead time insertion control register for compare A channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
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|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
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|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04E0464++0x03
|
|
line.long 0x00 "CMP_A_DTI_WID,Dead time insertion width register for compare A channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04E0468++0x03
|
|
line.long 0x00 "CMP_B_DTI_CTRL,Dead time insertion control register for compare B channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04E046C++0x03
|
|
line.long 0x00 "CMP_B_DTI_WID,Dead time insertion width register for compare B channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04E0470++0x03
|
|
line.long 0x00 "CMP_C_DTI_CTRL,Dead time insertion control register for compare C channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04E0474++0x03
|
|
line.long 0x00 "CMP_C_DTI_WID,Dead time insertion width register for compare C channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04E0478++0x03
|
|
line.long 0x00 "CMP_D_DTI_CTRL,Dead time insertion control register for compare D channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04E047C++0x03
|
|
line.long 0x00 "CMP_D_DTI_WID,Dead time insertion width register for compare D channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04E0500++0x03
|
|
line.long 0x00 "SIGNAL_STATUS,Signal status register"
|
|
bitfld.long 0x00 31. " CPT_D_CLR ,Capture D clear signal" "0,1"
|
|
bitfld.long 0x00 30. " CPT_D_SET ,Capture D set signal" "0,1"
|
|
bitfld.long 0x00 29. " CPT_D_DIR ,Capture D DIR signal" "0,1"
|
|
bitfld.long 0x00 28. " CPT_D_SIG ,Capture D SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "CPT_C_CLR ,Capture C clear signal" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_SET ,Capture C set signal" "0,1"
|
|
bitfld.long 0x00 25. " CPT_C_DIR ,Capture C DIR signal" "0,1"
|
|
bitfld.long 0x00 24. " CPT_C_SIG ,Capture C SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CPT_B_CLR ,Capture B clr signal" "0,1"
|
|
bitfld.long 0x00 22. " CPT_B_SET ,Capture B set signal" "0,1"
|
|
bitfld.long 0x00 21. " CPT_B_DIR ,Capture B DIR signal" "0,1"
|
|
bitfld.long 0x00 20. " CPT_B_SIG ,Capture B SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CPT_A_CLR ,Capture A clear signal" "0,1"
|
|
bitfld.long 0x00 18. " CPT_A_SET ,Capture A set signal" "0,1"
|
|
bitfld.long 0x00 17. " CPT_A_DIR ,Capture A DIR signal" "0,1"
|
|
bitfld.long 0x00 16. " CPT_A_SIG ,Capture A SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_CLR ,Compare D clear signal" "0,1"
|
|
bitfld.long 0x00 14. " CMP_D_SET ,Compare D set signal" "0,1"
|
|
bitfld.long 0x00 13. " CMP_C_CLR ,Compare C clear signal" "0,1"
|
|
bitfld.long 0x00 12. " CMP_C_SET ,Compare C set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_B_CLR ,Compare B clear signal" "0,1"
|
|
bitfld.long 0x00 10. " CMP_B_SET ,Compare B set signal" "0,1"
|
|
bitfld.long 0x00 9. " CMP_A_CLR ,Compare A clear signal" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A_SET ,Compare A set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D1 ,Compare D1 signal" "0,1"
|
|
bitfld.long 0x00 6. " CMP_D0 ,Compare D0 signal" "0,1"
|
|
bitfld.long 0x00 5. " CMP_C1 ,Compare C1 signal" "0,1"
|
|
bitfld.long 0x00 4. " CMP_C0 ,Compare C0 signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CMP_B1 ,Compare B1 signal" "0,1"
|
|
bitfld.long 0x00 2. " CMP_B0 ,Compare B0 signal" "0,1"
|
|
bitfld.long 0x00 1. " CMP_A1 ,Compare A1 signal" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A0 ,Compare A0 signal" "0,1"
|
|
group ad:0xF04E0FFC++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
tree.end
|
|
tree "ETIMER4"
|
|
width 28.
|
|
group ad:0xF04F0000++0x03
|
|
line.long 0x00 "INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,LCNT_D snapshot event happens" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,LCNT_C snapshot event happens" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,LCNT_B snapshot event happens" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,LCNT_A snapshot event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,CNT_G1 snapshot event happens" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,CNT_G0 snapshot event happens" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,CNT_LOCAL_D overflow" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,CNT_LOCAL_C overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,CNT_LOCAL_B overflow" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,CNT_LOCAL_A overflow" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,CNT_G1 overflow" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,CNT_G0 overflow" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Compare D event happens" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Compare C event happens" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Compare B event happens" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Compare A event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Capture D event happens" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Capture C event happens" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Capture B event happens" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Capture A event happens" "0,1"
|
|
group ad:0xF04F0004++0x03
|
|
line.long 0x00 "INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Status enable" "0,1"
|
|
group ad:0xF04F0008++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt singal enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "LCNT_D_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " LCNT_C_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " LCNT_B_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " LCNT_A_SNAP_SHOT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CNT_G1_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CNT_G0_SNAP_SHOT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " LCNT_D_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " LCNT_C_OVF ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "LCNT_B_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " LCNT_A_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CNT_G1_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0_OVF ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " CMP_C ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " CMP_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " CMP_A ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CPT_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " CPT_C ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A ,Singal enable" "0,1"
|
|
group ad:0xF04F000C++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA,Correctable error interrupt status register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,CPT D vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,CPT C vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,CPT B vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,CPT A vaule is not fetched" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,FIFO D overrun" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,FIFO C overrun" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,FIFO B overrun" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,FIFO A overrun" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04F0010++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA_EN,Correctable error interrupt status enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04F0014++0x03
|
|
line.long 0x00 "COR_ERR_INT_SIG_EN,Correctable error interrupt singal enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04F0018++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA,Uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,CPT D vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,CPT C vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,CPT B vaule is not fetched" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,CPT A vaule is not fetched" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,FIFO D overrun" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,FIFO C overrun" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,FIFO B overrun" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,FIFO A overrun" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04F001C++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04F0020++0x03
|
|
line.long 0x00 "UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt singal enable register"
|
|
bitfld.long 0x00 27. " CPT_D_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 25. " CPT_B_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
bitfld.long 0x00 24. " CPT_A_VAL_NOT_FETCH ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_D_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 5. " FIFO_B_OVERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A_OVERRUN ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04F0024++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata corrctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04F0028++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04F002C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04F0030++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Cock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Cock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error." "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error." "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error." "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04F0034++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN,Function safety uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04F0038++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN,Function safety uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error." "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error." "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input singal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,CONFIG_DMA eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04F003C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_1,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04F0040++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN_1,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04F0044++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN_1,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,CONFIG_DMA eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04F004C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF04F0050++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF04F0054++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF04F005C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF04F0060++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,RAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04F0064++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04F0068++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,RAM B rdata monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04F006C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,RAM B rdata ECC monitorerror injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04F0070++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF04F0074++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF04F0080++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 16.--18. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF04F0084++0x03
|
|
line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04F0088++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04F008C++0x03
|
|
line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04F0090++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 6. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
|
bitfld.long 0x00 5. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
|
bitfld.long 0x00 4. " CNT_OVF ,Counter overflow and snapshot interrupt error injection." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Channel D interrupt error injection." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CHN_C ,Channel C interrupt error injection." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B ,Channel B interrupt error injection." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Channel A interrupt error injection." "0,1"
|
|
group ad:0xF04F0094++0x03
|
|
line.long 0x00 "CLK_MON_CMP_ERR_INJ,Clock monitor compare error injection r"
|
|
bitfld.long 0x00 2.--3. " ERR1 ,Clock monitor 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ERR0 ,Clock monitor 0" "0,1,2,3"
|
|
group ad:0xF04F00A0++0x03
|
|
line.long 0x00 "TIM_CLK_CONFIG,Timer clock select and DIvider configuration."
|
|
bitfld.long 0x00 31. " CLK_CHANGE_UPD ,Set this bit to make new DIV_NUM/SRC_CLK_SEL value effective. Will be auto cleared after new DIV_NUM/SRC_CLK_SEL is effective" "0,1"
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|
bitfld.long 0x00 16.--17. " SRC_CLK_SEL ,Clock source select. 00: High frequency(HF) clock, update to 400mhz. 01: Alternative High frequency(AHF) clock, update to 400mhz. 10: External clock. 11: Low power(LP) clock, typically from low speed on chip RCOSC." "0,1,2,3"
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|
hexmask.long.word 0x00 0.--15. 1. " DIV_NUM ,DIvider number for timer clock."
|
|
group ad:0xF04F00A4++0x03
|
|
line.long 0x00 "CLK_MON_EN,Clock monitor enable register"
|
|
bitfld.long 0x00 2. " CMP_SET ,When enable or DIsable clock monitor, set this bit together. This bit is used to inDIcate configuration is completed." "0,1"
|
|
bitfld.long 0x00 1. " EN_N ,Active low. Enable clock monitor1" "0,1"
|
|
bitfld.long 0x00 0. " EN_P ,Active high.Enable clock monitor0" "0,1"
|
|
group ad:0xF04F00A8++0x03
|
|
line.long 0x00 "SW_RST,Software reset"
|
|
bitfld.long 0x00 5. " CNT_G1 ,Reset CNT_G1.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0 ,Reset CNT_G0.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Reset channel D. Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 2. " CHN_C ,Reset channel C.Will be auto cleared after reset complete." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CHN_B ,Reset channel B.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Reset channel A.Will be auto cleared after reset complete." "0,1"
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|
group ad:0xF04F00B0++0x03
|
|
line.long 0x00 "CHN_DMA_CTRL,Channel DMA control register"
|
|
bitfld.long 0x00 19. " CHN_D_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 18. " CHN_C_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 17. " CHN_B_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
bitfld.long 0x00 16. " CHN_A_16BIT_MODE ,16 bit mode enbale for compare mode 0: 32 bit compare value 1: 16 bit compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CHN_D_SIG_MASK ,Mask channel D dma request hardware output" "0,1"
|
|
bitfld.long 0x00 14. " CHN_C_SIG_MASK ,Mask channel C dma request hardware output" "0,1"
|
|
bitfld.long 0x00 13. " CHN_B_SIG_MASK ,Mask channel B dma request hardware output" "0,1"
|
|
bitfld.long 0x00 12. " CHN_A_SIG_MASK ,Mask channel A dma request hardware output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "CHN_D_SEL ,Select dma request working for CAPTURE D/COMPARE D channel 1x: Use for CPT_CMP delay mode D 01: Use for capture channel D. 00: Use for compare channel D." "0,1,2,3"
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|
bitfld.long 0x00 8.--9. " CHN_C_SEL ,Select dma request working for CAPTURE C/COMPARE C channel 1x: Use for CPT_CMP delay mode C 01: Use for capture channel C. 00: Use for compare channel C." "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " CHN_B_SEL ,Select dma request working for CAPTURE B/COMPARE B channel 1x: Use for CPT_CMP delay mode B 01: Use for capture channel B. 00: Use for compare channel B." "0,1,2,3"
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|
bitfld.long 0x00 4.--5. " CHN_A_SEL ,Select dma request working for CAPTURE A/COMPARE A channel 1x: Use for CPT_CMP delay mode A 01: Use for capture channel A. 00: Use for compare channel A." "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CHN_D_EN ,Enable dma request for CAPTURE D/COMPARE D channel accorDIng to channel D FIFO WML." "0,1"
|
|
bitfld.long 0x00 2. " CHN_C_EN ,Enable dma request for CAPTURE C/COMPARE C channel accorDIng to channel C FIFO WML." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B_EN ,Enable dma request for CAPTURE B/COMPARE B channel accorDIng to channel B FIFO WML." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A_EN ,Enable dma request for CAPTURE A/COMPARE A channel accorDIng to channle A FIFO WML." "0,1"
|
|
group ad:0xF04F00B4++0x03
|
|
line.long 0x00 "DMA_WML,DMA watermark leverl register"
|
|
bitfld.long 0x00 24.--27. " CHN_D ,Waterwark level setting for channel D DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CHN_C ,Waterwark level setting for channel C DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CHN_B ,Waterwark level setting for channel B DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " CHN_A ,Waterwark level setting for channel A DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04F00B8++0x03
|
|
line.long 0x00 "CONFIG_DMA_CTL,Configuration dma control register"
|
|
hexmask.long.word 0x00 2.--15. 1. " TRIG_SEL ,Select source to trigger dma request. 1. CMP_A_CE 2. CMP_B_CE 3. CMP_C_CE 4. CMP_D_CE 5. CPT_A_CE 6. CPT_B_CE 7. CPT_C_CE 8. CPT_D_CE 9. CNT_G0_CE 10. CNT_G1_CE 11. LCNT_A_CE 12. LCNT_B_CE 13. LCNT_C_CE 14. LCNT_D_CE.."
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bitfld.long 0x00 1. " SIG_MASK ,Mask configuration dma request hardware output" "0,1"
|
|
bitfld.long 0x00 0. " EN ,DMA enable for register configuration" "0,1"
|
|
group ad:0xF04F00BC++0x03
|
|
line.long 0x00 "FIFO_REQ_STATUS,FIFO request status"
|
|
bitfld.long 0x00 3. " CHN_D ,Channel D FIFO reach water mark level" "0,1"
|
|
bitfld.long 0x00 2. " CHN_C ,Channel C FIFO reach water mark level" "0,1"
|
|
bitfld.long 0x00 1. " CHN_B ,Channel B FIFO reach water mark level" "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Channel A FIFO reach water mark level" "0,1"
|
|
group ad:0xF04F00C0++0x03
|
|
line.long 0x00 "FIFO_A,FIFO_entry for capture and compare channel A"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04F00C4++0x03
|
|
line.long 0x00 "FIFO_B,FIFO_entry for capture and compare channel B"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04F00C8++0x03
|
|
line.long 0x00 "FIFO_C,FIFO_entry for capture and compare channel C"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04F00CC++0x03
|
|
line.long 0x00 "FIFO_D,FIFO_entry for capture and compare channel D"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04F00D0++0x03
|
|
line.long 0x00 "FIFO_STA,FIFO status."
|
|
bitfld.long 0x00 31. " FIFO_ERR_D ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 26.--30. " FIFO_ENTRIES_D ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 25. " FIFO_EMPTY_D ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 24. " FIFO_FULL_D ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "FIFO_ERR_C ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 18.--22. " FIFO_ENTRIES_C ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17. " FIFO_EMPTY_C ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 16. " FIFO_FULL_C ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "FIFO_ERR_B ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 10.--14. " FIFO_ENTRIES_B ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " FIFO_EMPTY_B ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 8. " FIFO_FULL_B ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_ERR_A ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 2.--6. " FIFO_ENTRIES_A ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x00 1. " FIFO_EMPTY_A ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 0. " FIFO_FULL_A ,InDIcate FIFO is full." "0,1"
|
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group ad:0xF04F0100++0x03
|
|
line.long 0x00 "CNT_G0_INIT,Counter G0 initial value registe"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF04F0104++0x03
|
|
line.long 0x00 "CNT_G0_OVF,Counter G0 overflow value registe"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF04F0108++0x03
|
|
line.long 0x00 "CNT_G0_CFG,CNT_G0 configuration register."
|
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bitfld.long 0x00 31. " CASCADE_MODE ,When this bit is set, CNT_G1 only increase when CNT_G0 is overflowed. In this setup, CNT_G0 can work as a 64 bit timer if CNT_G0_OVF_VAL is 32'hffffffff." "0,1"
|
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bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. "SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04F010C++0x03
|
|
line.long 0x00 "CNT_G0_EN,CNT_G0 enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
|
group ad:0xF04F0110++0x03
|
|
line.long 0x00 "CNT_G0,CNT_G0 TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F0114++0x03
|
|
line.long 0x00 "CNT_G0_HOLD,CNT_G0 Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04F0118++0x03
|
|
line.long 0x00 "CNT_G0_DIFF,CNT_G0 DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F0120++0x03
|
|
line.long 0x00 "CNT_G1_INIT,Counter G1 initial value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04F0124++0x03
|
|
line.long 0x00 "CNT_G1_OVF,Counter G1 overflow value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04F0128++0x03
|
|
line.long 0x00 "CNT_G1_CFG,CNT_G1 configuration register."
|
|
bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW" "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04F012C++0x03
|
|
line.long 0x00 "CNT_G1_EN,CNT_G1 enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
|
group ad:0xF04F0130++0x03
|
|
line.long 0x00 "CNT_G1,CNT_G1 TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F0134++0x03
|
|
line.long 0x00 "CNT_G1_HOLD,CNT_G1 Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04F0138++0x03
|
|
line.long 0x00 "CNT_G1_DIFF,CNT_G1 DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F0140++0x03
|
|
line.long 0x00 "LCNT_A_INIT,Local counter A initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04F0144++0x03
|
|
line.long 0x00 "LCNT_A_OVF,Local counter A overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04F0148++0x03
|
|
line.long 0x00 "LCNT_A_CFG,Local counter A configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
|
|
bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
|
|
bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04F014C++0x03
|
|
line.long 0x00 "LCNT_A_EN,Local counter A enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
|
|
group ad:0xF04F0150++0x03
|
|
line.long 0x00 "LCNT_A,LCNT_A TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F0154++0x03
|
|
line.long 0x00 "LCNT_A_HOLD,LCNT_A Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
|
group ad:0xF04F0158++0x03
|
|
line.long 0x00 "LCNT_A_DIFF,LCNT_A DIff Register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F0160++0x03
|
|
line.long 0x00 "LCNT_B_INIT,Local counter B initial value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04F0164++0x03
|
|
line.long 0x00 "LCNT_B_OVF,Local counter B overflow value register"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04F0168++0x03
|
|
line.long 0x00 "LCNT_B_CFG,Local counter B configuration register."
|
|
bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
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|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
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bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
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bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
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|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
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|
bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
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bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
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bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
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|
textline " "
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|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
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|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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|
textline " "
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|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04F016C++0x03
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line.long 0x00 "LCNT_B_EN,Local counter B enable register"
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
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group ad:0xF04F0170++0x03
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line.long 0x00 "LCNT_B,LCNT_B TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04F0174++0x03
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line.long 0x00 "LCNT_B_HOLD,LCNT_B Hold Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
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group ad:0xF04F0178++0x03
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line.long 0x00 "LCNT_B_DIFF,LCNT_B DIff Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04F0180++0x03
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line.long 0x00 "LCNT_C_INIT,Local counter C initial value register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04F0184++0x03
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line.long 0x00 "LCNT_C_OVF,Local counter C overflow value register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04F0188++0x03
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line.long 0x00 "LCNT_C_CFG,Local counter C configuration register."
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bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
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bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
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bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
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bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
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bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
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bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
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bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
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bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
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textline " "
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|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
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bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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textline " "
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|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04F018C++0x03
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line.long 0x00 "LCNT_C_EN,Local counter C enable register"
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
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group ad:0xF04F0190++0x03
|
|
line.long 0x00 "LCNT_C,LCNT_C TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F0194++0x03
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line.long 0x00 "LCNT_C_HOLD,LCNT_C Hold Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
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|
group ad:0xF04F0198++0x03
|
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line.long 0x00 "LCNT_C_DIFF,LCNT_C DIff Register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F01A0++0x03
|
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line.long 0x00 "LCNT_D_INIT,Local counter D initial value register"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF04F01A4++0x03
|
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line.long 0x00 "LCNT_D_OVF,Local counter D overflow value register"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF04F01A8++0x03
|
|
line.long 0x00 "LCNT_D_CFG,Local counter D configuration register."
|
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bitfld.long 0x00 28. " OVF_RST_DIS ,When this bit is set, overflow event does not reset counter" "0,1"
|
|
bitfld.long 0x00 27. " DELTA_TIME_EN ,In dual capture mode, when this bit is set, delta time of 2 capture will be stored in lcnt_[x]_DIff register" "0,1"
|
|
bitfld.long 0x00 26. " SIG_EN ,When this bit is set, only counting when cpt_[x]_sig is triggered" "0,1"
|
|
bitfld.long 0x00 25. " START_BY_FIRST_CPT ,After local counter is enable, local counter only start after first capture event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "CPT1_CLR_EN ,Local counter can be reset by cpt1_event" "0,1"
|
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bitfld.long 0x00 23. " CPT0_CLR_EN ,Local counter can be reset by cpt0_event" "0,1"
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bitfld.long 0x00 21.--22. " SIG_TRIG_SEL ,Counting triggered by SIG signal 2'b00: Positive edge 2'b01 Negative edge 2'b10 Signal toggle 2'b11 Level high (LCNT counts when SIG is high)" "0,1,2,3"
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bitfld.long 0x00 20. " NO_STOP_OVF_MODE ,In no stop mode, when counter value is less or grater than overflow value, counter overflow event is generated. 0: grater 1: less" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "NO_STOP_MODE ,When this bit is set, the counter starts non-stop counting.Counter does not reset to zero when reach overflow value." "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
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textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval.Only be active when SIG_TRIG_SEL bit is 2'b11."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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|
group ad:0xF04F01AC++0x03
|
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line.long 0x00 "LCNT_D_EN,Local counter D enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count.In single mode, this bit will be auto cleared when counter reach overflow value." "0,1"
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group ad:0xF04F01B0++0x03
|
|
line.long 0x00 "LCNT_D,LCNT_D TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F01B4++0x03
|
|
line.long 0x00 "LCNT_D_HOLD,LCNT_D Hold Register"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,On snapshot event, current counter value is captured in 'Hold register'."
|
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group ad:0xF04F01B8++0x03
|
|
line.long 0x00 "LCNT_D_DIFF,LCNT_D DIff Register"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04F01C0++0x03
|
|
line.long 0x00 "CPT_A_CPT0_CNT0,Capture A capture 0 counter 0 Register"
|
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
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group ad:0xF04F01C4++0x03
|
|
line.long 0x00 "CPT_A_CPT0_CNT1,Capture A capture 0 counter 1 Register"
|
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01C8++0x03
|
|
line.long 0x00 "CPT_A_CPT1_CNT0,Capture A capture 1 counter 0 Register"
|
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hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01CC++0x03
|
|
line.long 0x00 "CPT_A_CPT1_CNT1,Capture A capture 1 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01D0++0x03
|
|
line.long 0x00 "CPT_B_CPT0_CNT0,Capture B capture 0 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01D4++0x03
|
|
line.long 0x00 "CPT_B_CPT0_CNT1,Capture B capture 0 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01D8++0x03
|
|
line.long 0x00 "CPT_B_CPT1_CNT0,Capture B capture 1 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01DC++0x03
|
|
line.long 0x00 "CPT_B_CPT1_CNT1,Capture B capture 1 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01E0++0x03
|
|
line.long 0x00 "CPT_C_CPT0_CNT0,Capture C capture 0 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01E4++0x03
|
|
line.long 0x00 "CPT_C_CPT0_CNT1,Capture C capture 0 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01E8++0x03
|
|
line.long 0x00 "CPT_C_CPT1_CNT0,Capture C capture 1 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01EC++0x03
|
|
line.long 0x00 "CPT_C_CPT1_CNT1,Capture C capture 1 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01F0++0x03
|
|
line.long 0x00 "CPT_D_CPT0_CNT0,Capture D capture 0 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01F4++0x03
|
|
line.long 0x00 "CPT_D_CPT0_CNT1,Capture D capture 0 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01F8++0x03
|
|
line.long 0x00 "CPT_D_CPT1_CNT0,Capture D capture 1 counter 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F01FC++0x03
|
|
line.long 0x00 "CPT_D_CPT1_CNT1,Capture D capture 1 counter 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Captured time counter"
|
|
group ad:0xF04F0200++0x03
|
|
line.long 0x00 "CPT_A_CONFIG,Capture A channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04F0204++0x03
|
|
line.long 0x00 "CPT_B_CONFIG,Capture B channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04F0208++0x03
|
|
line.long 0x00 "CPT_C_CONFIG,Capture C channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04F020C++0x03
|
|
line.long 0x00 "CPT_D_CONFIG,Capture D channel configuration register"
|
|
bitfld.long 0x00 9.--10. " CE_TRIG_SEL ,Capture event is triggered by below event 00: cpt0 event 01: cpt1 event 10: both cpt0 and cpt1 event 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable capture event." "0,1"
|
|
bitfld.long 0x00 6.--7. " CNT_SEL ,When capture event happens, below selected counter value can be captured 00: cnt_g0 01: cnt_g0+cnt_g1 10: lcnt 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CPT1_TRIG_MODE ,Cpt1 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. "CPT0_TRIG_MODE ,Cpt0 event trigger mode 00: rising edge 01: failing edge 10: both rising and failing edge 11: ignore" "0,1,2,3"
|
|
bitfld.long 0x00 1. " DUAL_MODE ,In dual mode, only generate one IRQ event on cpt1 event. 2 capture event can be configured to DIfferent trigger mode. Only after cpt0 event is triggered, cpt1 event start to be triggered. 0: only trigger cpt0 event 1: .." "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and one-shot mode 0: Consecutive mode 1: Only execute one time capture." "0,1"
|
|
group ad:0xF04F0210++0x03
|
|
line.long 0x00 "CPT_CTRL,Capture control register"
|
|
bitfld.long 0x00 7. " CPT_D_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CPT_C_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
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bitfld.long 0x00 5. " CPT_B_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
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bitfld.long 0x00 4. " CPT_A_CONFIG_SET ,After this bit is set, capture configuration will be immeDIately reloaded with corresponDIng configuration in CPTX_CONFIG register. SW user need guarantee on the fly configuration changing would not cause unexpected .." "0,1"
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textline " "
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bitfld.long 0x00 3. "CPT_D_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
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bitfld.long 0x00 2. " CPT_C_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
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bitfld.long 0x00 1. " CPT_B_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
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bitfld.long 0x00 0. " CPT_A_EN ,Enable capture A channel. In non-consecutive mode, this bit will be auto cleared when capture IRQ event happens." "0,1"
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group ad:0xF04F0220++0x03
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line.long 0x00 "CMP_A_CONFIG,Compare A channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04F0224++0x03
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line.long 0x00 "CMP_A_EVENT_OUT_MODE,Compare A channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04F0228++0x03
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line.long 0x00 "CMP_A_PULSE_WID0,Compare A channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04F022C++0x03
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line.long 0x00 "CMP_A_PULSE_WID1,Compare A channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04F0230++0x03
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line.long 0x00 "CMP_A_00_VAL,Compare value for compare A channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F0234++0x03
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line.long 0x00 "CMP_A_01_VAL,Compare value for compare A channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F0238++0x03
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line.long 0x00 "CMP_A_10_VAL,Compare value for compare A channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F023C++0x03
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line.long 0x00 "CMP_A_11_VAL,Compare value for compare A channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F0240++0x03
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line.long 0x00 "CMP_A_DITHER,Compare A channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04F0244++0x03
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line.long 0x00 "CMP_A_OFFSET,Compare A offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04F0248++0x03
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line.long 0x00 "CMP_A_EID,Compare A channel event ID register"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,CMP11 event ID"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,CMP10 event ID"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,CMP01 event ID"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,CMP00 event ID"
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group ad:0xF04F0250++0x03
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line.long 0x00 "CMP_B_CONFIG,Compare B channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use.In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04F0254++0x03
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line.long 0x00 "CMP_B_EVENT_OUT_MODE,Compare B channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04F0258++0x03
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line.long 0x00 "CMP_B_PULSE_WID0,Compare B channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04F025C++0x03
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line.long 0x00 "CMP_B_PULSE_WID1,Compare B channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04F0260++0x03
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line.long 0x00 "CMP_B_00_VAL,Compare value for compare B channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F0264++0x03
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line.long 0x00 "CMP_B_01_VAL,Compare value for compare B channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F0268++0x03
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line.long 0x00 "CMP_B_10_VAL,Compare value for compare B channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F026C++0x03
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line.long 0x00 "CMP_B_11_VAL,Compare value for compare B channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F0270++0x03
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line.long 0x00 "CMP_B_DITHER,Compare B channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04F0274++0x03
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line.long 0x00 "CMP_B_OFFSET,Compare B offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04F0280++0x03
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line.long 0x00 "CMP_C_CONFIG,Compare C channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04F0284++0x03
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line.long 0x00 "CMP_C_EVENT_OUT_MODE,Compare C channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04F0288++0x03
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line.long 0x00 "CMP_C_PULSE_WID0,Compare C channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04F028C++0x03
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line.long 0x00 "CMP_C_PULSE_WID1,Compare C channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04F0290++0x03
|
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line.long 0x00 "CMP_C_00_VAL,Compare value for compare C channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F0294++0x03
|
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line.long 0x00 "CMP_C_01_VAL,Compare value for compare C channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F0298++0x03
|
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line.long 0x00 "CMP_C_10_VAL,Compare value for compare C channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F029C++0x03
|
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line.long 0x00 "CMP_C_11_VAL,Compare value for compare C channel cmp11 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F02A0++0x03
|
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line.long 0x00 "CMP_C_DITHER,Compare C channel DIther register"
|
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04F02A4++0x03
|
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line.long 0x00 "CMP_C_OFFSET,Compare C offset value register"
|
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04F02B0++0x03
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line.long 0x00 "CMP_D_CONFIG,Compare D channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 16. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 15. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 14. " RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and.." "0,1"
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textline " "
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bitfld.long 0x00 12.--13. "CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 10.--11. " SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 9. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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textline " "
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bitfld.long 0x00 6.--7. "CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 4.--5. " CNT_SEL ,Select compared counter 00: cnt_g0 01: lcnt 10/11: lcnt_d" "0,1,2,3"
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bitfld.long 0x00 2.--3. " CMP_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple mode" "0,1,2,3"
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bitfld.long 0x00 1. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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textline " "
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bitfld.long 0x00 0. "OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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group ad:0xF04F02B4++0x03
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line.long 0x00 "CMP_D_EVENT_OUT_MODE,Compare D channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04F02B8++0x03
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line.long 0x00 "CMP_D_PULSE_WID0,Compare D channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04F02BC++0x03
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line.long 0x00 "CMP_D_PULSE_WID1,Compare D channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04F02C0++0x03
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line.long 0x00 "CMP_D_00_VAL,Compare value for compare D channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F02C4++0x03
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line.long 0x00 "CMP_D_01_VAL,Compare value for compare D channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F02C8++0x03
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line.long 0x00 "CMP_D_10_VAL,Compare value for compare D channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F02CC++0x03
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line.long 0x00 "CMP_D_11_VAL,Compare value for compare D channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04F02D0++0x03
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line.long 0x00 "CMP_D_DITHER,Compare D channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04F02D4++0x03
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line.long 0x00 "CMP_D_OFFSET,Compare D offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04F02E0++0x03
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line.long 0x00 "CMP_CTRL,Compare control register"
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bitfld.long 0x00 28. " CMP_A_EID_UPD ,Update EID value. Will be auto clear after completing update EID value." "0,1"
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bitfld.long 0x00 27. " CMP_D1_INIT_UPD ,Update cmp_d1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 26. " CMP_D0_INIT_UPD ,Update cmp_d0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 25. " CMP_C1_INIT_UPD ,Update cmp_c1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 24. "CMP_C0_INIT_UPD ,Update cmp_c0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 23. " CMP_B1_INIT_UPD ,Update cmp_b1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 22. " CMP_B0_INIT_UPD ,Update cmp_b0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 21. " CMP_A1_INIT_UPD ,Update cmp_a1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 20. "CMP_A0_INIT_UPD ,Update cmp_a0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 19. " CMP_D1_INIT_STATUS ,cmp_d1 output initial status" "0,1"
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bitfld.long 0x00 18. " CMP_D0_INIT_STATUS ,cmp_d0 output initial status" "0,1"
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bitfld.long 0x00 17. " CMP_C1_INIT_STATUS ,cmp_c1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 16. "CMP_C0_INIT_STATUS ,cmp_c0 output initial status" "0,1"
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bitfld.long 0x00 15. " CMP_B1_INIT_STATUS ,cmp_b1 output initial status" "0,1"
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bitfld.long 0x00 14. " CMP_B0_INIT_STATUS ,cmp_b0 output initial status" "0,1"
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bitfld.long 0x00 13. " CMP_A1_INIT_STATUS ,cmp_a1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 12. "CMP_A0_INIT_STATUS ,cmp_a0 output initial status" "0,1"
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bitfld.long 0x00 11. " CMP_D_VAL_UPD ,Update all the compare value registers for compare D channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 10. " CMP_C_VAL_UPD ,Update all the compare value registers for compare C channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 9. " CMP_B_VAL_UPD ,Update all the compare value registers for compare B channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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textline " "
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bitfld.long 0x00 8. "CMP_A_VAL_UPD ,Update all the compare value registers for compare A channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 7. " CMP_D_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CMP_C_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 5. " CMP_B_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour.." "0,1"
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textline " "
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bitfld.long 0x00 4. "CMP_A_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 3. " CMP_D_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 2. " CMP_C_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 1. " CMP_B_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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textline " "
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bitfld.long 0x00 0. "CMP_A_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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group ad:0xF04F0300++0x03
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line.long 0x00 "CPT_A_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_A0 signals into one signal for capture channel A"
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bitfld.long 0x00 26. " QUAD_INDEX_POL ,When this bit is set, INDEX signal polarity is changed." "0,1"
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bitfld.long 0x00 25. " QUAD_HOME_POL ,When this bit is set, HOME signal polarity is changed." "0,1"
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bitfld.long 0x00 21.--24. " QUAD_CLR_SEL ,In quadrature mode, the counter CLR event can be configured to be initiated by HOME or INDEX input 0000: HOME high 0001: INDEX high 0010: HOME high and {PHASE_B, PHASE_A} = 2'b00; 0011: HOME high and {PHASE_B, PHASE_A} = 2'.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 17.--20. " QUAD_SET_SEL ,In quadrature mode, the counter SET event can be configured to be initiated by HOME or INDEX input 0000: HOME high 0001: INDEX high 0010: HOME high and {PHASE_B, PHASE_A} = 2'b00; 0011: HOME high and {PHASE_B, PHASE_A} = 2'.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 16. "QUAD_MODE_EN ,Quadrature mode enable" "0,1"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04F0304++0x03
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line.long 0x00 "CPT_A_SSE_REG,Signal synthesis for CAPTURE A"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04F0308++0x03
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line.long 0x00 "CPT_B_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_B0 signals into one signal for capture channel B"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04F030C++0x03
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line.long 0x00 "CPT_B_SSE_REG,Signal synthesis for CAPTURE B"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04F0310++0x03
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line.long 0x00 "CPT_C_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_C0 signals into one signal for capture channel C"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04F0314++0x03
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line.long 0x00 "CPT_C_SSE_REG,Signal synthesis for CAPTURE C"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04F0318++0x03
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line.long 0x00 "CPT_D_SSE_CTRL,Synthesis CPT_A0,CPT_B0,CPT_C0 and CPT_D0 inputs and CMP_D0 signals into one signal for capture channel D"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04F031C++0x03
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line.long 0x00 "CPT_D_SSE_REG,Signal synthesis for CAPTURE D"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04F0320++0x03
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line.long 0x00 "CMP_A_SSE_CTRL,Synthesis CMP_A0,CMP_B0,CMP_C0 and CMP_D0 outputs and CPT_A_SSE SO signals into one signal for compare channel A"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_A_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04F0324++0x03
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line.long 0x00 "CMP_A_SSE_REG,Signal synthesis for compare A output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04F0328++0x03
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line.long 0x00 "CMP_B_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_B_SSE SO signals into one signal for compare channel B"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_B_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04F032C++0x03
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line.long 0x00 "CMP_B_SSE_REG,Signal synthesis for compare B output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04F0330++0x03
|
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line.long 0x00 "CMP_C_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_C_SSE SO signals into one signal for compare channel C"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
|
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_C_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04F0334++0x03
|
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line.long 0x00 "CMP_C_SSE_REG,Signal synthesis for compare C output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04F0338++0x03
|
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line.long 0x00 "CMP_D_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CPT_D_SSE SO signals into one signal for compare channel D"
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bitfld.long 0x00 19. " SSE_FAULT_DET_EN ,SSE fault detect enable" "0,1"
|
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_D_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0. "SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04F033C++0x03
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line.long 0x00 "CMP_D_SSE_REG,Signal synthesis for compare D output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04F0340++0x03
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line.long 0x00 "CPT_A_INPUT_SEL,Capture A channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_A1 1000: CMP_A1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_A_SSE_SO 0001: CPT_A1 0010: CMP_A1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_A_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_A_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F0344++0x03
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line.long 0x00 "CPT_B_INPUT_SEL,Capture B channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_B1 1000: CMP_B1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_B_SSE_SO 0001: CPT_B1 0010: CMP_B1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_B_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_B_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F0348++0x03
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line.long 0x00 "CPT_C_INPUT_SEL,Capture C channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_C1 1000: CMP_C1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_C_SSE_SO 0001: CPT_C1 0010: CMP_C1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_C_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_C_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F034C++0x03
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line.long 0x00 "CPT_D_INPUT_SEL,Capture D channel input select register"
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bitfld.long 0x00 12.--15. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_D1 1000: CMP_D1 1001: Level high 1010: Level high 1011: Level high .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SIG_SEL ,SIG input select 0000: CPT_D_SSE_SO 0001: CPT_D1 0010: CMP_D1 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_D_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CMP_D_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F0350++0x03
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line.long 0x00 "CMP_A_INPUT_SEL,Compare A channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F0354++0x03
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line.long 0x00 "CMP_B_INPUT_SEL,Compare B channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F0358++0x03
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line.long 0x00 "CMP_C_INPUT_SEL,Compare C channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F035C++0x03
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line.long 0x00 "CMP_D_INPUT_SEL,Compare D channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F0360++0x03
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line.long 0x00 "CNT_G0_INPUT_SEL,Counter G0 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F0364++0x03
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line.long 0x00 "CNT_G1_INPUT_SEL,Counter G1 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F0368++0x03
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line.long 0x00 "EXT_OUTPUT_SEL,External output source select register"
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bitfld.long 0x00 8.--11. " DIR_SEL ,DIR input select 0000: Level high 0001: Level low 0010: CPT_A_SSE_DIR 0011: CPT_A_SSE_SO 0100: CPT_B_SSE_SO 0101: CPT_C_SSE_SO 0110: CPT_D_SSE_SO 0111: CPT_A1 1000: CPT_B1 1001: CPT_C1 1010: CPT_D1 1011: CMP_A1 1100: SW_TRIG0.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_CLR 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CPT_A_SSE_SET 0011: CPT_A_CE 0100: CPT_B_CE 0101: CPT_C_CE 0110: CPT_D_CE 0111: CNT_G0_CE 1000: CNT_G1_CE 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04F036C++0x03
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line.long 0x00 "ETM_POL_INV,Event trigger polarity invert"
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bitfld.long 0x00 30. " EXT_DIR ,Polarity invert" "0,1"
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bitfld.long 0x00 29. " EXT_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 28. " EXT_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 27. " CNT_G1_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 26. "CNT_G1_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 25. " CNT_G0_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 24. " CNT_G0_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 23. " CMP_D_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 22. "CMP_D_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 21. " CMP_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 20. " CMP_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 19. " CMP_B_CLR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 18. "CMP_B_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 17. " CMP_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 16. " CMP_A_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 15. " CPT_D_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 14. "CPT_D_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 13. " CPT_D_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 12. " CPT_D_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 11. " CPT_C_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 10. "CPT_C_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 9. " CPT_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 8. " CPT_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 7. " CPT_B_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 6. "CPT_B_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 5. " CPT_B_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 4. " CPT_B_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 3. " CPT_A_DIR ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 2. "CPT_A_SIG ,Polarity invert" "0,1"
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bitfld.long 0x00 1. " CPT_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 0. " CPT_A_SET ,Polarity invert" "0,1"
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group ad:0xF04F0370++0x03
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line.long 0x00 "CPT_SW_TRIG,Capture signal software trigger register"
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bitfld.long 0x00 11. " CPT_D_SIG ,Set high to generate SIG pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 10. " CPT_C_SIG ,Set high to generate SIG pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 9. " CPT_B_SIG ,Set high to generate SIG pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 8. " CPT_A_SIG ,Set high to generate SIG pulse signal for capture A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 7. "CPT_D_CLR ,Set high to generate CLR pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CPT_C_CLR ,Set high to generate CLR pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CPT_B_CLR ,Set high to generate CLR pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CPT_A_CLR ,Set high to generate CLR pulse signal for capture A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CPT_D_SET ,Set high to generate SET pulse signal for capture D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CPT_C_SET ,Set high to generate SET pulse signal for capture C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CPT_B_SET ,Set high to generate SET pulse signal for capture B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CPT_A_SET ,Set high to generate SET pulse signal for capture A channel. Auto clear after set." "0,1"
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group ad:0xF04F0374++0x03
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line.long 0x00 "CMP_SW_TRIG,Compare signal software trigger register"
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bitfld.long 0x00 7. " CMP_D_CLR ,Set high to generate CLR pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CMP_C_CLR ,Set high to generate CLR pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CMP_B_CLR ,Set high to generate CLR pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CMP_A_CLR ,Set high to generate CLR pulse signal for compare A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CMP_D_SET ,Set high to generate SET pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CMP_C_SET ,Set high to generate SET pulse signal for compare C channel. Auto clear after set." "0,1"
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|
bitfld.long 0x00 1. " CMP_B_SET ,Set high to generate SET pulse signal for compare B channel. Auto clear after set." "0,1"
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|
bitfld.long 0x00 0. " CMP_A_SET ,Set high to generate SET pulse signal for compare A channel. Auto clear after set." "0,1"
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|
group ad:0xF04F0378++0x03
|
|
line.long 0x00 "CNT_EXT_SW_TRIG,Counter and external signal software trigger register"
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|
bitfld.long 0x00 5. " EXT_CLR ,Set high to generate CLR pulse signal for external output. Auto clear after set." "0,1"
|
|
bitfld.long 0x00 4. " EXT_SET ,Set high to generate SET pulse signal for external output. Auto clear after set." "0,1"
|
|
bitfld.long 0x00 3. " CNT_G1_CLR ,Set high to generate CLR pulse signal for CNT_G1. Auto clear after set." "0,1"
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|
bitfld.long 0x00 2. " CNT_G1_SET ,Set high to generate SET pulse signal for CNT_G1. Auto clear after set." "0,1"
|
|
textline " "
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|
bitfld.long 0x00 1. "CNT_G0_CLR ,Set high to generate CLR pulse signal for CNT_G0. Auto clear after set." "0,1"
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|
bitfld.long 0x00 0. " CNT_G0_SET ,Set high to generate SET pulse signal for CNT_G0. Auto clear after set." "0,1"
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|
group ad:0xF04F0380++0x03
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|
line.long 0x00 "SW_TRIG_CTRL,SW trigger event generation control"
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bitfld.long 0x00 15. " SW_TRIG3_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 14. " SW_TRIG3_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 13. " SW_TRIG3_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 12. " SW_TRIG3_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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|
textline " "
|
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bitfld.long 0x00 11. "SW_TRIG2_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 10. " SW_TRIG2_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 9. " SW_TRIG2_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 8. " SW_TRIG2_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
|
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bitfld.long 0x00 7. "SW_TRIG1_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 6. " SW_TRIG1_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 5. " SW_TRIG1_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 4. " SW_TRIG1_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
|
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bitfld.long 0x00 3. "SW_TRIG0_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 2. " SW_TRIG0_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 1. " SW_TRIG0_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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group ad:0xF04F0384++0x03
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line.long 0x00 "SW_TRIG_STATUS,SW trigger outputs status"
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bitfld.long 0x00 3. " SW_TRIG3 ,SW trigger output" "0,1"
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bitfld.long 0x00 2. " SW_TRIG2 ,SW trigger output" "0,1"
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bitfld.long 0x00 1. " SW_TRIG1 ,SW trigger output" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0 ,SW trigger output" "0,1"
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group ad:0xF04F0388++0x03
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line.long 0x00 "SW_TRIG_PULSE0,SW trigger0 and trigger1 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG1_WIDTH ,Pulse width of SW trigger1"
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hexmask.long.word 0x00 0.--15. 1. " TRIG0_WIDTH ,Pulse width of SW trigger0"
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group ad:0xF04F038C++0x03
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line.long 0x00 "SW_TRIG_PULSE1,SW trigger2 and trigger3 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG3_WIDTH ,Pulse width of SW trigger3"
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hexmask.long.word 0x00 0.--15. 1. " TRIG2_WIDTH ,Pulse width of SW trigger2"
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group ad:0xF04F0390++0x03
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line.long 0x00 "CNT_G0_SNAP_SHOT_SEL,CNT_G0 snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04F0394++0x03
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line.long 0x00 "CNT_G1_SNAP_SHOT_SEL,CNT_G1 snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04F0398++0x03
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line.long 0x00 "LCNT_A_SNAP_SHOT_SEL,LCNT_A snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04F039C++0x03
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line.long 0x00 "LCNT_B_SNAP_SHOT_SEL,LCNT_B snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
|
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group ad:0xF04F03A0++0x03
|
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line.long 0x00 "LCNT_C_SNAP_SHOT_SEL,LCNT_C snapshot source select"
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hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04F03A4++0x03
|
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line.long 0x00 "LCNT_D_SNAP_SHOT_SEL,LCNT_D snapshot source select"
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|
hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04F03A8++0x03
|
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line.long 0x00 "SNAP_SHOT_O_SEL,Snapshot output snapshot source select"
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|
hexmask.long.byte 0x00 0.--6. 1. " TRIG_SEL ,Each bit selects one of trgger source. Can be configured to one or more than one snapshot event sources. bit0: read of CNT_G0 bit1: read of CNT_G1 bit2: read of LCNT_A bit3: read of LCNT_B bit4: read of LCNT_C bit5: read of .."
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group ad:0xF04F0400++0x03
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line.long 0x00 "CPT_A0_FLT,Filter setting for CPT_A0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
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group ad:0xF04F0404++0x03
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line.long 0x00 "CPT_B0_FLT,Filter setting for CPT_B0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
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group ad:0xF04F0408++0x03
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line.long 0x00 "CPT_C0_FLT,Filter setting for CPT_C0 input."
|
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
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group ad:0xF04F040C++0x03
|
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line.long 0x00 "CPT_D0_FLT,Filter setting for CPT_D0 input."
|
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04F0410++0x03
|
|
line.long 0x00 "FAULT0_FLT,Filter setting for fault0 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04F0414++0x03
|
|
line.long 0x00 "FAULT1_FLT,Filter setting for fault1 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04F0418++0x03
|
|
line.long 0x00 "FAULT2_FLT,Filter setting for fault2 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04F041C++0x03
|
|
line.long 0x00 "FAULT3_FLT,Filter setting for fault3 input."
|
|
hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
|
|
bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge capture channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for capture channel." "0,1"
|
|
group ad:0xF04F0420++0x03
|
|
line.long 0x00 "SYNC_DIS,Synchronization DIsable control register"
|
|
bitfld.long 0x00 15. " FAULT3 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 14. " FAULT2 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 13. " FAULT1 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 12. " FAULT0 ,DIsable synchronization" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "SNAP_SHOT ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 9. " EXT_CLR ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 8. " EXT_SET ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 7. " CPT_D1 ,DIsable synchronization" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "CPT_C1 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 5. " CPT_B1 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 4. " CPT_A1 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 3. " CPT_D0 ,DIsable synchronization" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CPT_C0 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 1. " CPT_B0 ,DIsable synchronization" "0,1"
|
|
bitfld.long 0x00 0. " CPT_A0 ,DIsable synchronization" "0,1"
|
|
group ad:0xF04F0440++0x03
|
|
line.long 0x00 "CMP_A_FAULT_EVENT_CTRL,Compare A channel event control register"
|
|
bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04F0444++0x03
|
|
line.long 0x00 "CMP_B_FAULT_EVENT_CTRL,Compare B channel event control register"
|
|
bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04F0448++0x03
|
|
line.long 0x00 "CMP_C_FAULT_EVENT_CTRL,Compare C channel event control register"
|
|
bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04F044C++0x03
|
|
line.long 0x00 "CMP_D_FAULT_EVENT_CTRL,Compare D channel event control register"
|
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
|
|
bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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|
bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
|
bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
|
bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
|
group ad:0xF04F0460++0x03
|
|
line.long 0x00 "CMP_A_DTI_CTRL,Dead time insertion control register for compare A channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04F0464++0x03
|
|
line.long 0x00 "CMP_A_DTI_WID,Dead time insertion width register for compare A channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04F0468++0x03
|
|
line.long 0x00 "CMP_B_DTI_CTRL,Dead time insertion control register for compare B channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04F046C++0x03
|
|
line.long 0x00 "CMP_B_DTI_WID,Dead time insertion width register for compare B channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04F0470++0x03
|
|
line.long 0x00 "CMP_C_DTI_CTRL,Dead time insertion control register for compare C channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04F0474++0x03
|
|
line.long 0x00 "CMP_C_DTI_WID,Dead time insertion width register for compare C channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04F0478++0x03
|
|
line.long 0x00 "CMP_D_DTI_CTRL,Dead time insertion control register for compare D channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04F047C++0x03
|
|
line.long 0x00 "CMP_D_DTI_WID,Dead time insertion width register for compare D channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04F0500++0x03
|
|
line.long 0x00 "SIGNAL_STATUS,Signal status register"
|
|
bitfld.long 0x00 31. " CPT_D_CLR ,Capture D clear signal" "0,1"
|
|
bitfld.long 0x00 30. " CPT_D_SET ,Capture D set signal" "0,1"
|
|
bitfld.long 0x00 29. " CPT_D_DIR ,Capture D DIR signal" "0,1"
|
|
bitfld.long 0x00 28. " CPT_D_SIG ,Capture D SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "CPT_C_CLR ,Capture C clear signal" "0,1"
|
|
bitfld.long 0x00 26. " CPT_C_SET ,Capture C set signal" "0,1"
|
|
bitfld.long 0x00 25. " CPT_C_DIR ,Capture C DIR signal" "0,1"
|
|
bitfld.long 0x00 24. " CPT_C_SIG ,Capture C SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "CPT_B_CLR ,Capture B clr signal" "0,1"
|
|
bitfld.long 0x00 22. " CPT_B_SET ,Capture B set signal" "0,1"
|
|
bitfld.long 0x00 21. " CPT_B_DIR ,Capture B DIR signal" "0,1"
|
|
bitfld.long 0x00 20. " CPT_B_SIG ,Capture B SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CPT_A_CLR ,Capture A clear signal" "0,1"
|
|
bitfld.long 0x00 18. " CPT_A_SET ,Capture A set signal" "0,1"
|
|
bitfld.long 0x00 17. " CPT_A_DIR ,Capture A DIR signal" "0,1"
|
|
bitfld.long 0x00 16. " CPT_A_SIG ,Capture A SIG signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_CLR ,Compare D clear signal" "0,1"
|
|
bitfld.long 0x00 14. " CMP_D_SET ,Compare D set signal" "0,1"
|
|
bitfld.long 0x00 13. " CMP_C_CLR ,Compare C clear signal" "0,1"
|
|
bitfld.long 0x00 12. " CMP_C_SET ,Compare C set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_B_CLR ,Compare B clear signal" "0,1"
|
|
bitfld.long 0x00 10. " CMP_B_SET ,Compare B set signal" "0,1"
|
|
bitfld.long 0x00 9. " CMP_A_CLR ,Compare A clear signal" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A_SET ,Compare A set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D1 ,Compare D1 signal" "0,1"
|
|
bitfld.long 0x00 6. " CMP_D0 ,Compare D0 signal" "0,1"
|
|
bitfld.long 0x00 5. " CMP_C1 ,Compare C1 signal" "0,1"
|
|
bitfld.long 0x00 4. " CMP_C0 ,Compare C0 signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CMP_B1 ,Compare B1 signal" "0,1"
|
|
bitfld.long 0x00 2. " CMP_B0 ,Compare B0 signal" "0,1"
|
|
bitfld.long 0x00 1. " CMP_A1 ,Compare A1 signal" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A0 ,Compare A0 signal" "0,1"
|
|
group ad:0xF04F0FFC++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "EPWM"
|
|
tree "EPWM1"
|
|
width 28.
|
|
group ad:0xF0480000++0x03
|
|
line.long 0x00 "INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,CNT_G1 overflow" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,CNT_G0 overflow" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Compare D event happens" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Compare C event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Compare B event happens" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Compare A event happens" "0,1"
|
|
group ad:0xF0480004++0x03
|
|
line.long 0x00 "INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Status enable" "0,1"
|
|
group ad:0xF0480008++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Singal enable" "0,1"
|
|
group ad:0xF048000C++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA,Correctable error interrupt status register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF0480010++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA_EN,Correctable error interrupt status enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF0480014++0x03
|
|
line.long 0x00 "COR_ERR_INT_SIG_EN,Correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF0480018++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA,Uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF048001C++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF0480020++0x03
|
|
line.long 0x00 "UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF0480024++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata corrctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0480028++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF048002C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0480030++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Cock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Cock monitor compare0 erro" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error." "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error." "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error." "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0480034++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0480038++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,CONFIG_DMA eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF048003C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_1,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF0480040++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN_1,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF0480044++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN_1,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,CONFIG_DMA eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF048004C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF0480050++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF0480054++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF048005C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0480060++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,RAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF0480064++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0480068++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,RAM rdata SECDED monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF048006C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,RAM rdata ECC SECDED monitor error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0480070++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF0480074++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF0480080++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 16.--18. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0480084++0x03
|
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line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0480088++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF048008C++0x03
|
|
line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0480090++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 6. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
|
bitfld.long 0x00 5. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
|
bitfld.long 0x00 4. " CNT_OVF ,Counter overflow and snapshot interrupt error injection." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Channel D interrupt error injection." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CHN_C ,Channel C interrupt error injection." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B ,Channel B interrupt error injection." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Channel A interrupt error injection." "0,1"
|
|
group ad:0xF0480094++0x03
|
|
line.long 0x00 "CLK_MON_CMP_ERR_INJ,Clock monitor compare error injection r"
|
|
bitfld.long 0x00 2.--3. " ERR1 ,Clock monitor 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ERR0 ,Clock monitor 0" "0,1,2,3"
|
|
group ad:0xF04800A0++0x03
|
|
line.long 0x00 "CLK_CONFIG,EPMW clock select and DIvider configuration."
|
|
bitfld.long 0x00 31. " CLK_CHANGE_UPD ,Set this bit to make new DIV_NUM value effective. Will be auto cleared after new DIV_NUM is effective" "0,1"
|
|
bitfld.long 0x00 16.--17. " SRC_CLK_SEL ,Clock source select. 00: High frequency(HF) clock, update to 400mhz. 01: Alternative High frequency(AHF) clock, update to 400mhz. 10: External clock. 11: Low power(LP) clock, typically from low speed on chip RCOSC." "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV_NUM ,DIvider number for timer clock."
|
|
group ad:0xF04800A4++0x03
|
|
line.long 0x00 "CLK_MON_EN,Clock monitor enable register"
|
|
bitfld.long 0x00 2. " CMP_SET ,When enable or DIsable clock monitor, set this bit together. This bit is used to inDIcate configuration is completed." "0,1"
|
|
bitfld.long 0x00 1. " EN_N ,Active low.Enable clock monitor1" "0,1"
|
|
bitfld.long 0x00 0. " EN_P ,Active high.Enable clock monitor0" "0,1"
|
|
group ad:0xF04800A8++0x03
|
|
line.long 0x00 "SW_RST,Software reset"
|
|
bitfld.long 0x00 9. " CNT_G1 ,Reset CNT_G1.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0 ,Reset CNT_G0.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 7. " FIFO_D ,Reset FIFO D relative logic. Will be auto cleared after reset complete" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C ,Reset FIFO C relative logic. Will be auto cleared after reset complete" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "FIFO_B ,Reset FIFO B relative logic. Will be auto cleared after reset complete" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A ,Reset FIFO A relative logic. Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Reset CMP_D. Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Reset CMP_C.Will be auto cleared after reset complete." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Reset CMP_B.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Reset CMP_A.Will be auto cleared after reset complete." "0,1"
|
|
group ad:0xF04800B0++0x03
|
|
line.long 0x00 "CHN_DMA_CTRL,DMA control register"
|
|
bitfld.long 0x00 30. " TWO_CHN_BD_MODE ,When this bit is enable, CMP_B and CMP_D block are sharing DMA_B and FIFO_B. RAM_B and RAM_D are combined are worked with FIFO_B. If four_chn_mode is enable, this bit is ignored." "0,1"
|
|
bitfld.long 0x00 29. " TWO_CHN_AC_MODE ,When this bit is enable, CMP_A and CMP_C block are sharing DMA_A and FIFO_A. RAM_A and RAM_C are combined are worked with FIFO_A. If four_chn_mode is enable, this bit is ignored." "0,1"
|
|
bitfld.long 0x00 28. " FOUR_CHN_MODE ,When this bit is enable, 4 compare blocks are sharing DMA_A and FIFO_A. RAM_A, RAM_B,RAM_C and RAM_D are combined are worked with FIFO_A." "0,1"
|
|
bitfld.long 0x00 26.--27. " CMP_D_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. "CMP_C_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " CMP_B_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " CMP_A_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
|
|
bitfld.long 0x00 19. " CMP_D_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. "CMP_C_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
|
|
bitfld.long 0x00 14.--15. " CMP_D_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. "CMP_C_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " CMP_B_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " CMP_A_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
|
|
bitfld.long 0x00 7. " CHN_D_SIG_MASK ,Mask channel D dma request hardware output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "CHN_C_SIG_MASK ,Mask channel C dma request hardware output" "0,1"
|
|
bitfld.long 0x00 5. " CHN_B_SIG_MASK ,Mask channel B dma request hardware output" "0,1"
|
|
bitfld.long 0x00 4. " CHN_A_SIG_MASK ,Mask channel A dma request hardware output" "0,1"
|
|
bitfld.long 0x00 3. " CHN_D_EN ,Enable dma request for COMPARE D channel accorDIng to channel D FIFO WML." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CHN_C_EN ,Enable dma request for COMPARE C channel accorDIng to channel C FIFO WML." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B_EN ,Enable dma request for COMPARE B channel accorDIng to channel B FIFO WML." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A_EN ,Enable dma request for COMPARE A channel accorDIng to channle A FIFO WML." "0,1"
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|
group ad:0xF04800B4++0x03
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|
line.long 0x00 "DMA_WML,DMA watermark leverl register"
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|
bitfld.long 0x00 24.--27. " CHN_D ,Waterwark level setting for channel D DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. " CHN_C ,Waterwark level setting for channel C DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--12. " CHN_B ,Waterwark level setting for channel B DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 0.--5. 1. " CHN_A ,Waterwark level setting for channel A DMA"
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group ad:0xF04800B8++0x03
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line.long 0x00 "CONFIG_DMA_CTL,Configuration dma control register"
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hexmask.long.byte 0x00 2.--7. 1. " TRIG_SEL ,Select source to trigger dma request. 1. CMP_A_CE 2. CMP_B_CE 3. CMP_C_CE 4. CMP_D_CE 5. CNT_G0_CE 6. CNT_G1_CE"
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bitfld.long 0x00 1. " SIG_MASK ,Mask configuration dma request hardware output" "0,1"
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bitfld.long 0x00 0. " EN ,DMA enable for register configuration" "0,1"
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group ad:0xF04800BC++0x03
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line.long 0x00 "FIFO_REQ_STATUS,FIFO request status"
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bitfld.long 0x00 3. " FIFO_D ,FIFO D reach water mark level" "0,1"
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bitfld.long 0x00 2. " FIFO_C ,FIFO C reach water mark level" "0,1"
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bitfld.long 0x00 1. " FIFO_B ,FIFO B reach water mark level" "0,1"
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bitfld.long 0x00 0. " FIFO_A ,FIFO A reach water mark level" "0,1"
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group ad:0xF04800C0++0x03
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line.long 0x00 "FIFO_A,FIFO_entry for compare channel A"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04800C4++0x03
|
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line.long 0x00 "FIFO_B,FIFO_entry for compare channel B"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
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group ad:0xF04800C8++0x03
|
|
line.long 0x00 "FIFO_C,FIFO_entry for compare channel C"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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|
group ad:0xF04800CC++0x03
|
|
line.long 0x00 "FIFO_D,FIFO_entry for compare channel D"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
|
|
group ad:0xF04800D0++0x03
|
|
line.long 0x00 "FIFO_STA0,FIFO status0 register."
|
|
bitfld.long 0x00 24. " FIFO_ERR_B ,InDIcate FIFO underrun or overrun." "0,1"
|
|
hexmask.long.byte 0x00 18.--23. 1. " FIFO_ENTRIES_B ,InDIcate FIFO data number"
|
|
bitfld.long 0x00 17. " FIFO_EMPTY_B ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 16. " FIFO_FULL_B ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "FIFO_ERR_A ,InDIcate FIFO underrun or overrun." "0,1"
|
|
hexmask.long.byte 0x00 2.--8. 1. " FIFO_ENTRIES_A ,InDIcate FIFO data number"
|
|
bitfld.long 0x00 1. " FIFO_EMPTY_A ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 0. " FIFO_FULL_A ,InDIcate FIFO is full." "0,1"
|
|
group ad:0xF04800D4++0x03
|
|
line.long 0x00 "FIFO_STA1,FIFO status1 register."
|
|
bitfld.long 0x00 23. " FIFO_ERR_D ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 18.--22. " FIFO_ENTRIES_D ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17. " FIFO_EMPTY_D ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 16. " FIFO_FULL_D ,InDIcate FIFO is full." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "FIFO_ERR_C ,InDIcate FIFO underrun or overrun." "0,1"
|
|
bitfld.long 0x00 2.--6. " FIFO_ENTRIES_C ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " FIFO_EMPTY_C ,InDIcate FIFO is empty." "0,1"
|
|
bitfld.long 0x00 0. " FIFO_FULL_C ,InDIcate FIFO is full." "0,1"
|
|
group ad:0xF0480100++0x03
|
|
line.long 0x00 "CNT_G0_INIT,Counter G0 initial value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF0480104++0x03
|
|
line.long 0x00 "CNT_G0_OVF,Counter G0 overflow value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF0480108++0x03
|
|
line.long 0x00 "CNT_G0_CFG,CNT_G0 configuration register."
|
|
bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset coun" "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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|
bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF048010C++0x03
|
|
line.long 0x00 "CNT_G0_EN,CNT_G0 enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
|
group ad:0xF0480110++0x03
|
|
line.long 0x00 "CNT_G0,CNT_G0 TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF0480114++0x03
|
|
line.long 0x00 "CNT_G0_MFC,cnt_g0 Modulation Frequency Control"
|
|
bitfld.long 0x00 0.--3. " MFC_UP ,ncreasing modulation frequency up to 2^N times, where N ranged in between [0,10]. 0 means MFC DIsable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0480120++0x03
|
|
line.long 0x00 "CNT_G1_INIT,Counter G1 initial value registe"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF0480124++0x03
|
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line.long 0x00 "CNT_G1_OVF,Counter G1 overflow value registe"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
|
group ad:0xF0480128++0x03
|
|
line.long 0x00 "CNT_G1_CFG,CNT_G1 configuration register."
|
|
bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset coun" "0,1"
|
|
bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
|
bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW" "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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|
group ad:0xF048012C++0x03
|
|
line.long 0x00 "CNT_G1_EN,CNT_G1 enable register"
|
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
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group ad:0xF0480130++0x03
|
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line.long 0x00 "CNT_G1,CNT_G1 TIMER"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
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group ad:0xF0480134++0x03
|
|
line.long 0x00 "CNT_G1_MFC,CNT_G1 Modulation Frequency Control"
|
|
bitfld.long 0x00 0.--3. " MFC_UP ,ncreasing modulation frequency up to 2^N times, where N ranged in between [0,10]. 0 means MFC DIsable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0480220++0x03
|
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line.long 0x00 "CMP_A_CONFIG,Compare A channel configuration register"
|
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
|
|
bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
|
group ad:0xF0480224++0x03
|
|
line.long 0x00 "CMP_A_EVENT_OUT_MODE,Compare A channel event output mode register"
|
|
bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp1 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
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group ad:0xF0480228++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID0,Compare A channel output pulse width register0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
|
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
|
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
|
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
|
|
group ad:0xF048022C++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID1,Compare A channel output pulse width register1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
|
|
group ad:0xF0480230++0x03
|
|
line.long 0x00 "CMP_A_00_VAL,Compare value for compare A channel cmp00 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF0480234++0x03
|
|
line.long 0x00 "CMP_A_01_VAL,Compare value for compare A channel cmp01 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF0480238++0x03
|
|
line.long 0x00 "CMP_A_10_VAL,Compare value for compare A channel cmp10 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF048023C++0x03
|
|
line.long 0x00 "CMP_A_11_VAL,Compare value for compare A channel cmp11 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF0480240++0x03
|
|
line.long 0x00 "CMP_A_DITHER,Compare A channel DIther register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
|
|
group ad:0xF0480244++0x03
|
|
line.long 0x00 "CMP_A_OFFSET,Compare A offset value register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
|
group ad:0xF048024C++0x03
|
|
line.long 0x00 "CMP_A_EID,Compare A channel event ID register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,CMP11 event ID"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,CMP10 event ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,CMP01 event ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,CMP00 event ID"
|
|
group ad:0xF0480250++0x03
|
|
line.long 0x00 "CMP_B_CONFIG,Compare B channel configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
|
|
bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
|
bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
|
|
bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
|
|
bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
|
group ad:0xF0480254++0x03
|
|
line.long 0x00 "CMP_B_EVENT_OUT_MODE,Compare B channel event output mode register"
|
|
bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0480258++0x03
|
|
line.long 0x00 "CMP_B_PULSE_WID0,Compare B channel output pulse width register0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF048025C++0x03
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line.long 0x00 "CMP_B_PULSE_WID1,Compare B channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF0480260++0x03
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line.long 0x00 "CMP_B_00_VAL,Compare value for compare B channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0480264++0x03
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|
line.long 0x00 "CMP_B_01_VAL,Compare value for compare B channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0480268++0x03
|
|
line.long 0x00 "CMP_B_10_VAL,Compare value for compare B channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF048026C++0x03
|
|
line.long 0x00 "CMP_B_11_VAL,Compare value for compare B channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0480270++0x03
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line.long 0x00 "CMP_B_DITHER,Compare B channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF0480274++0x03
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line.long 0x00 "CMP_B_OFFSET,Compare B offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF0480280++0x03
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line.long 0x00 "CMP_C_CONFIG,Compare C channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF0480284++0x03
|
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line.long 0x00 "CMP_C_EVENT_OUT_MODE,Compare C channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF0480288++0x03
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line.long 0x00 "CMP_C_PULSE_WID0,Compare C channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF048028C++0x03
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line.long 0x00 "CMP_C_PULSE_WID1,Compare C channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF0480290++0x03
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line.long 0x00 "CMP_C_00_VAL,Compare value for compare C channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0480294++0x03
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line.long 0x00 "CMP_C_01_VAL,Compare value for compare C channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0480298++0x03
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line.long 0x00 "CMP_C_10_VAL,Compare value for compare C channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF048029C++0x03
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line.long 0x00 "CMP_C_11_VAL,Compare value for compare C channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04802A0++0x03
|
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line.long 0x00 "CMP_C_DITHER,Compare C channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04802A4++0x03
|
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line.long 0x00 "CMP_C_OFFSET,Compare C offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04802B0++0x03
|
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line.long 0x00 "CMP_D_CONFIG,Compare D channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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textline " "
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF04802B4++0x03
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line.long 0x00 "CMP_D_EVENT_OUT_MODE,Compare D channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04802B8++0x03
|
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line.long 0x00 "CMP_D_PULSE_WID0,Compare D channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04802BC++0x03
|
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line.long 0x00 "CMP_D_PULSE_WID1,Compare D channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04802C0++0x03
|
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line.long 0x00 "CMP_D_00_VAL,Compare value for compare D channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04802C4++0x03
|
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line.long 0x00 "CMP_D_01_VAL,Compare value for compare D channel cmp01 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
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group ad:0xF04802C8++0x03
|
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line.long 0x00 "CMP_D_10_VAL,Compare value for compare D channel cmp10 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
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group ad:0xF04802CC++0x03
|
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line.long 0x00 "CMP_D_11_VAL,Compare value for compare D channel cmp11 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
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group ad:0xF04802D0++0x03
|
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line.long 0x00 "CMP_D_DITHER,Compare D channel DIther register"
|
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
|
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group ad:0xF04802D4++0x03
|
|
line.long 0x00 "CMP_D_OFFSET,Compare D offset value register"
|
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
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group ad:0xF04802E0++0x03
|
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line.long 0x00 "CMP_CTRL,Compare control register"
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bitfld.long 0x00 28. " CMP_A_EID_UPD ,Update EID value. Will be auto clear after completing update EID value." "0,1"
|
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bitfld.long 0x00 27. " CMP_D1_INIT_UPD ,Update cmp_d1 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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bitfld.long 0x00 26. " CMP_D0_INIT_UPD ,Update cmp_d0 output initial value. Will be auto clear after completing update initial value." "0,1"
|
|
bitfld.long 0x00 25. " CMP_C1_INIT_UPD ,Update cmp_c1 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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textline " "
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bitfld.long 0x00 24. "CMP_C0_INIT_UPD ,Update cmp_c0 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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bitfld.long 0x00 23. " CMP_B1_INIT_UPD ,Update cmp_b1 output initial value. Will be auto clear after completing update initial value." "0,1"
|
|
bitfld.long 0x00 22. " CMP_B0_INIT_UPD ,Update cmp_b0 output initial value. Will be auto clear after completing update initial value." "0,1"
|
|
bitfld.long 0x00 21. " CMP_A1_INIT_UPD ,Update cmp_a1 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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textline " "
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bitfld.long 0x00 20. "CMP_A0_INIT_UPD ,Update cmp_a0 output initial value. Will be auto clear after completing update initial value." "0,1"
|
|
bitfld.long 0x00 19. " CMP_D1_INIT_STATUS ,cmp_d1 output initial status" "0,1"
|
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bitfld.long 0x00 18. " CMP_D0_INIT_STATUS ,cmp_d0 output initial status" "0,1"
|
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bitfld.long 0x00 17. " CMP_C1_INIT_STATUS ,cmp_c1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 16. "CMP_C0_INIT_STATUS ,cmp_c0 output initial status" "0,1"
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bitfld.long 0x00 15. " CMP_B1_INIT_STATUS ,cmp_b1 output initial status" "0,1"
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bitfld.long 0x00 14. " CMP_B0_INIT_STATUS ,cmp_b0 output initial status" "0,1"
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bitfld.long 0x00 13. " CMP_A1_INIT_STATUS ,cmp_a1 output initial status" "0,1"
|
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textline " "
|
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bitfld.long 0x00 12. "CMP_A0_INIT_STATUS ,cmp_a0 output initial status" "0,1"
|
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bitfld.long 0x00 11. " CMP_D_VAL_UPD ,Update all the compare value registers for compare D channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
|
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bitfld.long 0x00 10. " CMP_C_VAL_UPD ,Update all the compare value registers for compare C channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
|
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bitfld.long 0x00 9. " CMP_B_VAL_UPD ,Update all the compare value registers for compare B channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
|
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textline " "
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bitfld.long 0x00 8. "CMP_A_VAL_UPD ,Update all the compare value registers for compare A channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 7. " CMP_D_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CMP_C_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 5. " CMP_B_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour.." "0,1"
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textline " "
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bitfld.long 0x00 4. "CMP_A_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
|
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bitfld.long 0x00 3. " CMP_D_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
|
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bitfld.long 0x00 2. " CMP_C_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
|
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bitfld.long 0x00 1. " CMP_B_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
|
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textline " "
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bitfld.long 0x00 0. "CMP_A_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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group ad:0xF0480320++0x03
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line.long 0x00 "CMP_A_SSE_CTRL,Synthesis CMP_A0,CMP_B0,CMP_C0 and CMP_D0 outputs and CMP_A1 signals into one signal for compare channel A"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_A_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF0480324++0x03
|
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line.long 0x00 "CMP_A_SSE_REG,Signal synthesis for compare A output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF0480328++0x03
|
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line.long 0x00 "CMP_B_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_B1 signals into one signal for compare channel B"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_B_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF048032C++0x03
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line.long 0x00 "CMP_B_SSE_REG,Signal synthesis for compare B output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF0480330++0x03
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line.long 0x00 "CMP_C_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_C1 signals into one signal for compare channel C"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_C_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF0480334++0x03
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line.long 0x00 "CMP_C_SSE_REG,Signal synthesis for compare C output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF0480338++0x03
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line.long 0x00 "CMP_D_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_D1 signals into one signal for compare channel D"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_D_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF048033C++0x03
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line.long 0x00 "CMP_D_SSE_REG,Signal synthesis for compare D output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF0480350++0x03
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line.long 0x00 "CMP_A_INPUT_SEL,Compare A channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0480354++0x03
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line.long 0x00 "CMP_B_INPUT_SEL,Compare B channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0480358++0x03
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line.long 0x00 "CMP_C_INPUT_SEL,Compare C channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF048035C++0x03
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line.long 0x00 "CMP_D_INPUT_SEL,Compare D channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0480360++0x03
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line.long 0x00 "CNT_G0_INPUT_SEL,Counter G0 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0480364++0x03
|
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line.long 0x00 "CNT_G1_INPUT_SEL,Counter G1 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0480368++0x03
|
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line.long 0x00 "EXT_OUTPUT_SEL,External output source select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF048036C++0x03
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line.long 0x00 "TRIGC_POL_INV,Event trigger polarity invert"
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bitfld.long 0x00 13. " EXT_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 12. " EXT_SET ,Polarity invert" "0,1"
|
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bitfld.long 0x00 11. " CNT_G1_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 10. " CNT_G1_SET ,Polarity invert" "0,1"
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textline " "
|
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bitfld.long 0x00 9. "CNT_G0_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 8. " CNT_G0_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 7. " CMP_D_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 6. " CMP_D_SET ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 5. "CMP_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 4. " CMP_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 3. " CMP_B_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 2. " CMP_B_SET ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 1. "CMP_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 0. " CMP_A_SET ,Polarity invert" "0,1"
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group ad:0xF0480374++0x03
|
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line.long 0x00 "CMP_SW_TRIG,Compare signal software trigger register"
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bitfld.long 0x00 7. " CMP_D_CLR ,Set high to generate CLR pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CMP_C_CLR ,Set high to generate CLR pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CMP_B_CLR ,Set high to generate CLR pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CMP_A_CLR ,Set high to generate CLR pulse signal for compare A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CMP_D_SET ,Set high to generate SET pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CMP_C_SET ,Set high to generate SET pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CMP_B_SET ,Set high to generate SET pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CMP_A_SET ,Set high to generate SET pulse signal for compare A channel. Auto clear after set." "0,1"
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group ad:0xF0480378++0x03
|
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line.long 0x00 "CNT_EXT_SW_TRIG,Counter and external signal software trigger register"
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bitfld.long 0x00 5. " EXT_CLR ,Set high to generate CLR pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " EXT_SET ,Set high to generate SET pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 3. " CNT_G1_CLR ,Set high to generate CLR pulse signal for CNT_G1. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CNT_G1_SET ,Set high to generate SET pulse signal for CNT_G1. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 1. "CNT_G0_CLR ,Set high to generate CLR pulse signal for CNT_G0. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CNT_G0_SET ,Set high to generate SET pulse signal for CNT_G0. Auto clear after set." "0,1"
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group ad:0xF0480380++0x03
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line.long 0x00 "SW_TRIG_CTRL,SW trigger event generation control"
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bitfld.long 0x00 15. " SW_TRIG3_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 14. " SW_TRIG3_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 13. " SW_TRIG3_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 12. " SW_TRIG3_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 11. "SW_TRIG2_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 10. " SW_TRIG2_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 9. " SW_TRIG2_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 8. " SW_TRIG2_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 7. "SW_TRIG1_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 6. " SW_TRIG1_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 5. " SW_TRIG1_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 4. " SW_TRIG1_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 3. "SW_TRIG0_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 2. " SW_TRIG0_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 1. " SW_TRIG0_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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group ad:0xF0480384++0x03
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line.long 0x00 "SW_TRIG_STATUS,SW trigger outputs status"
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bitfld.long 0x00 3. " SW_TRIG3 ,SW trigger output" "0,1"
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bitfld.long 0x00 2. " SW_TRIG2 ,SW trigger output" "0,1"
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bitfld.long 0x00 1. " SW_TRIG1 ,SW trigger output" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0 ,SW trigger output" "0,1"
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group ad:0xF0480388++0x03
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line.long 0x00 "SW_TRIG_PULSE0,SW trigger0 and trigger1 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG1_WIDTH ,Pulse width of SW trigger1"
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hexmask.long.word 0x00 0.--15. 1. " TRIG0_WIDTH ,Pulse width of SW trigger0"
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group ad:0xF048038C++0x03
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line.long 0x00 "SW_TRIG_PULSE1,SW trigger2 and trigger3 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG3_WIDTH ,Pulse width of SW trigger3"
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hexmask.long.word 0x00 0.--15. 1. " TRIG2_WIDTH ,Pulse width of SW trigger2"
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group ad:0xF0480410++0x03
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line.long 0x00 "FAULT0_FLT,Filter setting for fault0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF0480414++0x03
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line.long 0x00 "FAULT1_FLT,Filter setting for fault1 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF0480418++0x03
|
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line.long 0x00 "FAULT2_FLT,Filter setting for fault2 input."
|
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF048041C++0x03
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line.long 0x00 "FAULT3_FLT,Filter setting for fault3 input."
|
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF0480420++0x03
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line.long 0x00 "SYNC_DIS,Synchronization DIsable control register"
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bitfld.long 0x00 5. " FAULT3 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 4. " FAULT2 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 3. " FAULT1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 2. " FAULT0 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 1. "EXT_CLR ,DIsable synchronization" "0,1"
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bitfld.long 0x00 0. " EXT_SET ,DIsable synchronization" "0,1"
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group ad:0xF0480440++0x03
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line.long 0x00 "CMP_A_FAULT_EVENT_CTRL,Compare A channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF0480444++0x03
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line.long 0x00 "CMP_B_FAULT_EVENT_CTRL,Compare B channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF0480448++0x03
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line.long 0x00 "CMP_C_FAULT_EVENT_CTRL,Compare C channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF048044C++0x03
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line.long 0x00 "CMP_D_FAULT_EVENT_CTRL,Compare D channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF0480460++0x03
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line.long 0x00 "CMP_A_DTI_CTRL,Dead time insertion control register for compare A channel"
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
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textline " "
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
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group ad:0xF0480464++0x03
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line.long 0x00 "CMP_A_DTI_WID,Dead time insertion width register for compare A channel"
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF0480468++0x03
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line.long 0x00 "CMP_B_DTI_CTRL,Dead time insertion control register for compare B channel"
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
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textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
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group ad:0xF048046C++0x03
|
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line.long 0x00 "CMP_B_DTI_WID,Dead time insertion width register for compare B channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF0480470++0x03
|
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line.long 0x00 "CMP_C_DTI_CTRL,Dead time insertion control register for compare C channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
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textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
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group ad:0xF0480474++0x03
|
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line.long 0x00 "CMP_C_DTI_WID,Dead time insertion width register for compare C channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF0480478++0x03
|
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line.long 0x00 "CMP_D_DTI_CTRL,Dead time insertion control register for compare D channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
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group ad:0xF048047C++0x03
|
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line.long 0x00 "CMP_D_DTI_WID,Dead time insertion width register for compare D channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF0480500++0x03
|
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line.long 0x00 "SIGNAL_STATUS,Signal status register"
|
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bitfld.long 0x00 15. " CMP_D_CLR ,Compare D clear signal" "0,1"
|
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bitfld.long 0x00 14. " CMP_D_SET ,Compare D set signal" "0,1"
|
|
bitfld.long 0x00 13. " CMP_C_CLR ,Compare C clear signal" "0,1"
|
|
bitfld.long 0x00 12. " CMP_C_SET ,Compare C set signal" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 11. "CMP_B_CLR ,Compare B clear signal" "0,1"
|
|
bitfld.long 0x00 10. " CMP_B_SET ,Compare B set signal" "0,1"
|
|
bitfld.long 0x00 9. " CMP_A_CLR ,Compare A clear signal" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A_SET ,Compare A set signal" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 7. "CMP_D1 ,Compare D1 signal" "0,1"
|
|
bitfld.long 0x00 6. " CMP_D0 ,Compare D0 signal" "0,1"
|
|
bitfld.long 0x00 5. " CMP_C1 ,Compare C1 signal" "0,1"
|
|
bitfld.long 0x00 4. " CMP_C0 ,Compare C0 signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CMP_B1 ,Compare B1 signal" "0,1"
|
|
bitfld.long 0x00 2. " CMP_B0 ,Compare B0 signal" "0,1"
|
|
bitfld.long 0x00 1. " CMP_A1 ,Compare A1 signal" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A0 ,Compare A0 signal" "0,1"
|
|
group ad:0xF0480FFC++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
tree.end
|
|
tree "EPWM2"
|
|
width 28.
|
|
group ad:0xF0490000++0x03
|
|
line.long 0x00 "INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,CNT_G1 overflow" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,CNT_G0 overflow" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Compare D event happens" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Compare C event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Compare B event happens" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Compare A event happens" "0,1"
|
|
group ad:0xF0490004++0x03
|
|
line.long 0x00 "INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Status enable" "0,1"
|
|
group ad:0xF0490008++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Singal enable" "0,1"
|
|
group ad:0xF049000C++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA,Correctable error interrupt status register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF0490010++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA_EN,Correctable error interrupt status enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF0490014++0x03
|
|
line.long 0x00 "COR_ERR_INT_SIG_EN,Correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF0490018++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA,Uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF049001C++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF0490020++0x03
|
|
line.long 0x00 "UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF0490024++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata corrctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0490028++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF049002C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0490030++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Cock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Cock monitor compare0 erro" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error." "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error." "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error." "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0490034++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0490038++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,CONFIG_DMA eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF049003C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_1,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF0490040++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN_1,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF0490044++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN_1,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,CONFIG_DMA eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF049004C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF0490050++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF0490054++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF049005C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF0490060++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,RAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF0490064++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0490068++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,RAM rdata SECDED monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF049006C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,RAM rdata ECC SECDED monitor error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF0490070++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF0490074++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF0490080++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 16.--18. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0490084++0x03
|
|
line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0490088++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF049008C++0x03
|
|
line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0490090++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 6. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
|
bitfld.long 0x00 5. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
|
bitfld.long 0x00 4. " CNT_OVF ,Counter overflow and snapshot interrupt error injection." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Channel D interrupt error injection." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CHN_C ,Channel C interrupt error injection." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B ,Channel B interrupt error injection." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Channel A interrupt error injection." "0,1"
|
|
group ad:0xF0490094++0x03
|
|
line.long 0x00 "CLK_MON_CMP_ERR_INJ,Clock monitor compare error injection r"
|
|
bitfld.long 0x00 2.--3. " ERR1 ,Clock monitor 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ERR0 ,Clock monitor 0" "0,1,2,3"
|
|
group ad:0xF04900A0++0x03
|
|
line.long 0x00 "CLK_CONFIG,EPMW clock select and DIvider configuration."
|
|
bitfld.long 0x00 31. " CLK_CHANGE_UPD ,Set this bit to make new DIV_NUM value effective. Will be auto cleared after new DIV_NUM is effective" "0,1"
|
|
bitfld.long 0x00 16.--17. " SRC_CLK_SEL ,Clock source select. 00: High frequency(HF) clock, update to 400mhz. 01: Alternative High frequency(AHF) clock, update to 400mhz. 10: External clock. 11: Low power(LP) clock, typically from low speed on chip RCOSC." "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV_NUM ,DIvider number for timer clock."
|
|
group ad:0xF04900A4++0x03
|
|
line.long 0x00 "CLK_MON_EN,Clock monitor enable register"
|
|
bitfld.long 0x00 2. " CMP_SET ,When enable or DIsable clock monitor, set this bit together. This bit is used to inDIcate configuration is completed." "0,1"
|
|
bitfld.long 0x00 1. " EN_N ,Active low.Enable clock monitor1" "0,1"
|
|
bitfld.long 0x00 0. " EN_P ,Active high.Enable clock monitor0" "0,1"
|
|
group ad:0xF04900A8++0x03
|
|
line.long 0x00 "SW_RST,Software reset"
|
|
bitfld.long 0x00 9. " CNT_G1 ,Reset CNT_G1.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 8. " CNT_G0 ,Reset CNT_G0.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 7. " FIFO_D ,Reset FIFO D relative logic. Will be auto cleared after reset complete" "0,1"
|
|
bitfld.long 0x00 6. " FIFO_C ,Reset FIFO C relative logic. Will be auto cleared after reset complete" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "FIFO_B ,Reset FIFO B relative logic. Will be auto cleared after reset complete" "0,1"
|
|
bitfld.long 0x00 4. " FIFO_A ,Reset FIFO A relative logic. Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Reset CMP_D. Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Reset CMP_C.Will be auto cleared after reset complete." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Reset CMP_B.Will be auto cleared after reset complete." "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Reset CMP_A.Will be auto cleared after reset complete." "0,1"
|
|
group ad:0xF04900B0++0x03
|
|
line.long 0x00 "CHN_DMA_CTRL,DMA control register"
|
|
bitfld.long 0x00 30. " TWO_CHN_BD_MODE ,When this bit is enable, CMP_B and CMP_D block are sharing DMA_B and FIFO_B. RAM_B and RAM_D are combined are worked with FIFO_B. If four_chn_mode is enable, this bit is ignored." "0,1"
|
|
bitfld.long 0x00 29. " TWO_CHN_AC_MODE ,When this bit is enable, CMP_A and CMP_C block are sharing DMA_A and FIFO_A. RAM_A and RAM_C are combined are worked with FIFO_A. If four_chn_mode is enable, this bit is ignored." "0,1"
|
|
bitfld.long 0x00 28. " FOUR_CHN_MODE ,When this bit is enable, 4 compare blocks are sharing DMA_A and FIFO_A. RAM_A, RAM_B,RAM_C and RAM_D are combined are worked with FIFO_A." "0,1"
|
|
bitfld.long 0x00 26.--27. " CMP_D_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
|
|
textline " "
|
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bitfld.long 0x00 24.--25. "CMP_C_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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bitfld.long 0x00 22.--23. " CMP_B_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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bitfld.long 0x00 20.--21. " CMP_A_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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bitfld.long 0x00 19. " CMP_D_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 18. "CMP_C_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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bitfld.long 0x00 17. " CMP_B_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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bitfld.long 0x00 16. " CMP_A_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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bitfld.long 0x00 14.--15. " CMP_D_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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|
textline " "
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bitfld.long 0x00 12.--13. "CMP_C_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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bitfld.long 0x00 10.--11. " CMP_B_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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bitfld.long 0x00 8.--9. " CMP_A_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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bitfld.long 0x00 7. " CHN_D_SIG_MASK ,Mask channel D dma request hardware output" "0,1"
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|
textline " "
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bitfld.long 0x00 6. "CHN_C_SIG_MASK ,Mask channel C dma request hardware output" "0,1"
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bitfld.long 0x00 5. " CHN_B_SIG_MASK ,Mask channel B dma request hardware output" "0,1"
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bitfld.long 0x00 4. " CHN_A_SIG_MASK ,Mask channel A dma request hardware output" "0,1"
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bitfld.long 0x00 3. " CHN_D_EN ,Enable dma request for COMPARE D channel accorDIng to channel D FIFO WML." "0,1"
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textline " "
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bitfld.long 0x00 2. "CHN_C_EN ,Enable dma request for COMPARE C channel accorDIng to channel C FIFO WML." "0,1"
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bitfld.long 0x00 1. " CHN_B_EN ,Enable dma request for COMPARE B channel accorDIng to channel B FIFO WML." "0,1"
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bitfld.long 0x00 0. " CHN_A_EN ,Enable dma request for COMPARE A channel accorDIng to channle A FIFO WML." "0,1"
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group ad:0xF04900B4++0x03
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line.long 0x00 "DMA_WML,DMA watermark leverl register"
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bitfld.long 0x00 24.--27. " CHN_D ,Waterwark level setting for channel D DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CHN_C ,Waterwark level setting for channel C DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--12. " CHN_B ,Waterwark level setting for channel B DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 0.--5. 1. " CHN_A ,Waterwark level setting for channel A DMA"
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group ad:0xF04900B8++0x03
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line.long 0x00 "CONFIG_DMA_CTL,Configuration dma control register"
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hexmask.long.byte 0x00 2.--7. 1. " TRIG_SEL ,Select source to trigger dma request. 1. CMP_A_CE 2. CMP_B_CE 3. CMP_C_CE 4. CMP_D_CE 5. CNT_G0_CE 6. CNT_G1_CE"
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bitfld.long 0x00 1. " SIG_MASK ,Mask configuration dma request hardware output" "0,1"
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bitfld.long 0x00 0. " EN ,DMA enable for register configuration" "0,1"
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group ad:0xF04900BC++0x03
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line.long 0x00 "FIFO_REQ_STATUS,FIFO request status"
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bitfld.long 0x00 3. " FIFO_D ,FIFO D reach water mark level" "0,1"
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bitfld.long 0x00 2. " FIFO_C ,FIFO C reach water mark level" "0,1"
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bitfld.long 0x00 1. " FIFO_B ,FIFO B reach water mark level" "0,1"
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bitfld.long 0x00 0. " FIFO_A ,FIFO A reach water mark level" "0,1"
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group ad:0xF04900C0++0x03
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line.long 0x00 "FIFO_A,FIFO_entry for compare channel A"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04900C4++0x03
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line.long 0x00 "FIFO_B,FIFO_entry for compare channel B"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04900C8++0x03
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line.long 0x00 "FIFO_C,FIFO_entry for compare channel C"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04900CC++0x03
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line.long 0x00 "FIFO_D,FIFO_entry for compare channel D"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04900D0++0x03
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line.long 0x00 "FIFO_STA0,FIFO status0 register."
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bitfld.long 0x00 24. " FIFO_ERR_B ,InDIcate FIFO underrun or overrun." "0,1"
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hexmask.long.byte 0x00 18.--23. 1. " FIFO_ENTRIES_B ,InDIcate FIFO data number"
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bitfld.long 0x00 17. " FIFO_EMPTY_B ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 16. " FIFO_FULL_B ,InDIcate FIFO is full." "0,1"
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textline " "
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bitfld.long 0x00 9. "FIFO_ERR_A ,InDIcate FIFO underrun or overrun." "0,1"
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hexmask.long.byte 0x00 2.--8. 1. " FIFO_ENTRIES_A ,InDIcate FIFO data number"
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bitfld.long 0x00 1. " FIFO_EMPTY_A ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 0. " FIFO_FULL_A ,InDIcate FIFO is full." "0,1"
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group ad:0xF04900D4++0x03
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line.long 0x00 "FIFO_STA1,FIFO status1 register."
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bitfld.long 0x00 23. " FIFO_ERR_D ,InDIcate FIFO underrun or overrun." "0,1"
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bitfld.long 0x00 18.--22. " FIFO_ENTRIES_D ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 17. " FIFO_EMPTY_D ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 16. " FIFO_FULL_D ,InDIcate FIFO is full." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FIFO_ERR_C ,InDIcate FIFO underrun or overrun." "0,1"
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bitfld.long 0x00 2.--6. " FIFO_ENTRIES_C ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 1. " FIFO_EMPTY_C ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 0. " FIFO_FULL_C ,InDIcate FIFO is full." "0,1"
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group ad:0xF0490100++0x03
|
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line.long 0x00 "CNT_G0_INIT,Counter G0 initial value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF0490104++0x03
|
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line.long 0x00 "CNT_G0_OVF,Counter G0 overflow value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF0490108++0x03
|
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line.long 0x00 "CNT_G0_CFG,CNT_G0 configuration register."
|
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bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset coun" "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
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bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
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textline " "
|
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF049010C++0x03
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line.long 0x00 "CNT_G0_EN,CNT_G0 enable register"
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
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group ad:0xF0490110++0x03
|
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line.long 0x00 "CNT_G0,CNT_G0 TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
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group ad:0xF0490114++0x03
|
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line.long 0x00 "CNT_G0_MFC,cnt_g0 Modulation Frequency Control"
|
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bitfld.long 0x00 0.--3. " MFC_UP ,ncreasing modulation frequency up to 2^N times, where N ranged in between [0,10]. 0 means MFC DIsable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0490120++0x03
|
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line.long 0x00 "CNT_G1_INIT,Counter G1 initial value registe"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF0490124++0x03
|
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line.long 0x00 "CNT_G1_OVF,Counter G1 overflow value registe"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF0490128++0x03
|
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line.long 0x00 "CNT_G1_CFG,CNT_G1 configuration register."
|
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bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset coun" "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW" "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
|
textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
|
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF049012C++0x03
|
|
line.long 0x00 "CNT_G1_EN,CNT_G1 enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
|
group ad:0xF0490130++0x03
|
|
line.long 0x00 "CNT_G1,CNT_G1 TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF0490134++0x03
|
|
line.long 0x00 "CNT_G1_MFC,CNT_G1 Modulation Frequency Control"
|
|
bitfld.long 0x00 0.--3. " MFC_UP ,ncreasing modulation frequency up to 2^N times, where N ranged in between [0,10]. 0 means MFC DIsable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0490220++0x03
|
|
line.long 0x00 "CMP_A_CONFIG,Compare A channel configuration register"
|
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
|
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
|
bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
|
|
bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
|
|
bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
|
group ad:0xF0490224++0x03
|
|
line.long 0x00 "CMP_A_EVENT_OUT_MODE,Compare A channel event output mode register"
|
|
bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp1 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0490228++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID0,Compare A channel output pulse width register0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
|
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
|
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
|
|
group ad:0xF049022C++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID1,Compare A channel output pulse width register1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
|
|
group ad:0xF0490230++0x03
|
|
line.long 0x00 "CMP_A_00_VAL,Compare value for compare A channel cmp00 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF0490234++0x03
|
|
line.long 0x00 "CMP_A_01_VAL,Compare value for compare A channel cmp01 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF0490238++0x03
|
|
line.long 0x00 "CMP_A_10_VAL,Compare value for compare A channel cmp10 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF049023C++0x03
|
|
line.long 0x00 "CMP_A_11_VAL,Compare value for compare A channel cmp11 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF0490240++0x03
|
|
line.long 0x00 "CMP_A_DITHER,Compare A channel DIther register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
|
|
group ad:0xF0490244++0x03
|
|
line.long 0x00 "CMP_A_OFFSET,Compare A offset value register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
|
group ad:0xF049024C++0x03
|
|
line.long 0x00 "CMP_A_EID,Compare A channel event ID register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,CMP11 event ID"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,CMP10 event ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,CMP01 event ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,CMP00 event ID"
|
|
group ad:0xF0490250++0x03
|
|
line.long 0x00 "CMP_B_CONFIG,Compare B channel configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
|
|
bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
|
bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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|
textline " "
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF0490254++0x03
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line.long 0x00 "CMP_B_EVENT_OUT_MODE,Compare B channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF0490258++0x03
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line.long 0x00 "CMP_B_PULSE_WID0,Compare B channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF049025C++0x03
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line.long 0x00 "CMP_B_PULSE_WID1,Compare B channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF0490260++0x03
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line.long 0x00 "CMP_B_00_VAL,Compare value for compare B channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0490264++0x03
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line.long 0x00 "CMP_B_01_VAL,Compare value for compare B channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0490268++0x03
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line.long 0x00 "CMP_B_10_VAL,Compare value for compare B channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF049026C++0x03
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line.long 0x00 "CMP_B_11_VAL,Compare value for compare B channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0490270++0x03
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line.long 0x00 "CMP_B_DITHER,Compare B channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF0490274++0x03
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line.long 0x00 "CMP_B_OFFSET,Compare B offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF0490280++0x03
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line.long 0x00 "CMP_C_CONFIG,Compare C channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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textline " "
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bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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textline " "
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF0490284++0x03
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line.long 0x00 "CMP_C_EVENT_OUT_MODE,Compare C channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF0490288++0x03
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line.long 0x00 "CMP_C_PULSE_WID0,Compare C channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF049028C++0x03
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line.long 0x00 "CMP_C_PULSE_WID1,Compare C channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF0490290++0x03
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line.long 0x00 "CMP_C_00_VAL,Compare value for compare C channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0490294++0x03
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line.long 0x00 "CMP_C_01_VAL,Compare value for compare C channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF0490298++0x03
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line.long 0x00 "CMP_C_10_VAL,Compare value for compare C channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF049029C++0x03
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line.long 0x00 "CMP_C_11_VAL,Compare value for compare C channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04902A0++0x03
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line.long 0x00 "CMP_C_DITHER,Compare C channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04902A4++0x03
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line.long 0x00 "CMP_C_OFFSET,Compare C offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04902B0++0x03
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line.long 0x00 "CMP_D_CONFIG,Compare D channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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textline " "
|
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF04902B4++0x03
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line.long 0x00 "CMP_D_EVENT_OUT_MODE,Compare D channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04902B8++0x03
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line.long 0x00 "CMP_D_PULSE_WID0,Compare D channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04902BC++0x03
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line.long 0x00 "CMP_D_PULSE_WID1,Compare D channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04902C0++0x03
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line.long 0x00 "CMP_D_00_VAL,Compare value for compare D channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04902C4++0x03
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line.long 0x00 "CMP_D_01_VAL,Compare value for compare D channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04902C8++0x03
|
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line.long 0x00 "CMP_D_10_VAL,Compare value for compare D channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04902CC++0x03
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line.long 0x00 "CMP_D_11_VAL,Compare value for compare D channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04902D0++0x03
|
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line.long 0x00 "CMP_D_DITHER,Compare D channel DIther register"
|
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04902D4++0x03
|
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line.long 0x00 "CMP_D_OFFSET,Compare D offset value register"
|
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04902E0++0x03
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line.long 0x00 "CMP_CTRL,Compare control register"
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bitfld.long 0x00 28. " CMP_A_EID_UPD ,Update EID value. Will be auto clear after completing update EID value." "0,1"
|
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bitfld.long 0x00 27. " CMP_D1_INIT_UPD ,Update cmp_d1 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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bitfld.long 0x00 26. " CMP_D0_INIT_UPD ,Update cmp_d0 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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bitfld.long 0x00 25. " CMP_C1_INIT_UPD ,Update cmp_c1 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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textline " "
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bitfld.long 0x00 24. "CMP_C0_INIT_UPD ,Update cmp_c0 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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bitfld.long 0x00 23. " CMP_B1_INIT_UPD ,Update cmp_b1 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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bitfld.long 0x00 22. " CMP_B0_INIT_UPD ,Update cmp_b0 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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bitfld.long 0x00 21. " CMP_A1_INIT_UPD ,Update cmp_a1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 20. "CMP_A0_INIT_UPD ,Update cmp_a0 output initial value. Will be auto clear after completing update initial value." "0,1"
|
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bitfld.long 0x00 19. " CMP_D1_INIT_STATUS ,cmp_d1 output initial status" "0,1"
|
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bitfld.long 0x00 18. " CMP_D0_INIT_STATUS ,cmp_d0 output initial status" "0,1"
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bitfld.long 0x00 17. " CMP_C1_INIT_STATUS ,cmp_c1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 16. "CMP_C0_INIT_STATUS ,cmp_c0 output initial status" "0,1"
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bitfld.long 0x00 15. " CMP_B1_INIT_STATUS ,cmp_b1 output initial status" "0,1"
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bitfld.long 0x00 14. " CMP_B0_INIT_STATUS ,cmp_b0 output initial status" "0,1"
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bitfld.long 0x00 13. " CMP_A1_INIT_STATUS ,cmp_a1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 12. "CMP_A0_INIT_STATUS ,cmp_a0 output initial status" "0,1"
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bitfld.long 0x00 11. " CMP_D_VAL_UPD ,Update all the compare value registers for compare D channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
|
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bitfld.long 0x00 10. " CMP_C_VAL_UPD ,Update all the compare value registers for compare C channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
|
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bitfld.long 0x00 9. " CMP_B_VAL_UPD ,Update all the compare value registers for compare B channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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textline " "
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bitfld.long 0x00 8. "CMP_A_VAL_UPD ,Update all the compare value registers for compare A channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 7. " CMP_D_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CMP_C_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 5. " CMP_B_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour.." "0,1"
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textline " "
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bitfld.long 0x00 4. "CMP_A_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 3. " CMP_D_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 2. " CMP_C_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 1. " CMP_B_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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textline " "
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bitfld.long 0x00 0. "CMP_A_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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group ad:0xF0490320++0x03
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line.long 0x00 "CMP_A_SSE_CTRL,Synthesis CMP_A0,CMP_B0,CMP_C0 and CMP_D0 outputs and CMP_A1 signals into one signal for compare channel A"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_A_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF0490324++0x03
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line.long 0x00 "CMP_A_SSE_REG,Signal synthesis for compare A output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF0490328++0x03
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line.long 0x00 "CMP_B_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_B1 signals into one signal for compare channel B"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_B_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF049032C++0x03
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line.long 0x00 "CMP_B_SSE_REG,Signal synthesis for compare B output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF0490330++0x03
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line.long 0x00 "CMP_C_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_C1 signals into one signal for compare channel C"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_C_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF0490334++0x03
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line.long 0x00 "CMP_C_SSE_REG,Signal synthesis for compare C output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF0490338++0x03
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line.long 0x00 "CMP_D_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_D1 signals into one signal for compare channel D"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_D_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF049033C++0x03
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line.long 0x00 "CMP_D_SSE_REG,Signal synthesis for compare D output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF0490350++0x03
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line.long 0x00 "CMP_A_INPUT_SEL,Compare A channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0490354++0x03
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line.long 0x00 "CMP_B_INPUT_SEL,Compare B channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0490358++0x03
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line.long 0x00 "CMP_C_INPUT_SEL,Compare C channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF049035C++0x03
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line.long 0x00 "CMP_D_INPUT_SEL,Compare D channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0490360++0x03
|
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line.long 0x00 "CNT_G0_INPUT_SEL,Counter G0 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0490364++0x03
|
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line.long 0x00 "CNT_G1_INPUT_SEL,Counter G1 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0490368++0x03
|
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line.long 0x00 "EXT_OUTPUT_SEL,External output source select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF049036C++0x03
|
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line.long 0x00 "TRIGC_POL_INV,Event trigger polarity invert"
|
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bitfld.long 0x00 13. " EXT_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 12. " EXT_SET ,Polarity invert" "0,1"
|
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bitfld.long 0x00 11. " CNT_G1_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 10. " CNT_G1_SET ,Polarity invert" "0,1"
|
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textline " "
|
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bitfld.long 0x00 9. "CNT_G0_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 8. " CNT_G0_SET ,Polarity invert" "0,1"
|
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bitfld.long 0x00 7. " CMP_D_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 6. " CMP_D_SET ,Polarity invert" "0,1"
|
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textline " "
|
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bitfld.long 0x00 5. "CMP_C_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 4. " CMP_C_SET ,Polarity invert" "0,1"
|
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bitfld.long 0x00 3. " CMP_B_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 2. " CMP_B_SET ,Polarity invert" "0,1"
|
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textline " "
|
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bitfld.long 0x00 1. "CMP_A_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 0. " CMP_A_SET ,Polarity invert" "0,1"
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group ad:0xF0490374++0x03
|
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line.long 0x00 "CMP_SW_TRIG,Compare signal software trigger register"
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bitfld.long 0x00 7. " CMP_D_CLR ,Set high to generate CLR pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CMP_C_CLR ,Set high to generate CLR pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CMP_B_CLR ,Set high to generate CLR pulse signal for compare B channel. Auto clear after set." "0,1"
|
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bitfld.long 0x00 4. " CMP_A_CLR ,Set high to generate CLR pulse signal for compare A channel. Auto clear after set." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "CMP_D_SET ,Set high to generate SET pulse signal for compare D channel. Auto clear after set." "0,1"
|
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bitfld.long 0x00 2. " CMP_C_SET ,Set high to generate SET pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CMP_B_SET ,Set high to generate SET pulse signal for compare B channel. Auto clear after set." "0,1"
|
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bitfld.long 0x00 0. " CMP_A_SET ,Set high to generate SET pulse signal for compare A channel. Auto clear after set." "0,1"
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group ad:0xF0490378++0x03
|
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line.long 0x00 "CNT_EXT_SW_TRIG,Counter and external signal software trigger register"
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bitfld.long 0x00 5. " EXT_CLR ,Set high to generate CLR pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " EXT_SET ,Set high to generate SET pulse signal for external output. Auto clear after set." "0,1"
|
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bitfld.long 0x00 3. " CNT_G1_CLR ,Set high to generate CLR pulse signal for CNT_G1. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CNT_G1_SET ,Set high to generate SET pulse signal for CNT_G1. Auto clear after set." "0,1"
|
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textline " "
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bitfld.long 0x00 1. "CNT_G0_CLR ,Set high to generate CLR pulse signal for CNT_G0. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CNT_G0_SET ,Set high to generate SET pulse signal for CNT_G0. Auto clear after set." "0,1"
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group ad:0xF0490380++0x03
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line.long 0x00 "SW_TRIG_CTRL,SW trigger event generation control"
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bitfld.long 0x00 15. " SW_TRIG3_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 14. " SW_TRIG3_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 13. " SW_TRIG3_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 12. " SW_TRIG3_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 11. "SW_TRIG2_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 10. " SW_TRIG2_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 9. " SW_TRIG2_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 8. " SW_TRIG2_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 7. "SW_TRIG1_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 6. " SW_TRIG1_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 5. " SW_TRIG1_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 4. " SW_TRIG1_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 3. "SW_TRIG0_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 2. " SW_TRIG0_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 1. " SW_TRIG0_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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group ad:0xF0490384++0x03
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line.long 0x00 "SW_TRIG_STATUS,SW trigger outputs status"
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bitfld.long 0x00 3. " SW_TRIG3 ,SW trigger output" "0,1"
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bitfld.long 0x00 2. " SW_TRIG2 ,SW trigger output" "0,1"
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bitfld.long 0x00 1. " SW_TRIG1 ,SW trigger output" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0 ,SW trigger output" "0,1"
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group ad:0xF0490388++0x03
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line.long 0x00 "SW_TRIG_PULSE0,SW trigger0 and trigger1 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG1_WIDTH ,Pulse width of SW trigger1"
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hexmask.long.word 0x00 0.--15. 1. " TRIG0_WIDTH ,Pulse width of SW trigger0"
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group ad:0xF049038C++0x03
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line.long 0x00 "SW_TRIG_PULSE1,SW trigger2 and trigger3 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG3_WIDTH ,Pulse width of SW trigger3"
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hexmask.long.word 0x00 0.--15. 1. " TRIG2_WIDTH ,Pulse width of SW trigger2"
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group ad:0xF0490410++0x03
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line.long 0x00 "FAULT0_FLT,Filter setting for fault0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF0490414++0x03
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line.long 0x00 "FAULT1_FLT,Filter setting for fault1 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF0490418++0x03
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line.long 0x00 "FAULT2_FLT,Filter setting for fault2 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF049041C++0x03
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line.long 0x00 "FAULT3_FLT,Filter setting for fault3 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF0490420++0x03
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line.long 0x00 "SYNC_DIS,Synchronization DIsable control register"
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bitfld.long 0x00 5. " FAULT3 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 4. " FAULT2 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 3. " FAULT1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 2. " FAULT0 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 1. "EXT_CLR ,DIsable synchronization" "0,1"
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bitfld.long 0x00 0. " EXT_SET ,DIsable synchronization" "0,1"
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group ad:0xF0490440++0x03
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line.long 0x00 "CMP_A_FAULT_EVENT_CTRL,Compare A channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF0490444++0x03
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line.long 0x00 "CMP_B_FAULT_EVENT_CTRL,Compare B channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF0490448++0x03
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line.long 0x00 "CMP_C_FAULT_EVENT_CTRL,Compare C channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF049044C++0x03
|
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line.long 0x00 "CMP_D_FAULT_EVENT_CTRL,Compare D channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
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group ad:0xF0490460++0x03
|
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line.long 0x00 "CMP_A_DTI_CTRL,Dead time insertion control register for compare A channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
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textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
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group ad:0xF0490464++0x03
|
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line.long 0x00 "CMP_A_DTI_WID,Dead time insertion width register for compare A channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF0490468++0x03
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line.long 0x00 "CMP_B_DTI_CTRL,Dead time insertion control register for compare B channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
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textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
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group ad:0xF049046C++0x03
|
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line.long 0x00 "CMP_B_DTI_WID,Dead time insertion width register for compare B channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF0490470++0x03
|
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line.long 0x00 "CMP_C_DTI_CTRL,Dead time insertion control register for compare C channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
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textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
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group ad:0xF0490474++0x03
|
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line.long 0x00 "CMP_C_DTI_WID,Dead time insertion width register for compare C channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF0490478++0x03
|
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line.long 0x00 "CMP_D_DTI_CTRL,Dead time insertion control register for compare D channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF049047C++0x03
|
|
line.long 0x00 "CMP_D_DTI_WID,Dead time insertion width register for compare D channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF0490500++0x03
|
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line.long 0x00 "SIGNAL_STATUS,Signal status register"
|
|
bitfld.long 0x00 15. " CMP_D_CLR ,Compare D clear signal" "0,1"
|
|
bitfld.long 0x00 14. " CMP_D_SET ,Compare D set signal" "0,1"
|
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bitfld.long 0x00 13. " CMP_C_CLR ,Compare C clear signal" "0,1"
|
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bitfld.long 0x00 12. " CMP_C_SET ,Compare C set signal" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 11. "CMP_B_CLR ,Compare B clear signal" "0,1"
|
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bitfld.long 0x00 10. " CMP_B_SET ,Compare B set signal" "0,1"
|
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bitfld.long 0x00 9. " CMP_A_CLR ,Compare A clear signal" "0,1"
|
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bitfld.long 0x00 8. " CMP_A_SET ,Compare A set signal" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 7. "CMP_D1 ,Compare D1 signal" "0,1"
|
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bitfld.long 0x00 6. " CMP_D0 ,Compare D0 signal" "0,1"
|
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bitfld.long 0x00 5. " CMP_C1 ,Compare C1 signal" "0,1"
|
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bitfld.long 0x00 4. " CMP_C0 ,Compare C0 signal" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 3. "CMP_B1 ,Compare B1 signal" "0,1"
|
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bitfld.long 0x00 2. " CMP_B0 ,Compare B0 signal" "0,1"
|
|
bitfld.long 0x00 1. " CMP_A1 ,Compare A1 signal" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A0 ,Compare A0 signal" "0,1"
|
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group ad:0xF0490FFC++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
tree.end
|
|
tree "EPWM3"
|
|
width 28.
|
|
group ad:0xF04A0000++0x03
|
|
line.long 0x00 "INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,CNT_G1 overflow" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,CNT_G0 overflow" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Compare D event happens" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Compare C event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Compare B event happens" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Compare A event happens" "0,1"
|
|
group ad:0xF04A0004++0x03
|
|
line.long 0x00 "INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Status enable" "0,1"
|
|
group ad:0xF04A0008++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Singal enable" "0,1"
|
|
group ad:0xF04A000C++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA,Correctable error interrupt status register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04A0010++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA_EN,Correctable error interrupt status enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04A0014++0x03
|
|
line.long 0x00 "COR_ERR_INT_SIG_EN,Correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04A0018++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA,Uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04A001C++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04A0020++0x03
|
|
line.long 0x00 "UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04A0024++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata corrctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04A0028++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04A002C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04A0030++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Cock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Cock monitor compare0 erro" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error." "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error." "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error." "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04A0034++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04A0038++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,CONFIG_DMA eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04A003C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_1,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04A0040++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN_1,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04A0044++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN_1,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,CONFIG_DMA eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04A004C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF04A0050++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF04A0054++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF04A005C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF04A0060++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,RAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04A0064++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04A0068++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,RAM rdata SECDED monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04A006C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,RAM rdata ECC SECDED monitor error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04A0070++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF04A0074++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF04A0080++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 16.--18. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF04A0084++0x03
|
|
line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04A0088++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04A008C++0x03
|
|
line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04A0090++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 6. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
|
bitfld.long 0x00 5. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
|
bitfld.long 0x00 4. " CNT_OVF ,Counter overflow and snapshot interrupt error injection." "0,1"
|
|
bitfld.long 0x00 3. " CHN_D ,Channel D interrupt error injection." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CHN_C ,Channel C interrupt error injection." "0,1"
|
|
bitfld.long 0x00 1. " CHN_B ,Channel B interrupt error injection." "0,1"
|
|
bitfld.long 0x00 0. " CHN_A ,Channel A interrupt error injection." "0,1"
|
|
group ad:0xF04A0094++0x03
|
|
line.long 0x00 "CLK_MON_CMP_ERR_INJ,Clock monitor compare error injection r"
|
|
bitfld.long 0x00 2.--3. " ERR1 ,Clock monitor 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ERR0 ,Clock monitor 0" "0,1,2,3"
|
|
group ad:0xF04A00A0++0x03
|
|
line.long 0x00 "CLK_CONFIG,EPMW clock select and DIvider configuration."
|
|
bitfld.long 0x00 31. " CLK_CHANGE_UPD ,Set this bit to make new DIV_NUM value effective. Will be auto cleared after new DIV_NUM is effective" "0,1"
|
|
bitfld.long 0x00 16.--17. " SRC_CLK_SEL ,Clock source select. 00: High frequency(HF) clock, update to 400mhz. 01: Alternative High frequency(AHF) clock, update to 400mhz. 10: External clock. 11: Low power(LP) clock, typically from low speed on chip RCOSC." "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. " DIV_NUM ,DIvider number for timer clock."
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group ad:0xF04A00A4++0x03
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line.long 0x00 "CLK_MON_EN,Clock monitor enable register"
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bitfld.long 0x00 2. " CMP_SET ,When enable or DIsable clock monitor, set this bit together. This bit is used to inDIcate configuration is completed." "0,1"
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bitfld.long 0x00 1. " EN_N ,Active low.Enable clock monitor1" "0,1"
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bitfld.long 0x00 0. " EN_P ,Active high.Enable clock monitor0" "0,1"
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group ad:0xF04A00A8++0x03
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line.long 0x00 "SW_RST,Software reset"
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bitfld.long 0x00 9. " CNT_G1 ,Reset CNT_G1.Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 8. " CNT_G0 ,Reset CNT_G0.Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 7. " FIFO_D ,Reset FIFO D relative logic. Will be auto cleared after reset complete" "0,1"
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bitfld.long 0x00 6. " FIFO_C ,Reset FIFO C relative logic. Will be auto cleared after reset complete" "0,1"
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textline " "
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bitfld.long 0x00 5. "FIFO_B ,Reset FIFO B relative logic. Will be auto cleared after reset complete" "0,1"
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bitfld.long 0x00 4. " FIFO_A ,Reset FIFO A relative logic. Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 3. " CMP_D ,Reset CMP_D. Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 2. " CMP_C ,Reset CMP_C.Will be auto cleared after reset complete." "0,1"
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textline " "
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bitfld.long 0x00 1. "CMP_B ,Reset CMP_B.Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 0. " CMP_A ,Reset CMP_A.Will be auto cleared after reset complete." "0,1"
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group ad:0xF04A00B0++0x03
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line.long 0x00 "CHN_DMA_CTRL,DMA control register"
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bitfld.long 0x00 30. " TWO_CHN_BD_MODE ,When this bit is enable, CMP_B and CMP_D block are sharing DMA_B and FIFO_B. RAM_B and RAM_D are combined are worked with FIFO_B. If four_chn_mode is enable, this bit is ignored." "0,1"
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bitfld.long 0x00 29. " TWO_CHN_AC_MODE ,When this bit is enable, CMP_A and CMP_C block are sharing DMA_A and FIFO_A. RAM_A and RAM_C are combined are worked with FIFO_A. If four_chn_mode is enable, this bit is ignored." "0,1"
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bitfld.long 0x00 28. " FOUR_CHN_MODE ,When this bit is enable, 4 compare blocks are sharing DMA_A and FIFO_A. RAM_A, RAM_B,RAM_C and RAM_D are combined are worked with FIFO_A." "0,1"
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bitfld.long 0x00 26.--27. " CMP_D_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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textline " "
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bitfld.long 0x00 24.--25. "CMP_C_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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bitfld.long 0x00 22.--23. " CMP_B_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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bitfld.long 0x00 20.--21. " CMP_A_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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bitfld.long 0x00 19. " CMP_D_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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textline " "
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bitfld.long 0x00 18. "CMP_C_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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bitfld.long 0x00 17. " CMP_B_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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bitfld.long 0x00 16. " CMP_A_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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bitfld.long 0x00 14.--15. " CMP_D_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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textline " "
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bitfld.long 0x00 12.--13. "CMP_C_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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bitfld.long 0x00 10.--11. " CMP_B_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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bitfld.long 0x00 8.--9. " CMP_A_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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bitfld.long 0x00 7. " CHN_D_SIG_MASK ,Mask channel D dma request hardware output" "0,1"
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textline " "
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bitfld.long 0x00 6. "CHN_C_SIG_MASK ,Mask channel C dma request hardware output" "0,1"
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bitfld.long 0x00 5. " CHN_B_SIG_MASK ,Mask channel B dma request hardware output" "0,1"
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bitfld.long 0x00 4. " CHN_A_SIG_MASK ,Mask channel A dma request hardware output" "0,1"
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bitfld.long 0x00 3. " CHN_D_EN ,Enable dma request for COMPARE D channel accorDIng to channel D FIFO WML." "0,1"
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textline " "
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bitfld.long 0x00 2. "CHN_C_EN ,Enable dma request for COMPARE C channel accorDIng to channel C FIFO WML." "0,1"
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bitfld.long 0x00 1. " CHN_B_EN ,Enable dma request for COMPARE B channel accorDIng to channel B FIFO WML." "0,1"
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bitfld.long 0x00 0. " CHN_A_EN ,Enable dma request for COMPARE A channel accorDIng to channle A FIFO WML." "0,1"
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group ad:0xF04A00B4++0x03
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line.long 0x00 "DMA_WML,DMA watermark leverl register"
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bitfld.long 0x00 24.--27. " CHN_D ,Waterwark level setting for channel D DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CHN_C ,Waterwark level setting for channel C DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--12. " CHN_B ,Waterwark level setting for channel B DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 0.--5. 1. " CHN_A ,Waterwark level setting for channel A DMA"
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group ad:0xF04A00B8++0x03
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line.long 0x00 "CONFIG_DMA_CTL,Configuration dma control register"
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hexmask.long.byte 0x00 2.--7. 1. " TRIG_SEL ,Select source to trigger dma request. 1. CMP_A_CE 2. CMP_B_CE 3. CMP_C_CE 4. CMP_D_CE 5. CNT_G0_CE 6. CNT_G1_CE"
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bitfld.long 0x00 1. " SIG_MASK ,Mask configuration dma request hardware output" "0,1"
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bitfld.long 0x00 0. " EN ,DMA enable for register configuration" "0,1"
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group ad:0xF04A00BC++0x03
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line.long 0x00 "FIFO_REQ_STATUS,FIFO request status"
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bitfld.long 0x00 3. " FIFO_D ,FIFO D reach water mark level" "0,1"
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bitfld.long 0x00 2. " FIFO_C ,FIFO C reach water mark level" "0,1"
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bitfld.long 0x00 1. " FIFO_B ,FIFO B reach water mark level" "0,1"
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bitfld.long 0x00 0. " FIFO_A ,FIFO A reach water mark level" "0,1"
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group ad:0xF04A00C0++0x03
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line.long 0x00 "FIFO_A,FIFO_entry for compare channel A"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04A00C4++0x03
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line.long 0x00 "FIFO_B,FIFO_entry for compare channel B"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04A00C8++0x03
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line.long 0x00 "FIFO_C,FIFO_entry for compare channel C"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04A00CC++0x03
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line.long 0x00 "FIFO_D,FIFO_entry for compare channel D"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04A00D0++0x03
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line.long 0x00 "FIFO_STA0,FIFO status0 register."
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bitfld.long 0x00 24. " FIFO_ERR_B ,InDIcate FIFO underrun or overrun." "0,1"
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hexmask.long.byte 0x00 18.--23. 1. " FIFO_ENTRIES_B ,InDIcate FIFO data number"
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bitfld.long 0x00 17. " FIFO_EMPTY_B ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 16. " FIFO_FULL_B ,InDIcate FIFO is full." "0,1"
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textline " "
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bitfld.long 0x00 9. "FIFO_ERR_A ,InDIcate FIFO underrun or overrun." "0,1"
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hexmask.long.byte 0x00 2.--8. 1. " FIFO_ENTRIES_A ,InDIcate FIFO data number"
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bitfld.long 0x00 1. " FIFO_EMPTY_A ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 0. " FIFO_FULL_A ,InDIcate FIFO is full." "0,1"
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group ad:0xF04A00D4++0x03
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line.long 0x00 "FIFO_STA1,FIFO status1 register."
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bitfld.long 0x00 23. " FIFO_ERR_D ,InDIcate FIFO underrun or overrun." "0,1"
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bitfld.long 0x00 18.--22. " FIFO_ENTRIES_D ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 17. " FIFO_EMPTY_D ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 16. " FIFO_FULL_D ,InDIcate FIFO is full." "0,1"
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textline " "
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bitfld.long 0x00 7. "FIFO_ERR_C ,InDIcate FIFO underrun or overrun." "0,1"
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bitfld.long 0x00 2.--6. " FIFO_ENTRIES_C ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 1. " FIFO_EMPTY_C ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 0. " FIFO_FULL_C ,InDIcate FIFO is full." "0,1"
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group ad:0xF04A0100++0x03
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line.long 0x00 "CNT_G0_INIT,Counter G0 initial value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04A0104++0x03
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line.long 0x00 "CNT_G0_OVF,Counter G0 overflow value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04A0108++0x03
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line.long 0x00 "CNT_G0_CFG,CNT_G0 configuration register."
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bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset coun" "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
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bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04A010C++0x03
|
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line.long 0x00 "CNT_G0_EN,CNT_G0 enable register"
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
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group ad:0xF04A0110++0x03
|
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line.long 0x00 "CNT_G0,CNT_G0 TIMER"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
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group ad:0xF04A0114++0x03
|
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line.long 0x00 "CNT_G0_MFC,cnt_g0 Modulation Frequency Control"
|
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bitfld.long 0x00 0.--3. " MFC_UP ,ncreasing modulation frequency up to 2^N times, where N ranged in between [0,10]. 0 means MFC DIsable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04A0120++0x03
|
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line.long 0x00 "CNT_G1_INIT,Counter G1 initial value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF04A0124++0x03
|
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line.long 0x00 "CNT_G1_OVF,Counter G1 overflow value registe"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04A0128++0x03
|
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line.long 0x00 "CNT_G1_CFG,CNT_G1 configuration register."
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bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset coun" "0,1"
|
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW" "0,1"
|
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bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
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textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04A012C++0x03
|
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line.long 0x00 "CNT_G1_EN,CNT_G1 enable register"
|
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
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group ad:0xF04A0130++0x03
|
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line.long 0x00 "CNT_G1,CNT_G1 TIMER"
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
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group ad:0xF04A0134++0x03
|
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line.long 0x00 "CNT_G1_MFC,CNT_G1 Modulation Frequency Control"
|
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bitfld.long 0x00 0.--3. " MFC_UP ,ncreasing modulation frequency up to 2^N times, where N ranged in between [0,10]. 0 means MFC DIsable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04A0220++0x03
|
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line.long 0x00 "CMP_A_CONFIG,Compare A channel configuration register"
|
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
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bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
|
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
|
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
|
group ad:0xF04A0224++0x03
|
|
line.long 0x00 "CMP_A_EVENT_OUT_MODE,Compare A channel event output mode register"
|
|
bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp1 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
|
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04A0228++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID0,Compare A channel output pulse width register0"
|
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
|
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
|
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group ad:0xF04A022C++0x03
|
|
line.long 0x00 "CMP_A_PULSE_WID1,Compare A channel output pulse width register1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
|
|
group ad:0xF04A0230++0x03
|
|
line.long 0x00 "CMP_A_00_VAL,Compare value for compare A channel cmp00 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A0234++0x03
|
|
line.long 0x00 "CMP_A_01_VAL,Compare value for compare A channel cmp01 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A0238++0x03
|
|
line.long 0x00 "CMP_A_10_VAL,Compare value for compare A channel cmp10 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A023C++0x03
|
|
line.long 0x00 "CMP_A_11_VAL,Compare value for compare A channel cmp11 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A0240++0x03
|
|
line.long 0x00 "CMP_A_DITHER,Compare A channel DIther register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
|
|
group ad:0xF04A0244++0x03
|
|
line.long 0x00 "CMP_A_OFFSET,Compare A offset value register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
|
group ad:0xF04A024C++0x03
|
|
line.long 0x00 "CMP_A_EID,Compare A channel event ID register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,CMP11 event ID"
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|
hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,CMP10 event ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,CMP01 event ID"
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|
hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,CMP00 event ID"
|
|
group ad:0xF04A0250++0x03
|
|
line.long 0x00 "CMP_B_CONFIG,Compare B channel configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
|
|
bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
|
bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
|
|
bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
|
|
bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
|
group ad:0xF04A0254++0x03
|
|
line.long 0x00 "CMP_B_EVENT_OUT_MODE,Compare B channel event output mode register"
|
|
bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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|
group ad:0xF04A0258++0x03
|
|
line.long 0x00 "CMP_B_PULSE_WID0,Compare B channel output pulse width register0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04A025C++0x03
|
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line.long 0x00 "CMP_B_PULSE_WID1,Compare B channel output pulse width register1"
|
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
|
|
group ad:0xF04A0260++0x03
|
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line.long 0x00 "CMP_B_00_VAL,Compare value for compare B channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
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group ad:0xF04A0264++0x03
|
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line.long 0x00 "CMP_B_01_VAL,Compare value for compare B channel cmp01 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
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group ad:0xF04A0268++0x03
|
|
line.long 0x00 "CMP_B_10_VAL,Compare value for compare B channel cmp10 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A026C++0x03
|
|
line.long 0x00 "CMP_B_11_VAL,Compare value for compare B channel cmp11 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A0270++0x03
|
|
line.long 0x00 "CMP_B_DITHER,Compare B channel DIther register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
|
|
group ad:0xF04A0274++0x03
|
|
line.long 0x00 "CMP_B_OFFSET,Compare B offset value register"
|
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
|
group ad:0xF04A0280++0x03
|
|
line.long 0x00 "CMP_C_CONFIG,Compare C channel configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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|
bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF04A0284++0x03
|
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line.long 0x00 "CMP_C_EVENT_OUT_MODE,Compare C channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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|
textline " "
|
|
bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04A0288++0x03
|
|
line.long 0x00 "CMP_C_PULSE_WID0,Compare C channel output pulse width register0"
|
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
|
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
|
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
|
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
|
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group ad:0xF04A028C++0x03
|
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line.long 0x00 "CMP_C_PULSE_WID1,Compare C channel output pulse width register1"
|
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
|
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group ad:0xF04A0290++0x03
|
|
line.long 0x00 "CMP_C_00_VAL,Compare value for compare C channel cmp00 event"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A0294++0x03
|
|
line.long 0x00 "CMP_C_01_VAL,Compare value for compare C channel cmp01 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A0298++0x03
|
|
line.long 0x00 "CMP_C_10_VAL,Compare value for compare C channel cmp10 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A029C++0x03
|
|
line.long 0x00 "CMP_C_11_VAL,Compare value for compare C channel cmp11 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A02A0++0x03
|
|
line.long 0x00 "CMP_C_DITHER,Compare C channel DIther register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
|
|
group ad:0xF04A02A4++0x03
|
|
line.long 0x00 "CMP_C_OFFSET,Compare C offset value register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
|
group ad:0xF04A02B0++0x03
|
|
line.long 0x00 "CMP_D_CONFIG,Compare D channel configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
|
|
bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
|
bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
|
|
bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
|
|
bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
|
|
bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
|
|
group ad:0xF04A02B4++0x03
|
|
line.long 0x00 "CMP_D_EVENT_OUT_MODE,Compare D channel event output mode register"
|
|
bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF04A02B8++0x03
|
|
line.long 0x00 "CMP_D_PULSE_WID0,Compare D channel output pulse width register0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
|
|
group ad:0xF04A02BC++0x03
|
|
line.long 0x00 "CMP_D_PULSE_WID1,Compare D channel output pulse width register1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
|
|
group ad:0xF04A02C0++0x03
|
|
line.long 0x00 "CMP_D_00_VAL,Compare value for compare D channel cmp00 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A02C4++0x03
|
|
line.long 0x00 "CMP_D_01_VAL,Compare value for compare D channel cmp01 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A02C8++0x03
|
|
line.long 0x00 "CMP_D_10_VAL,Compare value for compare D channel cmp10 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A02CC++0x03
|
|
line.long 0x00 "CMP_D_11_VAL,Compare value for compare D channel cmp11 event"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
|
|
group ad:0xF04A02D0++0x03
|
|
line.long 0x00 "CMP_D_DITHER,Compare D channel DIther register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
|
|
bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
|
|
bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
|
|
group ad:0xF04A02D4++0x03
|
|
line.long 0x00 "CMP_D_OFFSET,Compare D offset value register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
|
|
group ad:0xF04A02E0++0x03
|
|
line.long 0x00 "CMP_CTRL,Compare control register"
|
|
bitfld.long 0x00 28. " CMP_A_EID_UPD ,Update EID value. Will be auto clear after completing update EID value." "0,1"
|
|
bitfld.long 0x00 27. " CMP_D1_INIT_UPD ,Update cmp_d1 output initial value. Will be auto clear after completing update initial value." "0,1"
|
|
bitfld.long 0x00 26. " CMP_D0_INIT_UPD ,Update cmp_d0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 25. " CMP_C1_INIT_UPD ,Update cmp_c1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 24. "CMP_C0_INIT_UPD ,Update cmp_c0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 23. " CMP_B1_INIT_UPD ,Update cmp_b1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 22. " CMP_B0_INIT_UPD ,Update cmp_b0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 21. " CMP_A1_INIT_UPD ,Update cmp_a1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 20. "CMP_A0_INIT_UPD ,Update cmp_a0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 19. " CMP_D1_INIT_STATUS ,cmp_d1 output initial status" "0,1"
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bitfld.long 0x00 18. " CMP_D0_INIT_STATUS ,cmp_d0 output initial status" "0,1"
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bitfld.long 0x00 17. " CMP_C1_INIT_STATUS ,cmp_c1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 16. "CMP_C0_INIT_STATUS ,cmp_c0 output initial status" "0,1"
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bitfld.long 0x00 15. " CMP_B1_INIT_STATUS ,cmp_b1 output initial status" "0,1"
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bitfld.long 0x00 14. " CMP_B0_INIT_STATUS ,cmp_b0 output initial status" "0,1"
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bitfld.long 0x00 13. " CMP_A1_INIT_STATUS ,cmp_a1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 12. "CMP_A0_INIT_STATUS ,cmp_a0 output initial status" "0,1"
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bitfld.long 0x00 11. " CMP_D_VAL_UPD ,Update all the compare value registers for compare D channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 10. " CMP_C_VAL_UPD ,Update all the compare value registers for compare C channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 9. " CMP_B_VAL_UPD ,Update all the compare value registers for compare B channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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textline " "
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bitfld.long 0x00 8. "CMP_A_VAL_UPD ,Update all the compare value registers for compare A channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 7. " CMP_D_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CMP_C_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 5. " CMP_B_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour.." "0,1"
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textline " "
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bitfld.long 0x00 4. "CMP_A_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 3. " CMP_D_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 2. " CMP_C_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 1. " CMP_B_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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textline " "
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bitfld.long 0x00 0. "CMP_A_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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group ad:0xF04A0320++0x03
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line.long 0x00 "CMP_A_SSE_CTRL,Synthesis CMP_A0,CMP_B0,CMP_C0 and CMP_D0 outputs and CMP_A1 signals into one signal for compare channel A"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_A_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04A0324++0x03
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line.long 0x00 "CMP_A_SSE_REG,Signal synthesis for compare A output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04A0328++0x03
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line.long 0x00 "CMP_B_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_B1 signals into one signal for compare channel B"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_B_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04A032C++0x03
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line.long 0x00 "CMP_B_SSE_REG,Signal synthesis for compare B output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04A0330++0x03
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line.long 0x00 "CMP_C_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_C1 signals into one signal for compare channel C"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_C_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04A0334++0x03
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line.long 0x00 "CMP_C_SSE_REG,Signal synthesis for compare C output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04A0338++0x03
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line.long 0x00 "CMP_D_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_D1 signals into one signal for compare channel D"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_D_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04A033C++0x03
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line.long 0x00 "CMP_D_SSE_REG,Signal synthesis for compare D output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04A0350++0x03
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line.long 0x00 "CMP_A_INPUT_SEL,Compare A channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04A0354++0x03
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line.long 0x00 "CMP_B_INPUT_SEL,Compare B channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04A0358++0x03
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line.long 0x00 "CMP_C_INPUT_SEL,Compare C channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04A035C++0x03
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line.long 0x00 "CMP_D_INPUT_SEL,Compare D channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04A0360++0x03
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line.long 0x00 "CNT_G0_INPUT_SEL,Counter G0 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04A0364++0x03
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line.long 0x00 "CNT_G1_INPUT_SEL,Counter G1 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04A0368++0x03
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line.long 0x00 "EXT_OUTPUT_SEL,External output source select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04A036C++0x03
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line.long 0x00 "TRIGC_POL_INV,Event trigger polarity invert"
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bitfld.long 0x00 13. " EXT_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 12. " EXT_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 11. " CNT_G1_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 10. " CNT_G1_SET ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 9. "CNT_G0_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 8. " CNT_G0_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 7. " CMP_D_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 6. " CMP_D_SET ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 5. "CMP_C_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 4. " CMP_C_SET ,Polarity invert" "0,1"
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bitfld.long 0x00 3. " CMP_B_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 2. " CMP_B_SET ,Polarity invert" "0,1"
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textline " "
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bitfld.long 0x00 1. "CMP_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 0. " CMP_A_SET ,Polarity invert" "0,1"
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group ad:0xF04A0374++0x03
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line.long 0x00 "CMP_SW_TRIG,Compare signal software trigger register"
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bitfld.long 0x00 7. " CMP_D_CLR ,Set high to generate CLR pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CMP_C_CLR ,Set high to generate CLR pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CMP_B_CLR ,Set high to generate CLR pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " CMP_A_CLR ,Set high to generate CLR pulse signal for compare A channel. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 3. "CMP_D_SET ,Set high to generate SET pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CMP_C_SET ,Set high to generate SET pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CMP_B_SET ,Set high to generate SET pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CMP_A_SET ,Set high to generate SET pulse signal for compare A channel. Auto clear after set." "0,1"
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group ad:0xF04A0378++0x03
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line.long 0x00 "CNT_EXT_SW_TRIG,Counter and external signal software trigger register"
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bitfld.long 0x00 5. " EXT_CLR ,Set high to generate CLR pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " EXT_SET ,Set high to generate SET pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 3. " CNT_G1_CLR ,Set high to generate CLR pulse signal for CNT_G1. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CNT_G1_SET ,Set high to generate SET pulse signal for CNT_G1. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 1. "CNT_G0_CLR ,Set high to generate CLR pulse signal for CNT_G0. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CNT_G0_SET ,Set high to generate SET pulse signal for CNT_G0. Auto clear after set." "0,1"
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group ad:0xF04A0380++0x03
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line.long 0x00 "SW_TRIG_CTRL,SW trigger event generation control"
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bitfld.long 0x00 15. " SW_TRIG3_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 14. " SW_TRIG3_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 13. " SW_TRIG3_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 12. " SW_TRIG3_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 11. "SW_TRIG2_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 10. " SW_TRIG2_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 9. " SW_TRIG2_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 8. " SW_TRIG2_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 7. "SW_TRIG1_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 6. " SW_TRIG1_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 5. " SW_TRIG1_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 4. " SW_TRIG1_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 3. "SW_TRIG0_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 2. " SW_TRIG0_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 1. " SW_TRIG0_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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group ad:0xF04A0384++0x03
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line.long 0x00 "SW_TRIG_STATUS,SW trigger outputs status"
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bitfld.long 0x00 3. " SW_TRIG3 ,SW trigger output" "0,1"
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bitfld.long 0x00 2. " SW_TRIG2 ,SW trigger output" "0,1"
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bitfld.long 0x00 1. " SW_TRIG1 ,SW trigger output" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0 ,SW trigger output" "0,1"
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group ad:0xF04A0388++0x03
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line.long 0x00 "SW_TRIG_PULSE0,SW trigger0 and trigger1 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG1_WIDTH ,Pulse width of SW trigger1"
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hexmask.long.word 0x00 0.--15. 1. " TRIG0_WIDTH ,Pulse width of SW trigger0"
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group ad:0xF04A038C++0x03
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line.long 0x00 "SW_TRIG_PULSE1,SW trigger2 and trigger3 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG3_WIDTH ,Pulse width of SW trigger3"
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hexmask.long.word 0x00 0.--15. 1. " TRIG2_WIDTH ,Pulse width of SW trigger2"
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group ad:0xF04A0410++0x03
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line.long 0x00 "FAULT0_FLT,Filter setting for fault0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF04A0414++0x03
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line.long 0x00 "FAULT1_FLT,Filter setting for fault1 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF04A0418++0x03
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line.long 0x00 "FAULT2_FLT,Filter setting for fault2 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF04A041C++0x03
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line.long 0x00 "FAULT3_FLT,Filter setting for fault3 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF04A0420++0x03
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line.long 0x00 "SYNC_DIS,Synchronization DIsable control register"
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bitfld.long 0x00 5. " FAULT3 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 4. " FAULT2 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 3. " FAULT1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 2. " FAULT0 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 1. "EXT_CLR ,DIsable synchronization" "0,1"
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bitfld.long 0x00 0. " EXT_SET ,DIsable synchronization" "0,1"
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group ad:0xF04A0440++0x03
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line.long 0x00 "CMP_A_FAULT_EVENT_CTRL,Compare A channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF04A0444++0x03
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line.long 0x00 "CMP_B_FAULT_EVENT_CTRL,Compare B channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF04A0448++0x03
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line.long 0x00 "CMP_C_FAULT_EVENT_CTRL,Compare C channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
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group ad:0xF04A044C++0x03
|
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line.long 0x00 "CMP_D_FAULT_EVENT_CTRL,Compare D channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
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group ad:0xF04A0460++0x03
|
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line.long 0x00 "CMP_A_DTI_CTRL,Dead time insertion control register for compare A channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
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textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
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group ad:0xF04A0464++0x03
|
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line.long 0x00 "CMP_A_DTI_WID,Dead time insertion width register for compare A channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF04A0468++0x03
|
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line.long 0x00 "CMP_B_DTI_CTRL,Dead time insertion control register for compare B channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04A046C++0x03
|
|
line.long 0x00 "CMP_B_DTI_WID,Dead time insertion width register for compare B channel"
|
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hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
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group ad:0xF04A0470++0x03
|
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line.long 0x00 "CMP_C_DTI_CTRL,Dead time insertion control register for compare C channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04A0474++0x03
|
|
line.long 0x00 "CMP_C_DTI_WID,Dead time insertion width register for compare C channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04A0478++0x03
|
|
line.long 0x00 "CMP_D_DTI_CTRL,Dead time insertion control register for compare D channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04A047C++0x03
|
|
line.long 0x00 "CMP_D_DTI_WID,Dead time insertion width register for compare D channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04A0500++0x03
|
|
line.long 0x00 "SIGNAL_STATUS,Signal status register"
|
|
bitfld.long 0x00 15. " CMP_D_CLR ,Compare D clear signal" "0,1"
|
|
bitfld.long 0x00 14. " CMP_D_SET ,Compare D set signal" "0,1"
|
|
bitfld.long 0x00 13. " CMP_C_CLR ,Compare C clear signal" "0,1"
|
|
bitfld.long 0x00 12. " CMP_C_SET ,Compare C set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_B_CLR ,Compare B clear signal" "0,1"
|
|
bitfld.long 0x00 10. " CMP_B_SET ,Compare B set signal" "0,1"
|
|
bitfld.long 0x00 9. " CMP_A_CLR ,Compare A clear signal" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A_SET ,Compare A set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D1 ,Compare D1 signal" "0,1"
|
|
bitfld.long 0x00 6. " CMP_D0 ,Compare D0 signal" "0,1"
|
|
bitfld.long 0x00 5. " CMP_C1 ,Compare C1 signal" "0,1"
|
|
bitfld.long 0x00 4. " CMP_C0 ,Compare C0 signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CMP_B1 ,Compare B1 signal" "0,1"
|
|
bitfld.long 0x00 2. " CMP_B0 ,Compare B0 signal" "0,1"
|
|
bitfld.long 0x00 1. " CMP_A1 ,Compare A1 signal" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A0 ,Compare A0 signal" "0,1"
|
|
group ad:0xF04A0FFC++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
tree.end
|
|
tree "EPWM4"
|
|
width 28.
|
|
group ad:0xF04B0000++0x03
|
|
line.long 0x00 "INT_STA,Function interrupt status register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Channel D DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Channel C DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Channel B DMA request interrupt" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Channel A DMA request interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,CNT_G1 overflow" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,CNT_G0 overflow" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Compare D event happens" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Compare C event happens" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Compare B event happens" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Compare A event happens" "0,1"
|
|
group ad:0xF04B0004++0x03
|
|
line.long 0x00 "INT_STA_EN,Function interrupt status enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,Status enable" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Status enable" "0,1"
|
|
group ad:0xF04B0008++0x03
|
|
line.long 0x00 "INT_SIG_EN,Function interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CHN_D_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CHN_C_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CHN_B_DMA_REQ ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CHN_A_DMA_REQ ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CNT_G1_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 4. " CNT_G0_OVF ,Singal enable" "0,1"
|
|
bitfld.long 0x00 3. " CMP_D ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " CMP_C ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CMP_B ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A ,Singal enable" "0,1"
|
|
group ad:0xF04B000C++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA,Correctable error interrupt status register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04B0010++0x03
|
|
line.long 0x00 "COR_ERR_INT_STA_EN,Correctable error interrupt status enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04B0014++0x03
|
|
line.long 0x00 "COR_ERR_INT_SIG_EN,Correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04B0018++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA,Uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,CMP D value register is updated twice" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,CMP C value register is updated twice" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,CMP B value register is updated twice" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,CMP A value register is updated twice" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,CMP D value register is not updated" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,CMP C value register is not updated" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,CMP B value register is not updated" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,CMP A value register is not updated" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,CMP D fault event" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,CMP C fault event" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,CMP B fault event" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,CMP A fault event" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,CMP D0 output fault" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,CMP C0 output fault" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,CMP B0 output fault" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,CMP A0 output fault" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,FIFO D underrun" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,FIFO C underrun" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,FIFO B underrun" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,FIFO A underrun" "0,1"
|
|
group ad:0xF04B001C++0x03
|
|
line.long 0x00 "UNC_ERR_INT_STA_EN,Uncorrectable error interrupt status enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Status enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Status enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Status enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Status enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Status enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Status enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Status enable" "0,1"
|
|
group ad:0xF04B0020++0x03
|
|
line.long 0x00 "UNC_ERR_INT_SIG_EN,Uncorrectable error interrupt signal enable register"
|
|
bitfld.long 0x00 23. " CMP_D_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 22. " CMP_C_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 21. " CMP_B_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
bitfld.long 0x00 20. " CMP_A_REG_UPD_TWICE ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "CMP_D_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 18. " CMP_C_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 17. " CMP_B_REG_NO_UPD ,Singal enable" "0,1"
|
|
bitfld.long 0x00 16. " CMP_A_REG_NO_UPD ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "CMP_D_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 14. " CMP_C_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 13. " CMP_B_FAULT_EVENT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 12. " CMP_A_FAULT_EVENT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_D0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 10. " CMP_C0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 9. " CMP_B0_FAULT ,Singal enable" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A0_FAULT ,Singal enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "FIFO_D_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 2. " FIFO_C_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 1. " FIFO_B_UNDERRUN ,Singal enable" "0,1"
|
|
bitfld.long 0x00 0. " FIFO_A_UNDERRUN ,Singal enable" "0,1"
|
|
group ad:0xF04B0024++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata corrctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata corrctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04B0028++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04B002C++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 9. " CONFIG_DMA_BW_COR_ERR ,Config_dma backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA_D_BW_COR_ERR ,DMA_D backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 7. " DMA_C_BW_COR_ERR ,DMA_C backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 6. " DMA_B_BW_COR_ERR ,DMA_B backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "DMA_A_BW_COR_ERR ,DMA_A backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_D_RDATA_COR_ERR ,RAM D rdata correctable error." "0,1"
|
|
bitfld.long 0x00 3. " RAM_C_RDATA_COR_ERR ,RAM C rdata correctable error." "0,1"
|
|
bitfld.long 0x00 2. " RAM_B_RDATA_COR_ERR ,RAM B rdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "RAM_A_RDATA_COR_ERR ,RAM A rdata correctable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF04B0030++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Cock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Cock monitor compare0 erro" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error." "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error." "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error." "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04B0034++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,Config_dma eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04B0038++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 31. " CLK_MON_ERR1 ,Clock monitor compare1 error" "0,1"
|
|
bitfld.long 0x00 30. " CLK_MON_ERR0 ,Clock monitor compare0 error" "0,1"
|
|
bitfld.long 0x00 27. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 26. " CONFIG_DMA_EOBA_ERR ,CONFIG_DMA eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA_D_EOBA_ERR ,DMA_D eoba error" "0,1"
|
|
bitfld.long 0x00 24. " DMA_C_EOBA_ERR ,DMA_C eoba error" "0,1"
|
|
bitfld.long 0x00 23. " DMA_B_EOBA_ERR ,DMA_B eoba error" "0,1"
|
|
bitfld.long 0x00 22. " DMA_A_EOBA_ERR ,DMA_A eoba error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. "CONFIG_DMA_BW_FATAL_ERR ,Config_dma backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 20. " DMA_D_BW_FATAL_ERR ,DMA_D backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 19. " DMA_C_BW_FATAL_ERR ,DMA_C backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 18. " DMA_B_BW_FATAL_ERR ,DMA_B backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "DMA_A_BW_FATAL_ERR ,DMA_A backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 16. " CONFIG_DMA_BW_UNC_ERR ,Config_dma backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 15. " DMA_D_BW_UNC_ERR ,DMA_D backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 14. " DMA_C_BW_UNC_ERR ,DMA_C backwad channel uncorrectable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA_B_BW_UNC_ERR ,DMA_B backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 12. " DMA_A_BW_UNC_ERR ,DMA_A backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 11. " RAM_D_RDATA_FATAL_ERR ,RAM D rdata fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RAM_C_RDATA_FATAL_ERR ,RAM C rdata fatal error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "RAM_B_RDATA_FATAL_ERR ,RAM B rdata fatal error" "0,1"
|
|
bitfld.long 0x00 8. " RAM_A_RDATA_FATAL_ERR ,RAM A rdata fatal error" "0,1"
|
|
bitfld.long 0x00 7. " RAM_D_RDATA_UNC_ERR ,RAM D rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 6. " RAM_C_RDATA_UNC_ERR ,RAM C rdata uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "RAM_B_RDATA_UNC_ERR ,RAM B rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 4. " RAM_A_RDATA_UNC_ERR ,RAM A rdata uncorrectable error" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF04B003C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_1,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04B0040++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_STA_EN_1,Function safety correctable error interrupt status enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,Config_dma eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04B0044++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_INT_SIG_EN_1,Function safety correctable error interrupt signal enable register"
|
|
bitfld.long 0x00 4. " CONFIG_DMA_EOBC_ERR ,CONFIG_DMA eobc error" "0,1"
|
|
bitfld.long 0x00 3. " DMA_D_EOBC_ERR ,DMA_D eobc error" "0,1"
|
|
bitfld.long 0x00 2. " DMA_C_EOBC_ERR ,DMA_C eobc error" "0,1"
|
|
bitfld.long 0x00 1. " DMA_B_EOBC_ERR ,DMA_B eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "DMA_A_EOBC_ERR ,DMA_A eobc error" "0,1"
|
|
group ad:0xF04B004C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF04B0050++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF04B0054++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF04B005C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF04B0060++0x03
|
|
line.long 0x00 "RAM_RDATA_INJ,RAM rdata error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04B0064++0x03
|
|
line.long 0x00 "RAM_RECC_INJ,RAM rdata ECC error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04B0068++0x03
|
|
line.long 0x00 "RAM_RDATA_MON_INJ,RAM rdata SECDED monitor error injection"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,RAM rdata error injection"
|
|
group ad:0xF04B006C++0x03
|
|
line.long 0x00 "RAM_RECC_MON_INJ,RAM rdata ECC SECDED monitor error injection"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,RAM rdata ECC error injection"
|
|
group ad:0xF04B0070++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF04B0074++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF04B0080++0x03
|
|
line.long 0x00 "DMA_FW_DATA_INJ,DMA forward channel data error injection"
|
|
bitfld.long 0x00 16.--18. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF04B0084++0x03
|
|
line.long 0x00 "DMA_FW_CODE_INJ,DMA forward channel code error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF04B0088++0x03
|
|
line.long 0x00 "DMA_BW_DATA_INJ,DMA backward channel data error injection"
|
|
bitfld.long 0x00 16.--19. " CONFIG_DMA ,Data error injection for config dma" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMA_D ,Data error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMA_C ,Data error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DMA_B ,Data error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 0.--3. "DMA_A ,Data error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B008C++0x03
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line.long 0x00 "DMA_BW_CODE_INJ,DMA backward channel code error injection"
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bitfld.long 0x00 16.--19. " CONFIG_DMA ,Code error injection for config_dma." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " DMA_D ,Code error injection for DMA_D channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " DMA_C ,Code error injection for DMA_C channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " DMA_B ,Code error injection for DMA_B channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 0.--3. "DMA_A ,Code error injection for DMA_A channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B0090++0x03
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line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
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bitfld.long 0x00 6. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
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bitfld.long 0x00 5. " COR_ERR ,Correctable error interrupt error injection." "0,1"
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bitfld.long 0x00 4. " CNT_OVF ,Counter overflow and snapshot interrupt error injection." "0,1"
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bitfld.long 0x00 3. " CHN_D ,Channel D interrupt error injection." "0,1"
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textline " "
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bitfld.long 0x00 2. "CHN_C ,Channel C interrupt error injection." "0,1"
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bitfld.long 0x00 1. " CHN_B ,Channel B interrupt error injection." "0,1"
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bitfld.long 0x00 0. " CHN_A ,Channel A interrupt error injection." "0,1"
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group ad:0xF04B0094++0x03
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line.long 0x00 "CLK_MON_CMP_ERR_INJ,Clock monitor compare error injection r"
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bitfld.long 0x00 2.--3. " ERR1 ,Clock monitor 1" "0,1,2,3"
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bitfld.long 0x00 0.--1. " ERR0 ,Clock monitor 0" "0,1,2,3"
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group ad:0xF04B00A0++0x03
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line.long 0x00 "CLK_CONFIG,EPMW clock select and DIvider configuration."
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bitfld.long 0x00 31. " CLK_CHANGE_UPD ,Set this bit to make new DIV_NUM value effective. Will be auto cleared after new DIV_NUM is effective" "0,1"
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bitfld.long 0x00 16.--17. " SRC_CLK_SEL ,Clock source select. 00: High frequency(HF) clock, update to 400mhz. 01: Alternative High frequency(AHF) clock, update to 400mhz. 10: External clock. 11: Low power(LP) clock, typically from low speed on chip RCOSC." "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. " DIV_NUM ,DIvider number for timer clock."
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group ad:0xF04B00A4++0x03
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line.long 0x00 "CLK_MON_EN,Clock monitor enable register"
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bitfld.long 0x00 2. " CMP_SET ,When enable or DIsable clock monitor, set this bit together. This bit is used to inDIcate configuration is completed." "0,1"
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bitfld.long 0x00 1. " EN_N ,Active low.Enable clock monitor1" "0,1"
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bitfld.long 0x00 0. " EN_P ,Active high.Enable clock monitor0" "0,1"
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group ad:0xF04B00A8++0x03
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line.long 0x00 "SW_RST,Software reset"
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bitfld.long 0x00 9. " CNT_G1 ,Reset CNT_G1.Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 8. " CNT_G0 ,Reset CNT_G0.Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 7. " FIFO_D ,Reset FIFO D relative logic. Will be auto cleared after reset complete" "0,1"
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bitfld.long 0x00 6. " FIFO_C ,Reset FIFO C relative logic. Will be auto cleared after reset complete" "0,1"
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textline " "
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bitfld.long 0x00 5. "FIFO_B ,Reset FIFO B relative logic. Will be auto cleared after reset complete" "0,1"
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bitfld.long 0x00 4. " FIFO_A ,Reset FIFO A relative logic. Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 3. " CMP_D ,Reset CMP_D. Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 2. " CMP_C ,Reset CMP_C.Will be auto cleared after reset complete." "0,1"
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textline " "
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bitfld.long 0x00 1. "CMP_B ,Reset CMP_B.Will be auto cleared after reset complete." "0,1"
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bitfld.long 0x00 0. " CMP_A ,Reset CMP_A.Will be auto cleared after reset complete." "0,1"
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group ad:0xF04B00B0++0x03
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line.long 0x00 "CHN_DMA_CTRL,DMA control register"
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bitfld.long 0x00 30. " TWO_CHN_BD_MODE ,When this bit is enable, CMP_B and CMP_D block are sharing DMA_B and FIFO_B. RAM_B and RAM_D are combined are worked with FIFO_B. If four_chn_mode is enable, this bit is ignored." "0,1"
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bitfld.long 0x00 29. " TWO_CHN_AC_MODE ,When this bit is enable, CMP_A and CMP_C block are sharing DMA_A and FIFO_A. RAM_A and RAM_C are combined are worked with FIFO_A. If four_chn_mode is enable, this bit is ignored." "0,1"
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bitfld.long 0x00 28. " FOUR_CHN_MODE ,When this bit is enable, 4 compare blocks are sharing DMA_A and FIFO_A. RAM_A, RAM_B,RAM_C and RAM_D are combined are worked with FIFO_A." "0,1"
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bitfld.long 0x00 26.--27. " CMP_D_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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textline " "
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bitfld.long 0x00 24.--25. "CMP_C_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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bitfld.long 0x00 22.--23. " CMP_B_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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bitfld.long 0x00 20.--21. " CMP_A_MODE ,Compare mode 00: single compare mode 01: dual compare mode 10/11: multiple compare mode" "0,1,2,3"
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bitfld.long 0x00 19. " CMP_D_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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textline " "
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bitfld.long 0x00 18. "CMP_C_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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bitfld.long 0x00 17. " CMP_B_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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bitfld.long 0x00 16. " CMP_A_OUT_MODE ,Select number of compare outputs 0: only cmp0 output 1: Both cmp0 and cmp1 output" "0,1"
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bitfld.long 0x00 14.--15. " CMP_D_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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textline " "
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bitfld.long 0x00 12.--13. "CMP_C_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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bitfld.long 0x00 10.--11. " CMP_B_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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bitfld.long 0x00 8.--9. " CMP_A_DAT_FORMAT ,data format for compare mode 00: 32 bit compare value 01: 16 bit compare value 10/11: 8 bit compare value" "0,1,2,3"
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bitfld.long 0x00 7. " CHN_D_SIG_MASK ,Mask channel D dma request hardware output" "0,1"
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textline " "
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bitfld.long 0x00 6. "CHN_C_SIG_MASK ,Mask channel C dma request hardware output" "0,1"
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bitfld.long 0x00 5. " CHN_B_SIG_MASK ,Mask channel B dma request hardware output" "0,1"
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bitfld.long 0x00 4. " CHN_A_SIG_MASK ,Mask channel A dma request hardware output" "0,1"
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bitfld.long 0x00 3. " CHN_D_EN ,Enable dma request for COMPARE D channel accorDIng to channel D FIFO WML." "0,1"
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textline " "
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bitfld.long 0x00 2. "CHN_C_EN ,Enable dma request for COMPARE C channel accorDIng to channel C FIFO WML." "0,1"
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bitfld.long 0x00 1. " CHN_B_EN ,Enable dma request for COMPARE B channel accorDIng to channel B FIFO WML." "0,1"
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bitfld.long 0x00 0. " CHN_A_EN ,Enable dma request for COMPARE A channel accorDIng to channle A FIFO WML." "0,1"
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group ad:0xF04B00B4++0x03
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line.long 0x00 "DMA_WML,DMA watermark leverl register"
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bitfld.long 0x00 24.--27. " CHN_D ,Waterwark level setting for channel D DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CHN_C ,Waterwark level setting for channel C DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--12. " CHN_B ,Waterwark level setting for channel B DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 0.--5. 1. " CHN_A ,Waterwark level setting for channel A DMA"
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group ad:0xF04B00B8++0x03
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line.long 0x00 "CONFIG_DMA_CTL,Configuration dma control register"
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hexmask.long.byte 0x00 2.--7. 1. " TRIG_SEL ,Select source to trigger dma request. 1. CMP_A_CE 2. CMP_B_CE 3. CMP_C_CE 4. CMP_D_CE 5. CNT_G0_CE 6. CNT_G1_CE"
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bitfld.long 0x00 1. " SIG_MASK ,Mask configuration dma request hardware output" "0,1"
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bitfld.long 0x00 0. " EN ,DMA enable for register configuration" "0,1"
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group ad:0xF04B00BC++0x03
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line.long 0x00 "FIFO_REQ_STATUS,FIFO request status"
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bitfld.long 0x00 3. " FIFO_D ,FIFO D reach water mark level" "0,1"
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bitfld.long 0x00 2. " FIFO_C ,FIFO C reach water mark level" "0,1"
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bitfld.long 0x00 1. " FIFO_B ,FIFO B reach water mark level" "0,1"
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bitfld.long 0x00 0. " FIFO_A ,FIFO A reach water mark level" "0,1"
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group ad:0xF04B00C0++0x03
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line.long 0x00 "FIFO_A,FIFO_entry for compare channel A"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04B00C4++0x03
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line.long 0x00 "FIFO_B,FIFO_entry for compare channel B"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04B00C8++0x03
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line.long 0x00 "FIFO_C,FIFO_entry for compare channel C"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04B00CC++0x03
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line.long 0x00 "FIFO_D,FIFO_entry for compare channel D"
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hexmask.long 0x00 0.--31. 1. " DATA ,FIFO entry"
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group ad:0xF04B00D0++0x03
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line.long 0x00 "FIFO_STA0,FIFO status0 register."
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bitfld.long 0x00 24. " FIFO_ERR_B ,InDIcate FIFO underrun or overrun." "0,1"
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hexmask.long.byte 0x00 18.--23. 1. " FIFO_ENTRIES_B ,InDIcate FIFO data number"
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bitfld.long 0x00 17. " FIFO_EMPTY_B ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 16. " FIFO_FULL_B ,InDIcate FIFO is full." "0,1"
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textline " "
|
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bitfld.long 0x00 9. "FIFO_ERR_A ,InDIcate FIFO underrun or overrun." "0,1"
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hexmask.long.byte 0x00 2.--8. 1. " FIFO_ENTRIES_A ,InDIcate FIFO data number"
|
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bitfld.long 0x00 1. " FIFO_EMPTY_A ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 0. " FIFO_FULL_A ,InDIcate FIFO is full." "0,1"
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group ad:0xF04B00D4++0x03
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line.long 0x00 "FIFO_STA1,FIFO status1 register."
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bitfld.long 0x00 23. " FIFO_ERR_D ,InDIcate FIFO underrun or overrun." "0,1"
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bitfld.long 0x00 18.--22. " FIFO_ENTRIES_D ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 17. " FIFO_EMPTY_D ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 16. " FIFO_FULL_D ,InDIcate FIFO is full." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FIFO_ERR_C ,InDIcate FIFO underrun or overrun." "0,1"
|
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bitfld.long 0x00 2.--6. " FIFO_ENTRIES_C ,InDIcate FIFO data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 1. " FIFO_EMPTY_C ,InDIcate FIFO is empty." "0,1"
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bitfld.long 0x00 0. " FIFO_FULL_C ,InDIcate FIFO is full." "0,1"
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group ad:0xF04B0100++0x03
|
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line.long 0x00 "CNT_G0_INIT,Counter G0 initial value registe"
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF04B0104++0x03
|
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line.long 0x00 "CNT_G0_OVF,Counter G0 overflow value registe"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF04B0108++0x03
|
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line.long 0x00 "CNT_G0_CFG,CNT_G0 configuration register."
|
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bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset coun" "0,1"
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW." "0,1"
|
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bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
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textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
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bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
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bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
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group ad:0xF04B010C++0x03
|
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line.long 0x00 "CNT_G0_EN,CNT_G0 enable register"
|
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bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
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group ad:0xF04B0110++0x03
|
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line.long 0x00 "CNT_G0,CNT_G0 TIMER"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
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group ad:0xF04B0114++0x03
|
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line.long 0x00 "CNT_G0_MFC,cnt_g0 Modulation Frequency Control"
|
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bitfld.long 0x00 0.--3. " MFC_UP ,ncreasing modulation frequency up to 2^N times, where N ranged in between [0,10]. 0 means MFC DIsable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B0120++0x03
|
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line.long 0x00 "CNT_G1_INIT,Counter G1 initial value registe"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
|
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group ad:0xF04B0124++0x03
|
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line.long 0x00 "CNT_G1_OVF,Counter G1 overflow value registe"
|
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hexmask.long 0x00 0.--31. 1. " VAL ,Counter initial value"
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group ad:0xF04B0128++0x03
|
|
line.long 0x00 "CNT_G1_CFG,CNT_G1 configuration register."
|
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bitfld.long 0x00 19. " OVF_RST_DIS ,When this bit is set, overflow event does not reset coun" "0,1"
|
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bitfld.long 0x00 18. " CON_MODE ,0: consecutive count 1: Only count once." "0,1"
|
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bitfld.long 0x00 17. " OVF_UPD ,When this bit is set, counter overflow value will be updated to shadow register. This bit will be auto cleared by HW" "0,1"
|
|
bitfld.long 0x00 16. " INIT_UPD ,When this bit is set, counter will be set to initial value. Then this bit will be auto cleared by HW." "0,1"
|
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textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. "INTERVAL ,Count enable interval."
|
|
bitfld.long 0x00 7. " CE_EN ,Counter event enable" "0,1"
|
|
bitfld.long 0x00 5.--6. " CLR_TRIG_SEL ,CLR event trigger mode 2'b00: Event ignored 2b01: Positive edge of CLR signal. 2'b10: Negative edge of CLR signal 2'b11: Level high of CLR signal" "0,1,2,3"
|
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bitfld.long 0x00 3.--4. " SET_UPD_SEL ,SET event update mode selection 2'b00: no update 2'b01: only reload overflow value. 2'b10: only reload counter initial value. 2'b11: reload both overflow and initial value" "0,1,2,3"
|
|
textline " "
|
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bitfld.long 0x00 1.--2. "SET_TRIG_SEL ,SET event trigger mode 2'b00: Event ignored 2b01: Positive edge of SET signal. 2'b10: Negative edge of SET signal 2'b11: Level high of SET signal" "0,1,2,3"
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bitfld.long 0x00 0. " FRC_RLD ,SW force reload .After this bit is set, counter will be reset to 0. Then this bit will be auto cleared by HW." "0,1"
|
|
group ad:0xF04B012C++0x03
|
|
line.long 0x00 "CNT_G1_EN,CNT_G1 enable register"
|
|
bitfld.long 0x00 0. " EN ,When this bit is set, counter start to count." "0,1"
|
|
group ad:0xF04B0130++0x03
|
|
line.long 0x00 "CNT_G1,CNT_G1 TIMER"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,Timer counter value"
|
|
group ad:0xF04B0134++0x03
|
|
line.long 0x00 "CNT_G1_MFC,CNT_G1 Modulation Frequency Control"
|
|
bitfld.long 0x00 0.--3. " MFC_UP ,ncreasing modulation frequency up to 2^N times, where N ranged in between [0,10]. 0 means MFC DIsable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group ad:0xF04B0220++0x03
|
|
line.long 0x00 "CMP_A_CONFIG,Compare A channel configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
|
|
bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
|
|
bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
textline " "
|
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bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
|
bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
|
bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
|
|
bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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|
textline " "
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF04B0224++0x03
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line.long 0x00 "CMP_A_EVENT_OUT_MODE,Compare A channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp1 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04B0228++0x03
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line.long 0x00 "CMP_A_PULSE_WID0,Compare A channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04B022C++0x03
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line.long 0x00 "CMP_A_PULSE_WID1,Compare A channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04B0230++0x03
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line.long 0x00 "CMP_A_00_VAL,Compare value for compare A channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B0234++0x03
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line.long 0x00 "CMP_A_01_VAL,Compare value for compare A channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B0238++0x03
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line.long 0x00 "CMP_A_10_VAL,Compare value for compare A channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B023C++0x03
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line.long 0x00 "CMP_A_11_VAL,Compare value for compare A channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B0240++0x03
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line.long 0x00 "CMP_A_DITHER,Compare A channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04B0244++0x03
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line.long 0x00 "CMP_A_OFFSET,Compare A offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04B024C++0x03
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line.long 0x00 "CMP_A_EID,Compare A channel event ID register"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,CMP11 event ID"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,CMP10 event ID"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,CMP01 event ID"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,CMP00 event ID"
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group ad:0xF04B0250++0x03
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line.long 0x00 "CMP_B_CONFIG,Compare B channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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textline " "
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bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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textline " "
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF04B0254++0x03
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line.long 0x00 "CMP_B_EVENT_OUT_MODE,Compare B channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04B0258++0x03
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line.long 0x00 "CMP_B_PULSE_WID0,Compare B channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04B025C++0x03
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line.long 0x00 "CMP_B_PULSE_WID1,Compare B channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04B0260++0x03
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line.long 0x00 "CMP_B_00_VAL,Compare value for compare B channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B0264++0x03
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line.long 0x00 "CMP_B_01_VAL,Compare value for compare B channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B0268++0x03
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line.long 0x00 "CMP_B_10_VAL,Compare value for compare B channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B026C++0x03
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line.long 0x00 "CMP_B_11_VAL,Compare value for compare B channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B0270++0x03
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line.long 0x00 "CMP_B_DITHER,Compare B channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04B0274++0x03
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line.long 0x00 "CMP_B_OFFSET,Compare B offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04B0280++0x03
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line.long 0x00 "CMP_C_CONFIG,Compare C channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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textline " "
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bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
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bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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textline " "
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF04B0284++0x03
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line.long 0x00 "CMP_C_EVENT_OUT_MODE,Compare C channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04B0288++0x03
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line.long 0x00 "CMP_C_PULSE_WID0,Compare C channel output pulse width register0"
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04B028C++0x03
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line.long 0x00 "CMP_C_PULSE_WID1,Compare C channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04B0290++0x03
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line.long 0x00 "CMP_C_00_VAL,Compare value for compare C channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B0294++0x03
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line.long 0x00 "CMP_C_01_VAL,Compare value for compare C channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B0298++0x03
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line.long 0x00 "CMP_C_10_VAL,Compare value for compare C channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B029C++0x03
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line.long 0x00 "CMP_C_11_VAL,Compare value for compare C channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B02A0++0x03
|
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line.long 0x00 "CMP_C_DITHER,Compare C channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04B02A4++0x03
|
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line.long 0x00 "CMP_C_OFFSET,Compare C offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04B02B0++0x03
|
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line.long 0x00 "CMP_D_CONFIG,Compare D channel configuration register"
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hexmask.long.byte 0x00 24.--31. 1. " REFRESH_INTVAL ,When the interval is configured to N, the compare values are used N+1 times before the new compare value is loaded for compare use. In No-DMA mode, if refresh_intval = 0xff, compare value will not be reloaded by oveflow .."
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bitfld.long 0x00 15. " SW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when SW_RLD_SET is set 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from shadow .." "0,1"
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bitfld.long 0x00 14. " SW_RLD_SET ,When this bit is set, will ignore REFRESH_INTVAL to reload compare value. Will auto clear after set" "0,1"
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bitfld.long 0x00 12.--13. " CLR_TRIG_SEL ,CLR event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
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textline " "
|
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bitfld.long 0x00 10.--11. "SET_TRIG_SEL ,SET event trigger mode 00: event ignored; 01: posedge; 10: negedge; 11: high" "0,1,2,3"
|
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bitfld.long 0x00 8. " CE_EN ,Enable compare event" "0,1"
|
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bitfld.long 0x00 6.--7. " CE_TRIG_SEL ,Compare event is triggered by below event 00: cmp00 event 01: cmp01 event 10: cmp10 event 11: cmp11 event" "0,1,2,3"
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bitfld.long 0x00 5. " HW_RLD_MODE ,When using no-dma mode, this bit is used to select compare value update mode when cmp_set event is asserted. 0: Reload compare value from shadow register when next overflow event is asserted. 1. Reload compare value from .." "0,1"
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textline " "
|
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bitfld.long 0x00 4. "RLD_TRIG_MODE ,This bit is used to select compare value update mode 0. Update when overflow event happen. 1. Update when compare event happen. For single mode, this bit should be set to 1 since comparae operation only executes one time and .." "0,1"
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bitfld.long 0x00 2. " CNT_SEL ,Select compared counter 0: cnt_g0 1: cnt_g1" "0,1"
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bitfld.long 0x00 0. " CON_MODE ,Consecutive and single mode 0: Consecutive mode 1: Only execute one time compare." "0,1"
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group ad:0xF04B02B4++0x03
|
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line.long 0x00 "CMP_D_EVENT_OUT_MODE,Compare D channel event output mode register"
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bitfld.long 0x00 20.--22. " CMP1_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " CMP0_OVF ,Select cmp0 output mode when counter overflow happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. " CMP11 ,Select output mode when cmp11 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " CMP10 ,Select output mode when cmp10 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 4.--6. "CMP01 ,Select output mode when cmp01 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " CMP00 ,Select output mode when cmp00 event happens 000: positive pulse. 001: Negative pulse. 010: Signal toggle 011: level high. 100: level_low. other: keep" "0,1,2,3,4,5,6,7"
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group ad:0xF04B02B8++0x03
|
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line.long 0x00 "CMP_D_PULSE_WID0,Compare D channel output pulse width register0"
|
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hexmask.long.byte 0x00 24.--31. 1. " CMP11 ,Output pulse width when cmp11 event happens"
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hexmask.long.byte 0x00 16.--23. 1. " CMP10 ,Output pulse width when cmp10 event happens"
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hexmask.long.byte 0x00 8.--15. 1. " CMP01 ,Output pulse width when cmp01 event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP00 ,Output pulse width when cmp00 event happens"
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group ad:0xF04B02BC++0x03
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line.long 0x00 "CMP_D_PULSE_WID1,Compare D channel output pulse width register1"
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hexmask.long.byte 0x00 8.--15. 1. " CMP0_OVF ,Cmp0 output pulse width when counter overflow event happens"
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hexmask.long.byte 0x00 0.--7. 1. " CMP1_OVF ,Cmp1 output pulse width when counter overflow event happens"
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group ad:0xF04B02C0++0x03
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line.long 0x00 "CMP_D_00_VAL,Compare value for compare D channel cmp00 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B02C4++0x03
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line.long 0x00 "CMP_D_01_VAL,Compare value for compare D channel cmp01 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B02C8++0x03
|
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line.long 0x00 "CMP_D_10_VAL,Compare value for compare D channel cmp10 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B02CC++0x03
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line.long 0x00 "CMP_D_11_VAL,Compare value for compare D channel cmp11 event"
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hexmask.long 0x00 0.--31. 1. " VAL ,Compare value"
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group ad:0xF04B02D0++0x03
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line.long 0x00 "CMP_D_DITHER,Compare D channel DIther register"
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hexmask.long.word 0x00 16.--31. 1. " INIT_OFFSET ,Init offset for carry bit generation of quantization error"
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bitfld.long 0x00 2.--5. " CLIP_RSLT ,DIther clipped LSB data bit width. 0~15 means 1~16 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. " INIT_OFFSET_EN ,When Quantizaion error reach INIT_OFFSET, generate carry bit for clipped data" "0,1"
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bitfld.long 0x00 0. " DITHER_EN ,DIther enable" "0,1"
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group ad:0xF04B02D4++0x03
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line.long 0x00 "CMP_D_OFFSET,Compare D offset value register"
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hexmask.long.word 0x00 0.--15. 1. " VAL ,Signed offset value for compare value"
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group ad:0xF04B02E0++0x03
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line.long 0x00 "CMP_CTRL,Compare control register"
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bitfld.long 0x00 28. " CMP_A_EID_UPD ,Update EID value. Will be auto clear after completing update EID value." "0,1"
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bitfld.long 0x00 27. " CMP_D1_INIT_UPD ,Update cmp_d1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 26. " CMP_D0_INIT_UPD ,Update cmp_d0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 25. " CMP_C1_INIT_UPD ,Update cmp_c1 output initial value. Will be auto clear after completing update initial value." "0,1"
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textline " "
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bitfld.long 0x00 24. "CMP_C0_INIT_UPD ,Update cmp_c0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 23. " CMP_B1_INIT_UPD ,Update cmp_b1 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 22. " CMP_B0_INIT_UPD ,Update cmp_b0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 21. " CMP_A1_INIT_UPD ,Update cmp_a1 output initial value. Will be auto clear after completing update initial value." "0,1"
|
|
textline " "
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bitfld.long 0x00 20. "CMP_A0_INIT_UPD ,Update cmp_a0 output initial value. Will be auto clear after completing update initial value." "0,1"
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bitfld.long 0x00 19. " CMP_D1_INIT_STATUS ,cmp_d1 output initial status" "0,1"
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bitfld.long 0x00 18. " CMP_D0_INIT_STATUS ,cmp_d0 output initial status" "0,1"
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bitfld.long 0x00 17. " CMP_C1_INIT_STATUS ,cmp_c1 output initial status" "0,1"
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textline " "
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bitfld.long 0x00 16. "CMP_C0_INIT_STATUS ,cmp_c0 output initial status" "0,1"
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bitfld.long 0x00 15. " CMP_B1_INIT_STATUS ,cmp_b1 output initial status" "0,1"
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bitfld.long 0x00 14. " CMP_B0_INIT_STATUS ,cmp_b0 output initial status" "0,1"
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bitfld.long 0x00 13. " CMP_A1_INIT_STATUS ,cmp_a1 output initial status" "0,1"
|
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textline " "
|
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bitfld.long 0x00 12. "CMP_A0_INIT_STATUS ,cmp_a0 output initial status" "0,1"
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bitfld.long 0x00 11. " CMP_D_VAL_UPD ,Update all the compare value registers for compare D channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 10. " CMP_C_VAL_UPD ,Update all the compare value registers for compare C channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 9. " CMP_B_VAL_UPD ,Update all the compare value registers for compare B channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
|
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textline " "
|
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bitfld.long 0x00 8. "CMP_A_VAL_UPD ,Update all the compare value registers for compare A channel. Will be auto cleared after compare value is loaded into shadow register." "0,1"
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bitfld.long 0x00 7. " CMP_D_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware .." "0,1"
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bitfld.long 0x00 6. " CMP_C_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 5. " CMP_B_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour.." "0,1"
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textline " "
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bitfld.long 0x00 4. "CMP_A_CONFIG_SET ,After this bit is set, compare configuration will be immeDIately reloaded with corresponDIng configuration in register. SW user need guarantee on the fly configuration changing would not cause unexpected hardware behaviour .." "0,1"
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bitfld.long 0x00 3. " CMP_D_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 2. " CMP_C_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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bitfld.long 0x00 1. " CMP_B_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
|
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textline " "
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bitfld.long 0x00 0. "CMP_A_EN ,Enable compare A channel. In non-consecutive mode, this bit will be auto cleared when compare IRQ event happens." "0,1"
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group ad:0xF04B0320++0x03
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line.long 0x00 "CMP_A_SSE_CTRL,Synthesis CMP_A0,CMP_B0,CMP_C0 and CMP_D0 outputs and CMP_A1 signals into one signal for compare channel A"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_A_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04B0324++0x03
|
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line.long 0x00 "CMP_A_SSE_REG,Signal synthesis for compare A output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04B0328++0x03
|
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line.long 0x00 "CMP_B_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_B1 signals into one signal for compare channel B"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_B_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04B032C++0x03
|
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line.long 0x00 "CMP_B_SSE_REG,Signal synthesis for compare B output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04B0330++0x03
|
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line.long 0x00 "CMP_C_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_C1 signals into one signal for compare channel C"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_C_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04B0334++0x03
|
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line.long 0x00 "CMP_C_SSE_REG,Signal synthesis for compare C output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04B0338++0x03
|
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line.long 0x00 "CMP_D_SSE_CTRL,Synthesis CMP_A0,CMP_B0, CMP_C0 and CMP_D0 outputs and CMP_D1 signals into one signal for compare channel D"
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bitfld.long 0x00 16.--18. " SSE_SO_DET_FAULT ,When detect CMP_D_SSE SO meet below beavior , generate fault IRQ. 000: Level low 001: Level high 010: posedge 011: negedge 100: both edge" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. " EDGE_SEL ,Edge of Each input can be converted to pulse when accorDIng SSE_MODE is high. 00: rising edge 01: failing edge 10/11: both edge"
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bitfld.long 0x00 1.--5. " SSE_MODE ,Each input can be configured as level or edge input 0: Level mode, the signal is synthesized DIrectly. 1: Edge mode, the rising, falling or both edges are converted to pulse before use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. " SSE_EN ,SSE function enable" "0,1"
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group ad:0xF04B033C++0x03
|
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line.long 0x00 "CMP_D_SSE_REG,Signal synthesis for compare D output"
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hexmask.long 0x00 0.--31. 1. " SSE ,Signal synthesis to drive one logic output from 5 logic inputs."
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group ad:0xF04B0350++0x03
|
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line.long 0x00 "CMP_A_INPUT_SEL,Compare A channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B0354++0x03
|
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line.long 0x00 "CMP_B_INPUT_SEL,Compare B channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B0358++0x03
|
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line.long 0x00 "CMP_C_INPUT_SEL,Compare C channel input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B035C++0x03
|
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line.long 0x00 "CMP_D_INPUT_SEL,Compare D channel input select register"
|
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B0360++0x03
|
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line.long 0x00 "CNT_G0_INPUT_SEL,Counter G0 input select register"
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B0364++0x03
|
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line.long 0x00 "CNT_G1_INPUT_SEL,Counter G1 input select register"
|
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B0368++0x03
|
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line.long 0x00 "EXT_OUTPUT_SEL,External output source select register"
|
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bitfld.long 0x00 4.--7. " CLR_SEL ,CLR input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: SW_TRIG0 .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SET_SEL ,SET input select 0000: EXT_SET 0001: EXT_CLR 0010: CMP_A_CE 0011: CMP_B_CE 0100: CMP_C_CE 0101: CMP_D_CE 0110: CNT_G0_CE 0111: CNT_G1_CE 1000: Reserved 1001: Level low 1010: Level high 1011: Sw program pulse 1100: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF04B036C++0x03
|
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line.long 0x00 "TRIGC_POL_INV,Event trigger polarity invert"
|
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bitfld.long 0x00 13. " EXT_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 12. " EXT_SET ,Polarity invert" "0,1"
|
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bitfld.long 0x00 11. " CNT_G1_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 10. " CNT_G1_SET ,Polarity invert" "0,1"
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textline " "
|
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bitfld.long 0x00 9. "CNT_G0_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 8. " CNT_G0_SET ,Polarity invert" "0,1"
|
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bitfld.long 0x00 7. " CMP_D_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 6. " CMP_D_SET ,Polarity invert" "0,1"
|
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textline " "
|
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bitfld.long 0x00 5. "CMP_C_CLR ,Polarity invert" "0,1"
|
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bitfld.long 0x00 4. " CMP_C_SET ,Polarity invert" "0,1"
|
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bitfld.long 0x00 3. " CMP_B_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 2. " CMP_B_SET ,Polarity invert" "0,1"
|
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textline " "
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bitfld.long 0x00 1. "CMP_A_CLR ,Polarity invert" "0,1"
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bitfld.long 0x00 0. " CMP_A_SET ,Polarity invert" "0,1"
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group ad:0xF04B0374++0x03
|
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line.long 0x00 "CMP_SW_TRIG,Compare signal software trigger register"
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bitfld.long 0x00 7. " CMP_D_CLR ,Set high to generate CLR pulse signal for compare D channel. Auto clear after set." "0,1"
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bitfld.long 0x00 6. " CMP_C_CLR ,Set high to generate CLR pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 5. " CMP_B_CLR ,Set high to generate CLR pulse signal for compare B channel. Auto clear after set." "0,1"
|
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bitfld.long 0x00 4. " CMP_A_CLR ,Set high to generate CLR pulse signal for compare A channel. Auto clear after set." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "CMP_D_SET ,Set high to generate SET pulse signal for compare D channel. Auto clear after set." "0,1"
|
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bitfld.long 0x00 2. " CMP_C_SET ,Set high to generate SET pulse signal for compare C channel. Auto clear after set." "0,1"
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bitfld.long 0x00 1. " CMP_B_SET ,Set high to generate SET pulse signal for compare B channel. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CMP_A_SET ,Set high to generate SET pulse signal for compare A channel. Auto clear after set." "0,1"
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group ad:0xF04B0378++0x03
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line.long 0x00 "CNT_EXT_SW_TRIG,Counter and external signal software trigger register"
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bitfld.long 0x00 5. " EXT_CLR ,Set high to generate CLR pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 4. " EXT_SET ,Set high to generate SET pulse signal for external output. Auto clear after set." "0,1"
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bitfld.long 0x00 3. " CNT_G1_CLR ,Set high to generate CLR pulse signal for CNT_G1. Auto clear after set." "0,1"
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bitfld.long 0x00 2. " CNT_G1_SET ,Set high to generate SET pulse signal for CNT_G1. Auto clear after set." "0,1"
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textline " "
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bitfld.long 0x00 1. "CNT_G0_CLR ,Set high to generate CLR pulse signal for CNT_G0. Auto clear after set." "0,1"
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bitfld.long 0x00 0. " CNT_G0_SET ,Set high to generate SET pulse signal for CNT_G0. Auto clear after set." "0,1"
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group ad:0xF04B0380++0x03
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line.long 0x00 "SW_TRIG_CTRL,SW trigger event generation control"
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bitfld.long 0x00 15. " SW_TRIG3_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 14. " SW_TRIG3_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 13. " SW_TRIG3_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 12. " SW_TRIG3_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 11. "SW_TRIG2_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 10. " SW_TRIG2_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 9. " SW_TRIG2_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 8. " SW_TRIG2_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 7. "SW_TRIG1_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 6. " SW_TRIG1_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 5. " SW_TRIG1_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 4. " SW_TRIG1_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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textline " "
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bitfld.long 0x00 3. "SW_TRIG0_CTRL3 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 2. " SW_TRIG0_CTRL2 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 1. " SW_TRIG0_CTRL1 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0_CTRL0 ,When write 1 to DIfferent bit generates corresponDIng trigger output. {S,C,T,P} 1xxx: high 01xx: low 001x: toggle 0001: pulse" "0,1"
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group ad:0xF04B0384++0x03
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line.long 0x00 "SW_TRIG_STATUS,SW trigger outputs status"
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bitfld.long 0x00 3. " SW_TRIG3 ,SW trigger output" "0,1"
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bitfld.long 0x00 2. " SW_TRIG2 ,SW trigger output" "0,1"
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bitfld.long 0x00 1. " SW_TRIG1 ,SW trigger output" "0,1"
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bitfld.long 0x00 0. " SW_TRIG0 ,SW trigger output" "0,1"
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group ad:0xF04B0388++0x03
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line.long 0x00 "SW_TRIG_PULSE0,SW trigger0 and trigger1 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG1_WIDTH ,Pulse width of SW trigger1"
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hexmask.long.word 0x00 0.--15. 1. " TRIG0_WIDTH ,Pulse width of SW trigger0"
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group ad:0xF04B038C++0x03
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line.long 0x00 "SW_TRIG_PULSE1,SW trigger2 and trigger3 pulse width configuration"
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hexmask.long.word 0x00 16.--31. 1. " TRIG3_WIDTH ,Pulse width of SW trigger3"
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hexmask.long.word 0x00 0.--15. 1. " TRIG2_WIDTH ,Pulse width of SW trigger2"
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group ad:0xF04B0410++0x03
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line.long 0x00 "FAULT0_FLT,Filter setting for fault0 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF04B0414++0x03
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line.long 0x00 "FAULT1_FLT,Filter setting for fault1 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF04B0418++0x03
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line.long 0x00 "FAULT2_FLT,Filter setting for fault2 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF04B041C++0x03
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line.long 0x00 "FAULT3_FLT,Filter setting for fault3 input."
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hexmask.long.byte 0x00 12.--19. 1. " SMPL_INTVAL ,Sampling interval for 1~256 timer clock cycles"
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bitfld.long 0x00 8.--11. " NEG_BAND_WID ,Filter bandwidth for negedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " POS_BAND_WID ,Filter bandwidth for posedge compare channel. 0~15 inDIcate 2~17 sample interval." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " FLT_EDGE_SEL ,Filter edge select 00: Posedge 01: Negedge 10/11: Both edge" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0. "FLT_EN ,When this bit is set, filter is enabled for compare channel." "0,1"
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group ad:0xF04B0420++0x03
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line.long 0x00 "SYNC_DIS,Synchronization DIsable control register"
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bitfld.long 0x00 5. " FAULT3 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 4. " FAULT2 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 3. " FAULT1 ,DIsable synchronization" "0,1"
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bitfld.long 0x00 2. " FAULT0 ,DIsable synchronization" "0,1"
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textline " "
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bitfld.long 0x00 1. "EXT_CLR ,DIsable synchronization" "0,1"
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bitfld.long 0x00 0. " EXT_SET ,DIsable synchronization" "0,1"
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group ad:0xF04B0440++0x03
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line.long 0x00 "CMP_A_FAULT_EVENT_CTRL,Compare A channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
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group ad:0xF04B0444++0x03
|
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line.long 0x00 "CMP_B_FAULT_EVENT_CTRL,Compare B channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
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group ad:0xF04B0448++0x03
|
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line.long 0x00 "CMP_C_FAULT_EVENT_CTRL,Compare C channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
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group ad:0xF04B044C++0x03
|
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line.long 0x00 "CMP_D_FAULT_EVENT_CTRL,Compare D channel event control register"
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bitfld.long 0x00 15. " FAULT3_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 14. " FAULT3_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 13. " FAULT3_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 12. " FAULT3_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
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bitfld.long 0x00 11. "FAULT2_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 10. " FAULT2_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 9. " FAULT2_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 8. " FAULT2_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 7. "FAULT1_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 6. " FAULT1_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 5. " FAULT1_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 4. " FAULT1_EN ,Use to enable input fault sources." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "FAULT0_CLR ,Use to clear fault source in sticky mode." "0,1"
|
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bitfld.long 0x00 2. " FAULT0_CLR_MODE ,The fault event can be configured to two modes: 0: Auto clear mode, in which the fault event is removed until the fault input is de-asserted. Output of the Compare block exits failsafe mode when the fault input is de-.." "0,1"
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bitfld.long 0x00 1. " FAULT0_POL ,define active polarity of input fault sources. 0: active high 1: active low" "0,1"
|
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bitfld.long 0x00 0. " FAULT0_EN ,Use to enable input fault sources." "0,1"
|
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group ad:0xF04B0460++0x03
|
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line.long 0x00 "CMP_A_DTI_CTRL,Dead time insertion control register for compare A channel"
|
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bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
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bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
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bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
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bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
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textline " "
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bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
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bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04B0464++0x03
|
|
line.long 0x00 "CMP_A_DTI_WID,Dead time insertion width register for compare A channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
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hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04B0468++0x03
|
|
line.long 0x00 "CMP_B_DTI_CTRL,Dead time insertion control register for compare B channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04B046C++0x03
|
|
line.long 0x00 "CMP_B_DTI_WID,Dead time insertion width register for compare B channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04B0470++0x03
|
|
line.long 0x00 "CMP_C_DTI_CTRL,Dead time insertion control register for compare C channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04B0474++0x03
|
|
line.long 0x00 "CMP_C_DTI_WID,Dead time insertion width register for compare C channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04B0478++0x03
|
|
line.long 0x00 "CMP_D_DTI_CTRL,Dead time insertion control register for compare D channel"
|
|
bitfld.long 0x00 6. " CMP1_INV_CMP0 ,In this mode, cmp1 is inverted version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 5. " CMP1_SAME_CMP0 ,In this mode, cmp1 is same version of cmp0 and ignores input cmp1." "0,1"
|
|
bitfld.long 0x00 4. " CMP1_FS_STATUS ,force value of cmp1 when fault event happens." "0,1"
|
|
bitfld.long 0x00 3. " CMP0_FS_STATUS ,force value of cmp0 when fault event happens." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "CMP1_POL ,Change polarity of CMP1 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 1. " CMP0_POL ,Change polarity of CMP0 0: No change 1: Invert" "0,1"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time insertion." "0,1"
|
|
group ad:0xF04B047C++0x03
|
|
line.long 0x00 "CMP_D_DTI_WID,Dead time insertion width register for compare D channel"
|
|
hexmask.long.word 0x00 16.--31. 1. " DT1_WID ,Used for set the dead-time between negative edge of CMP0 to positive edge of CMP1."
|
|
hexmask.long.word 0x00 0.--15. 1. " DT0_WID ,Used for set the dead-time between negative edge of CMP1 to positive edge of CMP0"
|
|
group ad:0xF04B0500++0x03
|
|
line.long 0x00 "SIGNAL_STATUS,Signal status register"
|
|
bitfld.long 0x00 15. " CMP_D_CLR ,Compare D clear signal" "0,1"
|
|
bitfld.long 0x00 14. " CMP_D_SET ,Compare D set signal" "0,1"
|
|
bitfld.long 0x00 13. " CMP_C_CLR ,Compare C clear signal" "0,1"
|
|
bitfld.long 0x00 12. " CMP_C_SET ,Compare C set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "CMP_B_CLR ,Compare B clear signal" "0,1"
|
|
bitfld.long 0x00 10. " CMP_B_SET ,Compare B set signal" "0,1"
|
|
bitfld.long 0x00 9. " CMP_A_CLR ,Compare A clear signal" "0,1"
|
|
bitfld.long 0x00 8. " CMP_A_SET ,Compare A set signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "CMP_D1 ,Compare D1 signal" "0,1"
|
|
bitfld.long 0x00 6. " CMP_D0 ,Compare D0 signal" "0,1"
|
|
bitfld.long 0x00 5. " CMP_C1 ,Compare C1 signal" "0,1"
|
|
bitfld.long 0x00 4. " CMP_C0 ,Compare C0 signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "CMP_B1 ,Compare B1 signal" "0,1"
|
|
bitfld.long 0x00 2. " CMP_B0 ,Compare B0 signal" "0,1"
|
|
bitfld.long 0x00 1. " CMP_A1 ,Compare A1 signal" "0,1"
|
|
bitfld.long 0x00 0. " CMP_A0 ,Compare A0 signal" "0,1"
|
|
group ad:0xF04B0FFC++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "ETH"
|
|
tree "ETH1"
|
|
width 28.
|
|
group ad:0xF2012008++0x03
|
|
line.long 0x00 "APB_ERR_INT_SIG_EN,Apb bus error Interrupt signal enable"
|
|
bitfld.long 0x00 5. " PRDATA_PARITY_ERR ,APB read data parity error" "0,1"
|
|
bitfld.long 0x00 4. " PWDATA_FATAL ,Interrupt signal enable for pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 3. " PWDATA_UNCERR ,Interrupt signal enable for pwdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 2. " PWDATA_CORERR ,Interrupt Signal enable for pwdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PCTL_UNCERR ,Interrupt signal enable for apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 0. " PADDR_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF2012010++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF2012014++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF2012018++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF201201C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF2012020++0x03
|
|
line.long 0x00 "INPUT_ERR_INT_STA,Input signals error interrupt status register"
|
|
bitfld.long 0x00 1. " reg_parity_ej_en ,Input reg_parity_ej_en signal error interrupt status" "0,1"
|
|
bitfld.long 0x00 0. " SELFTEST_MODE ,Input selftest_mode signal error interrupt status" "0,1"
|
|
group ad:0xF2012024++0x03
|
|
line.long 0x00 "INPUT_ERR_INT_STA_EN,Input signals error interrupt status enable register"
|
|
bitfld.long 0x00 1. " reg_parity_ej_en ,Input reg_parity_ej_en signal interupt status enable registe" "0,1"
|
|
bitfld.long 0x00 0. " selftest_mode ,Input selftest_mode signal interupt status enable register" "0,1"
|
|
group ad:0xF2012028++0x03
|
|
line.long 0x00 "INPUT_ERR_INT_SIG_EN,Input signals error interrupt signal enable register"
|
|
bitfld.long 0x00 1. " reg_parity_ej_en ,Input reg_parity_ej_en signal interupt status enable registe" "0,1"
|
|
bitfld.long 0x00 0. " selftest_mode ,Input selftest_mode signal interupt status enable register" "0,1"
|
|
group ad:0xF2012030++0x03
|
|
line.long 0x00 "DMA_ERR_INT_STA,DMA error interrupt status register"
|
|
bitfld.long 0x00 29. " DMA3_MULTI_REQ_ERR ,DMA3 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 28. " DMA3_EOBC_ERR ,DMA3 eobc error" "0,1"
|
|
bitfld.long 0x00 27. " DMA3_EOBA_ERR ,DMA3 eoba error" "0,1"
|
|
bitfld.long 0x00 26. " DMA3_BW_FATAL_ERR ,DMA3 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA3_BW_UNC_ERR ,DMA3 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 24. " DMA3_BW_COR_ERR ,DMA3 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 21. " DMA2_MULTI_REQ_ERR ,DMA2 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 20. " DMA2_EOBC_ERR ,DMA2 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "DMA2_EOBA_ERR ,DMA2 eoba error" "0,1"
|
|
bitfld.long 0x00 18. " DMA2_BW_FATAL_ERR ,DMA2 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 17. " DMA2_BW_UNC_ERR ,DMA2 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 16. " DMA2_BW_COR_ERR ,DMA2 backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA1_MULTI_REQ_ERR ,DMA1 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,DMA1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA1_EOBA_ERR ,DMA1 eoba error" "0,1"
|
|
bitfld.long 0x00 10. " DMA1_BW_FATAL_ERR ,DMA1 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "DMA1_BW_UNC_ERR ,DMA1 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_COR_ERR ,DMA1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_MULTI_REQ_ERR ,DMA0 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 4. " DMA0_EOBC_ERR ,DMA0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DMA0_EOBA_ERR ,DMA0 eoba error" "0,1"
|
|
bitfld.long 0x00 2. " DMA0_BW_FATAL_ERR ,DMA0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_UNC_ERR ,DMA0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 0. " DMA0_BW_COR_ERR ,DMA0 backwad channel correctable error." "0,1"
|
|
group ad:0xF2012034++0x03
|
|
line.long 0x00 "DMA_ERR_INT_STA_EN,DMA error interrupt status enable register"
|
|
bitfld.long 0x00 29. " DMA3_MULTI_REQ_ERR ,DMA3 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 28. " DMA3_EOBC_ERR ,DMA3 eobc error" "0,1"
|
|
bitfld.long 0x00 27. " DMA3_EOBA_ERR ,DMA3 eoba error" "0,1"
|
|
bitfld.long 0x00 26. " DMA3_BW_FATAL_ERR ,DMA3 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA3_BW_UNC_ERR ,DMA3 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 24. " DMA3_BW_COR_ERR ,DMA3 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 21. " DMA2_MULTI_REQ_ERR ,DMA2 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 20. " DMA2_EOBC_ERR ,DMA2 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "DMA2_EOBA_ERR ,DMA2 eoba error" "0,1"
|
|
bitfld.long 0x00 18. " DMA2_BW_FATAL_ERR ,DMA2 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 17. " DMA2_BW_UNC_ERR ,DMA2 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 16. " DMA2_BW_COR_ERR ,DMA2 backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA1_MULTI_REQ_ERR ,DMA1 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,DMA1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA1_EOBA_ERR ,DMA1 eoba error" "0,1"
|
|
bitfld.long 0x00 10. " DMA1_BW_FATAL_ERR ,DMA1 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "DMA1_BW_UNC_ERR ,DMA1 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_COR_ERR ,DMA1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_MULTI_REQ_ERR ,DMA0 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 4. " DMA0_EOBC_ERR ,DMA0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DMA0_EOBA_ERR ,DMA0 eoba error" "0,1"
|
|
bitfld.long 0x00 2. " DMA0_BW_FATAL_ERR ,DMA0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_UNC_ERR ,DMA0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 0. " DMA0_BW_COR_ERR ,DMA0 backwad channel correctable error." "0,1"
|
|
group ad:0xF2012038++0x03
|
|
line.long 0x00 "DMA_ERR_INT_SIG_EN,DMA error interrupt signal enable register"
|
|
bitfld.long 0x00 29. " DMA3_MULTI_REQ_ERR ,DMA3 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 28. " DMA3_EOBC_ERR ,DMA3 eobc error" "0,1"
|
|
bitfld.long 0x00 27. " DMA3_EOBA_ERR ,DMA3 eoba error" "0,1"
|
|
bitfld.long 0x00 26. " DMA3_BW_FATAL_ERR ,DMA3 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA3_BW_UNC_ERR ,DMA3 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 24. " DMA3_BW_COR_ERR ,DMA3 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 21. " DMA2_MULTI_REQ_ERR ,DMA2 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 20. " DMA2_EOBC_ERR ,DMA2 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "DMA2_EOBA_ERR ,DMA2 eoba error" "0,1"
|
|
bitfld.long 0x00 18. " DMA2_BW_FATAL_ERR ,DMA2 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 17. " DMA2_BW_UNC_ERR ,DMA2 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 16. " DMA2_BW_COR_ERR ,DMA2 backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA1_MULTI_REQ_ERR ,DMA1 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,DMA1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA1_EOBA_ERR ,DMA1 eoba error" "0,1"
|
|
bitfld.long 0x00 10. " DMA1_BW_FATAL_ERR ,DMA1 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "DMA1_BW_UNC_ERR ,DMA1 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_COR_ERR ,DMA1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_MULTI_REQ_ERR ,DMA0 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 4. " DMA0_EOBC_ERR ,DMA0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DMA0_EOBA_ERR ,DMA0 eoba error" "0,1"
|
|
bitfld.long 0x00 2. " DMA0_BW_FATAL_ERR ,DMA0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_UNC_ERR ,DMA0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 0. " DMA0_BW_COR_ERR ,DMA0 backwad channel correctable error." "0,1"
|
|
group ad:0xF2012040++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb wdata"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Apb wdata error injection on SECDED monitor"
|
|
group ad:0xF2012044++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb wdata ecc"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Apb wecc error injection on SECDEC monitor"
|
|
group ad:0xF2012048++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection register"
|
|
bitfld.long 0x00 16. " PMT_INTR ,Interrupt from PMT" "0,1"
|
|
bitfld.long 0x00 11.--15. " SBD_PERCH_RX_INTR ,Per Channel Receive Interrupt signal to host system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. " SBD_PERCH_TX_INTR ,Per Channel Transmit Interrupt signal to host system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " SBD_SFTY_UE_INTR ,Safety interrupt signal for un-correctable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "SBD_SFTY_CE_INTR ,Safety interrupt signal for correctable error" "0,1"
|
|
bitfld.long 0x00 3. " SBD_INTR ,Susystem Interrupt from one or multiple DMA channels." "0,1"
|
|
bitfld.long 0x00 2. " LPI_INTR ,lPI RX exit interrupt" "0,1"
|
|
bitfld.long 0x00 1. " UNC_ERR ,Uncorrectabel error interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "COR_ERR ,Correctable error interrupt." "0,1"
|
|
group ad:0xF2012050++0x03
|
|
line.long 0x00 "DMA0_ERR_INJ,DMA0 error injection"
|
|
bitfld.long 0x00 12.--15. " BW_CODE_INJ ,DMA backward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " BW_DATA_INJ ,DMA backward channel data error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FW_CODE_INJ ,DMA forward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " FW_DATA_INJ ,DMA forward channel data error injection" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF2012054++0x03
|
|
line.long 0x00 "DMA1_ERR_INJ,DMA1 error injection"
|
|
bitfld.long 0x00 12.--15. " BW_CODE_INJ ,DMA backward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " BW_DATA_INJ ,DMA backward channel data error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FW_CODE_INJ ,DMA forward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " FW_DATA_INJ ,DMA forward channel data error injection" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF2012058++0x03
|
|
line.long 0x00 "DMA2_ERR_INJ,DMA2 error injection"
|
|
bitfld.long 0x00 12.--15. " BW_CODE_INJ ,DMA backward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " BW_DATA_INJ ,DMA backward channel data error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FW_CODE_INJ ,DMA forward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " FW_DATA_INJ ,DMA forward channel data error injection" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF201205C++0x03
|
|
line.long 0x00 "DMA3_ERR_INJ,DMA3 error injection"
|
|
bitfld.long 0x00 12.--15. " BW_CODE_INJ ,DMA backward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " BW_DATA_INJ ,DMA backward channel data error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FW_CODE_INJ ,DMA forward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " FW_DATA_INJ ,DMA forward channel data error injection" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF2012060++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
group ad:0xF2012070++0x03
|
|
line.long 0x00 "PPS_STRETCH_CFG,PPS output stretch configuration."
|
|
hexmask.long.byte 0x00 26.--31. 1. " PPS3_STRETCH_WIDTH ,Stretch PPS output width from 1 clk_ptp_ref_i cycle to 2~65 clk_ptp_ref_i cycles."
|
|
bitfld.long 0x00 25. " PPS3_PULSE_SEL ,Stretch pulse select 0: posedge 1: negedge" "0,1"
|
|
bitfld.long 0x00 24. " PPS3_EN ,PPS output3 strench enable" "0,1"
|
|
hexmask.long.byte 0x00 18.--23. 1. " PPS2_STRETCH_WIDTH ,Stretch PPS output width from 1 clk_ptp_ref_i cycle to 2~65 clk_ptp_ref_i cycles."
|
|
textline " "
|
|
bitfld.long 0x00 17. "PPS2_PULSE_SEL ,Stretch pulse select 0: posedge 1: negedge" "0,1"
|
|
bitfld.long 0x00 16. " PPS2_EN ,PPS output2 strench enable" "0,1"
|
|
hexmask.long.byte 0x00 10.--15. 1. " PPS1_STRETCH_WIDTH ,Stretch PPS output width from 1 clk_ptp_ref_i cycle to 2~65 clk_ptp_ref_i cycles."
|
|
bitfld.long 0x00 9. " PPS1_PULSE_SEL ,Stretch pulse select 0: posedge 1: negedge" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "PPS1_EN ,PPS output1 strench enable" "0,1"
|
|
hexmask.long.byte 0x00 2.--7. 1. " PPS0_STRETCH_WIDTH ,Stretch PPS output width from 1 clk_ptp_ref_i cycle to 2~65 clk_ptp_ref_i cycles."
|
|
bitfld.long 0x00 1. " PPS0_PULSE_SEL ,Stretch pulse select 0: posedge 1: negedge" "0,1"
|
|
bitfld.long 0x00 0. " PPS0_EN ,PPS output0 strench enable" "0,1"
|
|
group ad:0xF2012080++0x03
|
|
line.long 0x00 "PHY_INTF_SEL,PHY interface selection register"
|
|
bitfld.long 0x00 0.--2. " SEL ,Phy selection 3'b000: MII 3'b001: RGMII 3'b100: RMII" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "ETH2"
|
|
width 28.
|
|
group ad:0xF2022008++0x03
|
|
line.long 0x00 "APB_ERR_INT_SIG_EN,Apb bus error Interrupt signal enable"
|
|
bitfld.long 0x00 5. " PRDATA_PARITY_ERR ,APB read data parity error" "0,1"
|
|
bitfld.long 0x00 4. " PWDATA_FATAL ,Interrupt signal enable for pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 3. " PWDATA_UNCERR ,Interrupt signal enable for pwdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 2. " PWDATA_CORERR ,Interrupt Signal enable for pwdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PCTL_UNCERR ,Interrupt signal enable for apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 0. " PADDR_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF2022010++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF2022014++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt status enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status enable" "0,1"
|
|
group ad:0xF2022018++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF202201C++0x03
|
|
line.long 0x00 "PRDATAINJ,Prdata error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ ,Prdata error injection" "0,1"
|
|
group ad:0xF2022020++0x03
|
|
line.long 0x00 "INPUT_ERR_INT_STA,Input signals error interrupt status register"
|
|
bitfld.long 0x00 1. " reg_parity_ej_en ,Input reg_parity_ej_en signal error interrupt status" "0,1"
|
|
bitfld.long 0x00 0. " SELFTEST_MODE ,Input selftest_mode signal error interrupt status" "0,1"
|
|
group ad:0xF2022024++0x03
|
|
line.long 0x00 "INPUT_ERR_INT_STA_EN,Input signals error interrupt status enable register"
|
|
bitfld.long 0x00 1. " reg_parity_ej_en ,Input reg_parity_ej_en signal interupt status enable registe" "0,1"
|
|
bitfld.long 0x00 0. " selftest_mode ,Input selftest_mode signal interupt status enable register" "0,1"
|
|
group ad:0xF2022028++0x03
|
|
line.long 0x00 "INPUT_ERR_INT_SIG_EN,Input signals error interrupt signal enable register"
|
|
bitfld.long 0x00 1. " reg_parity_ej_en ,Input reg_parity_ej_en signal interupt status enable registe" "0,1"
|
|
bitfld.long 0x00 0. " selftest_mode ,Input selftest_mode signal interupt status enable register" "0,1"
|
|
group ad:0xF2022030++0x03
|
|
line.long 0x00 "DMA_ERR_INT_STA,DMA error interrupt status register"
|
|
bitfld.long 0x00 29. " DMA3_MULTI_REQ_ERR ,DMA3 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 28. " DMA3_EOBC_ERR ,DMA3 eobc error" "0,1"
|
|
bitfld.long 0x00 27. " DMA3_EOBA_ERR ,DMA3 eoba error" "0,1"
|
|
bitfld.long 0x00 26. " DMA3_BW_FATAL_ERR ,DMA3 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA3_BW_UNC_ERR ,DMA3 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 24. " DMA3_BW_COR_ERR ,DMA3 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 21. " DMA2_MULTI_REQ_ERR ,DMA2 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 20. " DMA2_EOBC_ERR ,DMA2 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "DMA2_EOBA_ERR ,DMA2 eoba error" "0,1"
|
|
bitfld.long 0x00 18. " DMA2_BW_FATAL_ERR ,DMA2 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 17. " DMA2_BW_UNC_ERR ,DMA2 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 16. " DMA2_BW_COR_ERR ,DMA2 backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA1_MULTI_REQ_ERR ,DMA1 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,DMA1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA1_EOBA_ERR ,DMA1 eoba error" "0,1"
|
|
bitfld.long 0x00 10. " DMA1_BW_FATAL_ERR ,DMA1 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "DMA1_BW_UNC_ERR ,DMA1 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_COR_ERR ,DMA1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_MULTI_REQ_ERR ,DMA0 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 4. " DMA0_EOBC_ERR ,DMA0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DMA0_EOBA_ERR ,DMA0 eoba error" "0,1"
|
|
bitfld.long 0x00 2. " DMA0_BW_FATAL_ERR ,DMA0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_UNC_ERR ,DMA0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 0. " DMA0_BW_COR_ERR ,DMA0 backwad channel correctable error." "0,1"
|
|
group ad:0xF2022034++0x03
|
|
line.long 0x00 "DMA_ERR_INT_STA_EN,DMA error interrupt status enable register"
|
|
bitfld.long 0x00 29. " DMA3_MULTI_REQ_ERR ,DMA3 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 28. " DMA3_EOBC_ERR ,DMA3 eobc error" "0,1"
|
|
bitfld.long 0x00 27. " DMA3_EOBA_ERR ,DMA3 eoba error" "0,1"
|
|
bitfld.long 0x00 26. " DMA3_BW_FATAL_ERR ,DMA3 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA3_BW_UNC_ERR ,DMA3 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 24. " DMA3_BW_COR_ERR ,DMA3 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 21. " DMA2_MULTI_REQ_ERR ,DMA2 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 20. " DMA2_EOBC_ERR ,DMA2 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "DMA2_EOBA_ERR ,DMA2 eoba error" "0,1"
|
|
bitfld.long 0x00 18. " DMA2_BW_FATAL_ERR ,DMA2 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 17. " DMA2_BW_UNC_ERR ,DMA2 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 16. " DMA2_BW_COR_ERR ,DMA2 backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA1_MULTI_REQ_ERR ,DMA1 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,DMA1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA1_EOBA_ERR ,DMA1 eoba error" "0,1"
|
|
bitfld.long 0x00 10. " DMA1_BW_FATAL_ERR ,DMA1 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "DMA1_BW_UNC_ERR ,DMA1 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_COR_ERR ,DMA1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_MULTI_REQ_ERR ,DMA0 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 4. " DMA0_EOBC_ERR ,DMA0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DMA0_EOBA_ERR ,DMA0 eoba error" "0,1"
|
|
bitfld.long 0x00 2. " DMA0_BW_FATAL_ERR ,DMA0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_UNC_ERR ,DMA0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 0. " DMA0_BW_COR_ERR ,DMA0 backwad channel correctable error." "0,1"
|
|
group ad:0xF2022038++0x03
|
|
line.long 0x00 "DMA_ERR_INT_SIG_EN,DMA error interrupt signal enable register"
|
|
bitfld.long 0x00 29. " DMA3_MULTI_REQ_ERR ,DMA3 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 28. " DMA3_EOBC_ERR ,DMA3 eobc error" "0,1"
|
|
bitfld.long 0x00 27. " DMA3_EOBA_ERR ,DMA3 eoba error" "0,1"
|
|
bitfld.long 0x00 26. " DMA3_BW_FATAL_ERR ,DMA3 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. "DMA3_BW_UNC_ERR ,DMA3 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 24. " DMA3_BW_COR_ERR ,DMA3 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 21. " DMA2_MULTI_REQ_ERR ,DMA2 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 20. " DMA2_EOBC_ERR ,DMA2 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "DMA2_EOBA_ERR ,DMA2 eoba error" "0,1"
|
|
bitfld.long 0x00 18. " DMA2_BW_FATAL_ERR ,DMA2 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 17. " DMA2_BW_UNC_ERR ,DMA2 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 16. " DMA2_BW_COR_ERR ,DMA2 backwad channel correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. "DMA1_MULTI_REQ_ERR ,DMA1 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 12. " DMA1_EOBC_ERR ,DMA1 eobc error" "0,1"
|
|
bitfld.long 0x00 11. " DMA1_EOBA_ERR ,DMA1 eoba error" "0,1"
|
|
bitfld.long 0x00 10. " DMA1_BW_FATAL_ERR ,DMA1 backwad channel fatal error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "DMA1_BW_UNC_ERR ,DMA1 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 8. " DMA1_BW_COR_ERR ,DMA1 backwad channel correctable error." "0,1"
|
|
bitfld.long 0x00 5. " DMA0_MULTI_REQ_ERR ,DMA0 multiple dma request error" "0,1"
|
|
bitfld.long 0x00 4. " DMA0_EOBC_ERR ,DMA0 eobc error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DMA0_EOBA_ERR ,DMA0 eoba error" "0,1"
|
|
bitfld.long 0x00 2. " DMA0_BW_FATAL_ERR ,DMA0 backwad channel fatal error." "0,1"
|
|
bitfld.long 0x00 1. " DMA0_BW_UNC_ERR ,DMA0 backwad channel uncorrectable error." "0,1"
|
|
bitfld.long 0x00 0. " DMA0_BW_COR_ERR ,DMA0 backwad channel correctable error." "0,1"
|
|
group ad:0xF2022040++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb wdata"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Apb wdata error injection on SECDED monitor"
|
|
group ad:0xF2022044++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb wdata ecc"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Apb wecc error injection on SECDEC monitor"
|
|
group ad:0xF2022048++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection register"
|
|
bitfld.long 0x00 16. " PMT_INTR ,Interrupt from PMT" "0,1"
|
|
bitfld.long 0x00 11.--15. " SBD_PERCH_RX_INTR ,Per Channel Receive Interrupt signal to host system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. " SBD_PERCH_TX_INTR ,Per Channel Transmit Interrupt signal to host system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " SBD_SFTY_UE_INTR ,Safety interrupt signal for un-correctable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "SBD_SFTY_CE_INTR ,Safety interrupt signal for correctable error" "0,1"
|
|
bitfld.long 0x00 3. " SBD_INTR ,Susystem Interrupt from one or multiple DMA channels." "0,1"
|
|
bitfld.long 0x00 2. " LPI_INTR ,lPI RX exit interrupt" "0,1"
|
|
bitfld.long 0x00 1. " UNC_ERR ,Uncorrectabel error interrupt" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "COR_ERR ,Correctable error interrupt." "0,1"
|
|
group ad:0xF2022050++0x03
|
|
line.long 0x00 "DMA0_ERR_INJ,DMA0 error injection"
|
|
bitfld.long 0x00 12.--15. " BW_CODE_INJ ,DMA backward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " BW_DATA_INJ ,DMA backward channel data error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FW_CODE_INJ ,DMA forward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " FW_DATA_INJ ,DMA forward channel data error injection" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF2022054++0x03
|
|
line.long 0x00 "DMA1_ERR_INJ,DMA1 error injection"
|
|
bitfld.long 0x00 12.--15. " BW_CODE_INJ ,DMA backward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " BW_DATA_INJ ,DMA backward channel data error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FW_CODE_INJ ,DMA forward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " FW_DATA_INJ ,DMA forward channel data error injection" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF2022058++0x03
|
|
line.long 0x00 "DMA2_ERR_INJ,DMA2 error injection"
|
|
bitfld.long 0x00 12.--15. " BW_CODE_INJ ,DMA backward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " BW_DATA_INJ ,DMA backward channel data error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FW_CODE_INJ ,DMA forward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " FW_DATA_INJ ,DMA forward channel data error injection" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF202205C++0x03
|
|
line.long 0x00 "DMA3_ERR_INJ,DMA3 error injection"
|
|
bitfld.long 0x00 12.--15. " BW_CODE_INJ ,DMA backward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " BW_DATA_INJ ,DMA backward channel data error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FW_CODE_INJ ,DMA forward channel code error injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " FW_DATA_INJ ,DMA forward channel data error injection" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF2022060++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Enable all the error injection function"
|
|
bitfld.long 0x00 0. " EN ,Self test mode enable" "0,1"
|
|
group ad:0xF2022070++0x03
|
|
line.long 0x00 "PPS_STRETCH_CFG,PPS output stretch configuration."
|
|
hexmask.long.byte 0x00 26.--31. 1. " PPS3_STRETCH_WIDTH ,Stretch PPS output width from 1 clk_ptp_ref_i cycle to 2~65 clk_ptp_ref_i cycles."
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|
bitfld.long 0x00 25. " PPS3_PULSE_SEL ,Stretch pulse select 0: posedge 1: negedge" "0,1"
|
|
bitfld.long 0x00 24. " PPS3_EN ,PPS output3 strench enable" "0,1"
|
|
hexmask.long.byte 0x00 18.--23. 1. " PPS2_STRETCH_WIDTH ,Stretch PPS output width from 1 clk_ptp_ref_i cycle to 2~65 clk_ptp_ref_i cycles."
|
|
textline " "
|
|
bitfld.long 0x00 17. "PPS2_PULSE_SEL ,Stretch pulse select 0: posedge 1: negedge" "0,1"
|
|
bitfld.long 0x00 16. " PPS2_EN ,PPS output2 strench enable" "0,1"
|
|
hexmask.long.byte 0x00 10.--15. 1. " PPS1_STRETCH_WIDTH ,Stretch PPS output width from 1 clk_ptp_ref_i cycle to 2~65 clk_ptp_ref_i cycles."
|
|
bitfld.long 0x00 9. " PPS1_PULSE_SEL ,Stretch pulse select 0: posedge 1: negedge" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "PPS1_EN ,PPS output1 strench enable" "0,1"
|
|
hexmask.long.byte 0x00 2.--7. 1. " PPS0_STRETCH_WIDTH ,Stretch PPS output width from 1 clk_ptp_ref_i cycle to 2~65 clk_ptp_ref_i cycles."
|
|
bitfld.long 0x00 1. " PPS0_PULSE_SEL ,Stretch pulse select 0: posedge 1: negedge" "0,1"
|
|
bitfld.long 0x00 0. " PPS0_EN ,PPS output0 strench enable" "0,1"
|
|
group ad:0xF2022080++0x03
|
|
line.long 0x00 "PHY_INTF_SEL,PHY interface selection register"
|
|
bitfld.long 0x00 0.--2. " SEL ,Phy selection 3'b000: MII 3'b001: RGMII 3'b100: RMII" "0,1,2,3,4,5,6,7"
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|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "FUSE"
|
|
width 21.
|
|
group ad:0xF05F0000++0x03
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|
line.long 0x00 "FUSE_CTRL,Fuse program and read control register"
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|
hexmask.long.word 0x00 16.--31. 1. " PROG_KEY ,Write special key to enable fuse program operation."
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|
bitfld.long 0x00 12. " RED_COR ,InDIcate redundancy correction result in reset load or SW load. 0: uncorrect. 1: corrected. 0: uncorrect. 1: corrected." "0,1"
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|
bitfld.long 0x00 11. " ERROR ,Error status bits." "0,1"
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|
bitfld.long 0x00 10. " BUSY ,Busy status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "PECCFG ,InDIcate ECC correction result. 0: uncorrect. 1: corrected." "0,1"
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|
bitfld.long 0x00 8. " PECCB ,ECC function enable for fuse programming and reaDIng(low active)." "0,1"
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|
hexmask.long.byte 0x00 0.--7. 1. " ADDR ,Fuse program and read access address register. In normal program and read, ADDR[7:0] is used to select one of 256 fuse words. In test program/read row mode, A[3:0] is used to select which bit is programmed in selected test row. In.."
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|
group ad:0xF05F0004++0x03
|
|
line.long 0x00 "PROG_DATA,Programming data."
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,fuse program data"
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|
group ad:0xF05F0008++0x03
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|
line.long 0x00 "FUSE_TRIG,It is in conjuction with FUSE_CTRL and FUSE_DATA register to initial fuse operation."
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|
bitfld.long 0x00 6. " BURST_RD ,Used to initiate fuse read to fuse macro. When fuse read is completed, do not assert IP enable immeDIatelly." "0,1"
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|
bitfld.long 0x00 5. " REPAIR_PROGRAM ,repair program. Need set PTM to 4;h2 together." "0,1"
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|
bitfld.long 0x00 4. " REPAIR_CHECK ,Repair check. Need set PTM to 4'h4 together." "0,1"
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|
bitfld.long 0x00 3. " REPAIR_MARGIN_READ ,Repair margin read. Need set PTM to 4'h1 together." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "LOAD ,reload fuse into shadow registers." "0,1"
|
|
bitfld.long 0x00 1. " PROG ,Used to initiate fuse read to fuse macro" "0,1"
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|
bitfld.long 0x00 0. " READ ,Used to initiate fuse read to fuse macro" "0,1"
|
|
group ad:0xF05F000C++0x03
|
|
line.long 0x00 "READ_FUSE_DATA,The fuse data read from fuse macro."
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,The fuse data read from fuse macro."
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|
group ad:0xF05F0010++0x03
|
|
line.long 0x00 "FUSE_TEST_CFG,Fuse test mode configuration"
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|
bitfld.long 0x00 5. " PTC ,Test column enable" "0,1"
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|
bitfld.long 0x00 4. " PTR ,Test row enable" "0,1"
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|
bitfld.long 0x00 0.--3. " PTM ,Test mode enabling. Will be clear to 0 after fuse operation is completed. 0000: read mode 0010: program mode 0001: room temp initial margin read 1001: high temp initial margin read 0100: room temp PGM margin read 1100: high temp .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group ad:0xF05F0020++0x03
|
|
line.long 0x00 "FUSE_PWR_UP_TIMING,Fuse power up timing configuration register"
|
|
hexmask.long.word 0x00 20.--29. 1. " TSAS_CNT ,Deep standy to active mode setup mode"
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|
hexmask.long.word 0x00 8.--19. 1. " TPLS_CNT ,LDO setup time. Minimum 10us"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TPENS_CNT ,Power enable setup time. Minimum 1us"
|
|
group ad:0xF05F0024++0x03
|
|
line.long 0x00 "FUSE_STB_TIMING,Fuse standby timing configuration register"
|
|
hexmask.long 0x00 0.--31. 1. " TSTB_CNT ,10ms."
|
|
group ad:0xF05F0028++0x03
|
|
line.long 0x00 "FUSE_IPEN_RD_TIMING,Fuse IPEN and read timing configuration register"
|
|
hexmask.long.word 0x00 22.--31. 1. " TIPEN_CNT ,IP enable exit time in burst read."
|
|
bitfld.long 0x00 20.--21. " TASH_CNT ,Active mode to Deep standy hold time" "0,1,2,3"
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|
bitfld.long 0x00 18.--19. " TASP_CNT ,Program address setup time." "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TAS_CNT ,Address setup time." "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. "TCS_CNT ,IP enable time"
|
|
bitfld.long 0x00 0.--3. " TRD_CNT ,Read clock cycle time. Mininum 50ns." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group ad:0xF05F002C++0x03
|
|
line.long 0x00 "FUSE_PG_TIMING,Fuse program timing configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TPWI_CNT ,Progam pulse interval time."
|
|
hexmask.long.word 0x00 13.--23. 1. " TPM_CNT ,Program mode setup, hold, recovery timing. Minimum 5us."
|
|
hexmask.long.word 0x00 0.--12. 1. " TPW_CNT ,Program width time"
|
|
group ad:0xF05F0030++0x03
|
|
line.long 0x00 "FUSE_REPAIR_TIMING,Fuse repaire timing configuration register"
|
|
bitfld.long 0x00 14.--15. " TTAH_CNT ,Repair mode hold time" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " TTAS_CNT ,Repair mode setup time"
|
|
group ad:0xF05F0038++0x03
|
|
line.long 0x00 "HUK_READY,HUK key status register"
|
|
bitfld.long 0x00 0. " READY ,InDIcate huk key is ready." "0,1"
|
|
group ad:0xF05F0080++0x03
|
|
line.long 0x00 "FUSA_ERR_INT_STA,Function safety interrupt status register"
|
|
bitfld.long 0x00 11. " REG_ECC_UNC_ERR ,Shadow register ECC uncorrectable error." "0,1"
|
|
bitfld.long 0x00 10. " REG_ECC_COR_ERR ,Shadow register ECC correctable error." "0,1"
|
|
bitfld.long 0x00 9. " MEM_ECC_UNC_ERR ,Memory ECC uncorrectable error." "0,1"
|
|
bitfld.long 0x00 8. " MEM_ECC_COR_ERR ,Memory ECC correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "LSP_HW_FUSE_CMP_ERR ,Lockstep hw fuse compare error" "0,1"
|
|
bitfld.long 0x00 6. " LSP_CMP_ERR ,Lockstep compare error" "0,1"
|
|
bitfld.long 0x00 5. " INPUT_ERR ,Input signal error 1. selftest_mode 2.self_des_mode 3. violation[14:0]" "0,1"
|
|
bitfld.long 0x00 4. " PUSER_UNC_ERR ,Puser parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PCTL_UNC_ERR ,Apb control siganls(pwrite, psel ,penable and pstrb) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF05F0084++0x03
|
|
line.long 0x00 "FUSA_ERR_INT_STA_EN,Function safety interrupt status enable register"
|
|
bitfld.long 0x00 11. " REG_ECC_UNC_ERR ,Shadow register ECC uncorrectable error" "0,1"
|
|
bitfld.long 0x00 10. " REG_ECC_COR_ERR ,Shadow register ECC correctable error" "0,1"
|
|
bitfld.long 0x00 9. " MEM_ECC_UNC_ERR ,Memory ECC uncorrectable error" "0,1"
|
|
bitfld.long 0x00 8. " MEM_ECC_COR_ERR ,Memory ECC correctable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "LSP_HW_FUSE_CMP_ERR ,lockstep HW fuse compare error" "0,1"
|
|
bitfld.long 0x00 6. " LSP_CMP_ERR ,lockstep compare error" "0,1"
|
|
bitfld.long 0x00 5. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 4. " PUSER_UNC_ERR ,Puser parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PCTL_UNC_ERR ,Apb control siganls(pwrite, psel ,penable and pstrb) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF05F0088++0x03
|
|
line.long 0x00 "FUSA_ERR_INT_SIG_EN,Function safety interrupt signal enable register"
|
|
bitfld.long 0x00 11. " REG_ECC_UNC_ERR ,Shaow register ECC uncorrectable error" "0,1"
|
|
bitfld.long 0x00 10. " REG_ECC_COR_ERR ,Shadow register ECC correctable error" "0,1"
|
|
bitfld.long 0x00 9. " MEM_ECC_UNC_ERR ,Memory ECC uncorrectable error" "0,1"
|
|
bitfld.long 0x00 8. " MEM_ECC_COR_ERR ,Memory ECC correctable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "LSP_HW_FUSE_CMP_ERR ,Lockstep HW fuse compare error" "0,1"
|
|
bitfld.long 0x00 6. " LSP_CMP_ERR ,Lockstep compare error" "0,1"
|
|
bitfld.long 0x00 5. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 4. " PUSER_UNC_ERR ,Puser parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "PCTL_UNC_ERR ,Apb control siganls(pwrite, psel ,penable and pstrb) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
bitfld.long 0x00 1. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF05F00A0++0x03
|
|
line.long 0x00 "ERR_INJ,Error injection"
|
|
bitfld.long 0x00 5. " FUSE_READY ,Error injection on fuse_ready" "0,1"
|
|
bitfld.long 0x00 4. " FUSE_LATCHED_PARTIAL ,Error injection on fuse_latched_partial" "0,1"
|
|
bitfld.long 0x00 2.--3. " VIO_O ,Error injection on violation output." "0,1,2,3"
|
|
bitfld.long 0x00 1. " UNCERR ,Uncorrectable error irq error injection." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CORERR ,Correctable error irq error injection." "0,1"
|
|
group ad:0xF05F00A4++0x03
|
|
line.long 0x00 "FUSE_OUTPUT_ERR_INJ,Fuse output error injection register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ERR_INJ_BITS ,Error injection bits selection"
|
|
bitfld.long 0x00 0.--4. " ERR_INJ_SEL ,Error injection selection for fuse output bus 5'h0: DIsable 5;h1: huk_xspi 5'h2: pvk0_xspi 5'h3: pvk1_xspi 5'h4: pvk2_xspi 5'h5: pvk3_xspi 5'h6: huk_rs_xspi 5'h7: manu_cfg 5'h8: devide_id 5'h9: mem_ana 5'ha: sec_dbg_cfg 5'.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF05F00A8++0x03
|
|
line.long 0x00 "LSP_CMP_INJ,Lockstep compare error injection register"
|
|
hexmask.long.word 0x00 2.--12. 1. " ERR_INJ_BIT ,Bit location for bit flip to generate lockstep compare error injection."
|
|
bitfld.long 0x00 1. " ERR_INJ_SEL ,Error injection objection selection. 0: Fuse output to xspi and fuse_ctrl output 1: Static fuse output to other module except xspi." "0,1"
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,lockstep compare error injection enable" "0,1"
|
|
group ad:0xF05F00C0++0x03
|
|
line.long 0x00 "MEM_RDATA_ERR_INJ,Memory rdata error injection."
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,Error injection"
|
|
group ad:0xF05F00C4++0x03
|
|
line.long 0x00 "MEM_RECC_ERR_INJ,Memory recc error injection."
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,Error injection"
|
|
group ad:0xF05F00C8++0x03
|
|
line.long 0x00 "MEM_ERR_ADDR,Memory error address"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ERR_ADDR ,Error address,"
|
|
group ad:0xF05F0100++0x03
|
|
line.long 0x00 "GLB_LOCK,Global setting for bank lock. Sticky register."
|
|
bitfld.long 0x00 0. " LOCK ,Lock lock register bits" "0,1"
|
|
group ad:0xF05F0104++0x03
|
|
line.long 0x00 "BANK_LOCK0,Bank1~8 lock bit."
|
|
bitfld.long 0x00 31. " HLOCK8 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 30. " OLOCK8 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 29. " RLOCK8 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 28. " PLOCK8 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HLOCK7 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 26. " OLOCK7 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 25. " RLOCK7 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 24. " PLOCK7 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "HLOCK6 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 22. " OLOCK6 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 21. " RLOCK6 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 20. " PLOCK6 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "HLOCK5 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 18. " OLOCK5 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 17. " RLOCK5 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 16. " PLOCK5 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "HLOCK4 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 14. " OLOCK4 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 13. " RLOCK4 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 12. " PLOCK4 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "HLOCK3 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 10. " OLOCK3 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 9. " RLOCK3 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 8. " PLOCK3 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "HLOCK2 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 6. " OLOCK2 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 5. " RLOCK2 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 4. " PLOCK2 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "HLOCK1 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 2. " OLOCK1 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 1. " RLOCK1 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 0. " PLOCK1 ,Lock for program fuse." "0,1"
|
|
group ad:0xF05F0108++0x03
|
|
line.long 0x00 "BANK_LOCK1,Bank9~16 lock bit."
|
|
bitfld.long 0x00 31. " HLOCK16 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 30. " OLOCK16 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 29. " RLOCK16 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 28. " PLOCK16 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HLOCK15 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 26. " OLOCK15 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 25. " RLOCK15 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 24. " PLOCK15 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "HLOCK14 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 22. " OLOCK14 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 21. " RLOCK14 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 20. " PLOCK14 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "HLOCK13 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 18. " OLOCK13 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 17. " RLOCK13 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 16. " PLOCK13 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "HLOCK12 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 14. " OLOCK12 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 13. " RLOCK12 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 12. " PLOCK12 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "HLOCK11 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 10. " OLOCK11 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 9. " RLOCK11 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 8. " PLOCK11 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "HLOCK10 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 6. " OLOCK10 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 5. " RLOCK10 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 4. " PLOCK10 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "HLOCK9 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 2. " OLOCK9 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 1. " RLOCK9 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 0. " PLOCK9 ,Lock for program fuse." "0,1"
|
|
group ad:0xF05F010C++0x03
|
|
line.long 0x00 "BANK_LOCK2,Bank17~24 lock bit."
|
|
bitfld.long 0x00 31. " HLOCK24 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 30. " OLOCK24 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 29. " RLOCK24 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 28. " PLOCK24 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HLOCK23 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 26. " OLOCK23 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 25. " RLOCK23 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 24. " PLOCK23 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "HLOCK22 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 22. " OLOCK22 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 21. " RLOCK22 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 20. " PLOCK22 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "HLOCK21 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 18. " OLOCK21 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 17. " RLOCK21 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 16. " PLOCK21 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "HLOCK20 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 14. " OLOCK20 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 13. " RLOCK20 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 12. " PLOCK20 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "HLOCK19 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 10. " OLOCK19 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 9. " RLOCK19 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 8. " PLOCK19 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "HLOCK18 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 6. " OLOCK18 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 5. " RLOCK18 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 4. " PLOCK18 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "HLOCK17 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 2. " OLOCK17 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 1. " RLOCK17 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 0. " PLOCK17 ,Lock for program fuse." "0,1"
|
|
group ad:0xF05F0110++0x03
|
|
line.long 0x00 "BANK_LOCK3,Bank25~32 lock bit."
|
|
bitfld.long 0x00 31. " HLOCK32 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 30. " OLOCK32 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 29. " RLOCK32 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 28. " PLOCK32 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "HLOCK31 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 26. " OLOCK31 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 25. " RLOCK31 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 24. " PLOCK31 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "HLOCK30 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 22. " OLOCK30 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 21. " RLOCK30 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 20. " PLOCK30 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "HLOCK29 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 18. " OLOCK29 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 17. " RLOCK29 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 16. " PLOCK29 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "HLOCK28 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 14. " OLOCK28 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 13. " RLOCK28 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 12. " PLOCK28 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "HLOCK27 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 10. " OLOCK27 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 9. " RLOCK27 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 8. " PLOCK27 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "HLOCK26 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 6. " OLOCK26 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 5. " RLOCK26 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 4. " PLOCK26 ,Lock for program fuse." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "HLOCK25 ,Lock for HW key bus." "0,1"
|
|
bitfld.long 0x00 2. " OLOCK25 ,Lock for write shadow registers." "0,1"
|
|
bitfld.long 0x00 1. " RLOCK25 ,Lock for read fuse and shadow register." "0,1"
|
|
bitfld.long 0x00 0. " PLOCK25 ,Lock for program fuse." "0,1"
|
|
group ad:0xF05F0140++0x03
|
|
line.long 0x00 "SW_STICKY,SW sticky register"
|
|
bitfld.long 0x00 31. " BIT31 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 30. " BIT30 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 29. " BIT29 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 28. " BIT28 ,SW sticky bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "BIT27 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 26. " BIT26 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 25. " BIT25 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 24. " BIT24 ,SW sticky bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "BIT23 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 22. " BIT22 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 21. " BIT21 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 20. " BIT20 ,SW sticky bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "BIT19 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 18. " BIT18 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 17. " BIT17 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 16. " BIT16 ,SW sticky bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "BIT15 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 14. " BIT14 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 13. " BIT13 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 12. " BIT12 ,SW sticky bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "BIT11 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 10. " BIT10 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 9. " BIT9 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 8. " BIT8 ,SW sticky bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "BIT7 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 6. " BIT6 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 5. " BIT5 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 4. " BIT4 ,SW sticky bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "BIT3 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 2. " BIT2 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 1. " BIT1 ,SW sticky bit" "0,1"
|
|
bitfld.long 0x00 0. " BIT0 ,SW sticky bit" "0,1"
|
|
group ad:0xF05F0200++0x03
|
|
line.long 0x00 "VIO0_CFG,Violation0 configure register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock VIO_EN register bits." "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " VIO_POL ,HW violation polarity 0: postive 1: negative"
|
|
hexmask.long.word 0x00 0.--15. 1. " VIO_EN ,Violation source enable"
|
|
group ad:0xF05F0204++0x03
|
|
line.long 0x00 "VIO1_CFG,Violation1 configure register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock VIO_EN register bits." "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " VIO_POL ,HW violation polarity 0: postive 1: negative"
|
|
hexmask.long.word 0x00 0.--15. 1. " VIO_EN ,Violation source enable"
|
|
group ad:0xF05F0208++0x03
|
|
line.long 0x00 "SW_TRIG_VIO,Software trigger violation"
|
|
bitfld.long 0x00 0.--1. " SW_TRIG ,Software trigger violation" "0,1,2,3"
|
|
group ad:0xF05F1000++0x03
|
|
line.long 0x00 "LOCK_FUSE_0,Shadow register for lock fuse word"
|
|
hexmask.long 0x00 0.--31. 1. " LOCK ,Shadow register for lock fuse word"
|
|
group ad:0xF05F1004++0x03
|
|
line.long 0x00 "LOCK_FUSE_1,Shadow register for lock fuse word"
|
|
hexmask.long 0x00 0.--31. 1. " LOCK ,Shadow register for lock fuse word"
|
|
group ad:0xF05F1008++0x03
|
|
line.long 0x00 "LOCK_FUSE_2,Shadow register for lock fuse word"
|
|
hexmask.long 0x00 0.--31. 1. " LOCK ,Shadow register for lock fuse word"
|
|
group ad:0xF05F100C++0x03
|
|
line.long 0x00 "LOCK_FUSE_3,Shadow register for lock fuse word"
|
|
hexmask.long 0x00 0.--31. 1. " LOCK ,Shadow register for lock fuse word"
|
|
group ad:0xF05F1010++0x03
|
|
line.long 0x00 "SHA_REG0_0,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1014++0x03
|
|
line.long 0x00 "SHA_REG0_1,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1018++0x03
|
|
line.long 0x00 "SHA_REG0_2,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F101C++0x03
|
|
line.long 0x00 "SHA_REG0_3,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1020++0x03
|
|
line.long 0x00 "SHA_REG0_4,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1024++0x03
|
|
line.long 0x00 "SHA_REG0_5,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1028++0x03
|
|
line.long 0x00 "SHA_REG0_6,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F102C++0x03
|
|
line.long 0x00 "SHA_REG0_7,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1030++0x03
|
|
line.long 0x00 "SHA_REG0_8,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1034++0x03
|
|
line.long 0x00 "SHA_REG0_9,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1038++0x03
|
|
line.long 0x00 "SHA_REG0_10,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F103C++0x03
|
|
line.long 0x00 "SHA_REG0_11,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1040++0x03
|
|
line.long 0x00 "SHA_REG0_12,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1044++0x03
|
|
line.long 0x00 "SHA_REG0_13,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1048++0x03
|
|
line.long 0x00 "SHA_REG0_14,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F104C++0x03
|
|
line.long 0x00 "SHA_REG0_15,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1050++0x03
|
|
line.long 0x00 "SHA_REG0_16,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1054++0x03
|
|
line.long 0x00 "SHA_REG0_17,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1058++0x03
|
|
line.long 0x00 "SHA_REG0_18,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F105C++0x03
|
|
line.long 0x00 "SHA_REG0_19,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1060++0x03
|
|
line.long 0x00 "SHA_REG0_20,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1064++0x03
|
|
line.long 0x00 "SHA_REG0_21,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1068++0x03
|
|
line.long 0x00 "SHA_REG0_22,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F106C++0x03
|
|
line.long 0x00 "SHA_REG0_23,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1070++0x03
|
|
line.long 0x00 "SHA_REG0_24,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1074++0x03
|
|
line.long 0x00 "SHA_REG0_25,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1078++0x03
|
|
line.long 0x00 "SHA_REG0_26,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F107C++0x03
|
|
line.long 0x00 "SHA_REG0_27,Shadow register for fuse word4~31"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1080++0x03
|
|
line.long 0x00 "SHA_MEM0_0,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1084++0x03
|
|
line.long 0x00 "SHA_MEM0_1,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1088++0x03
|
|
line.long 0x00 "SHA_MEM0_2,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F108C++0x03
|
|
line.long 0x00 "SHA_MEM0_3,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1090++0x03
|
|
line.long 0x00 "SHA_MEM0_4,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1094++0x03
|
|
line.long 0x00 "SHA_MEM0_5,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1098++0x03
|
|
line.long 0x00 "SHA_MEM0_6,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F109C++0x03
|
|
line.long 0x00 "SHA_MEM0_7,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10A0++0x03
|
|
line.long 0x00 "SHA_MEM0_8,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10A4++0x03
|
|
line.long 0x00 "SHA_MEM0_9,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10A8++0x03
|
|
line.long 0x00 "SHA_MEM0_10,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10AC++0x03
|
|
line.long 0x00 "SHA_MEM0_11,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10B0++0x03
|
|
line.long 0x00 "SHA_MEM0_12,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10B4++0x03
|
|
line.long 0x00 "SHA_MEM0_13,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10B8++0x03
|
|
line.long 0x00 "SHA_MEM0_14,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10BC++0x03
|
|
line.long 0x00 "SHA_MEM0_15,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10C0++0x03
|
|
line.long 0x00 "SHA_MEM0_16,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10C4++0x03
|
|
line.long 0x00 "SHA_MEM0_17,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10C8++0x03
|
|
line.long 0x00 "SHA_MEM0_18,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10CC++0x03
|
|
line.long 0x00 "SHA_MEM0_19,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10D0++0x03
|
|
line.long 0x00 "SHA_MEM0_20,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10D4++0x03
|
|
line.long 0x00 "SHA_MEM0_21,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10D8++0x03
|
|
line.long 0x00 "SHA_MEM0_22,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10DC++0x03
|
|
line.long 0x00 "SHA_MEM0_23,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10E0++0x03
|
|
line.long 0x00 "SHA_MEM0_24,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10E4++0x03
|
|
line.long 0x00 "SHA_MEM0_25,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10E8++0x03
|
|
line.long 0x00 "SHA_MEM0_26,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10EC++0x03
|
|
line.long 0x00 "SHA_MEM0_27,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10F0++0x03
|
|
line.long 0x00 "SHA_MEM0_28,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10F4++0x03
|
|
line.long 0x00 "SHA_MEM0_29,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10F8++0x03
|
|
line.long 0x00 "SHA_MEM0_30,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F10FC++0x03
|
|
line.long 0x00 "SHA_MEM0_31,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1100++0x03
|
|
line.long 0x00 "SHA_MEM0_32,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1104++0x03
|
|
line.long 0x00 "SHA_MEM0_33,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1108++0x03
|
|
line.long 0x00 "SHA_MEM0_34,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F110C++0x03
|
|
line.long 0x00 "SHA_MEM0_35,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1110++0x03
|
|
line.long 0x00 "SHA_MEM0_36,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1114++0x03
|
|
line.long 0x00 "SHA_MEM0_37,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1118++0x03
|
|
line.long 0x00 "SHA_MEM0_38,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F111C++0x03
|
|
line.long 0x00 "SHA_MEM0_39,Shadow memory for fuse word32~71"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1120++0x03
|
|
line.long 0x00 "SHA_REG1_0,Shadow register for fuse word72~79"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1124++0x03
|
|
line.long 0x00 "SHA_REG1_1,Shadow register for fuse word72~79"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1128++0x03
|
|
line.long 0x00 "SHA_REG1_2,Shadow register for fuse word72~79"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F112C++0x03
|
|
line.long 0x00 "SHA_REG1_3,Shadow register for fuse word72~79"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1130++0x03
|
|
line.long 0x00 "SHA_REG1_4,Shadow register for fuse word72~79"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1134++0x03
|
|
line.long 0x00 "SHA_REG1_5,Shadow register for fuse word72~79"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1138++0x03
|
|
line.long 0x00 "SHA_REG1_6,Shadow register for fuse word72~79"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F113C++0x03
|
|
line.long 0x00 "SHA_REG1_7,Shadow register for fuse word72~79"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1140++0x03
|
|
line.long 0x00 "SHA_MEM1_0,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1144++0x03
|
|
line.long 0x00 "SHA_MEM1_1,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1148++0x03
|
|
line.long 0x00 "SHA_MEM1_2,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F114C++0x03
|
|
line.long 0x00 "SHA_MEM1_3,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1150++0x03
|
|
line.long 0x00 "SHA_MEM1_4,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1154++0x03
|
|
line.long 0x00 "SHA_MEM1_5,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1158++0x03
|
|
line.long 0x00 "SHA_MEM1_6,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F115C++0x03
|
|
line.long 0x00 "SHA_MEM1_7,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1160++0x03
|
|
line.long 0x00 "SHA_MEM1_8,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1164++0x03
|
|
line.long 0x00 "SHA_MEM1_9,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1168++0x03
|
|
line.long 0x00 "SHA_MEM1_10,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F116C++0x03
|
|
line.long 0x00 "SHA_MEM1_11,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1170++0x03
|
|
line.long 0x00 "SHA_MEM1_12,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1174++0x03
|
|
line.long 0x00 "SHA_MEM1_13,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1178++0x03
|
|
line.long 0x00 "SHA_MEM1_14,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F117C++0x03
|
|
line.long 0x00 "SHA_MEM1_15,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1180++0x03
|
|
line.long 0x00 "SHA_MEM1_16,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1184++0x03
|
|
line.long 0x00 "SHA_MEM1_17,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1188++0x03
|
|
line.long 0x00 "SHA_MEM1_18,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F118C++0x03
|
|
line.long 0x00 "SHA_MEM1_19,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1190++0x03
|
|
line.long 0x00 "SHA_MEM1_20,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1194++0x03
|
|
line.long 0x00 "SHA_MEM1_21,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1198++0x03
|
|
line.long 0x00 "SHA_MEM1_22,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F119C++0x03
|
|
line.long 0x00 "SHA_MEM1_23,Shadow memory for fuse word80~103"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11A0++0x03
|
|
line.long 0x00 "SHA_REG2_0,Shadow register for fuse word104~111"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11A4++0x03
|
|
line.long 0x00 "SHA_REG2_1,Shadow register for fuse word104~111"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11A8++0x03
|
|
line.long 0x00 "SHA_REG2_2,Shadow register for fuse word104~111"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11AC++0x03
|
|
line.long 0x00 "SHA_REG2_3,Shadow register for fuse word104~111"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11B0++0x03
|
|
line.long 0x00 "SHA_REG2_4,Shadow register for fuse word104~111"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11B4++0x03
|
|
line.long 0x00 "SHA_REG2_5,Shadow register for fuse word104~111"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11B8++0x03
|
|
line.long 0x00 "SHA_REG2_6,Shadow register for fuse word104~111"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11BC++0x03
|
|
line.long 0x00 "SHA_REG2_7,Shadow register for fuse word104~111"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11C0++0x03
|
|
line.long 0x00 "SHA_MEM2_0,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11C4++0x03
|
|
line.long 0x00 "SHA_MEM2_1,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11C8++0x03
|
|
line.long 0x00 "SHA_MEM2_2,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11CC++0x03
|
|
line.long 0x00 "SHA_MEM2_3,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11D0++0x03
|
|
line.long 0x00 "SHA_MEM2_4,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11D4++0x03
|
|
line.long 0x00 "SHA_MEM2_5,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11D8++0x03
|
|
line.long 0x00 "SHA_MEM2_6,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11DC++0x03
|
|
line.long 0x00 "SHA_MEM2_7,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11E0++0x03
|
|
line.long 0x00 "SHA_MEM2_8,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11E4++0x03
|
|
line.long 0x00 "SHA_MEM2_9,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11E8++0x03
|
|
line.long 0x00 "SHA_MEM2_10,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11EC++0x03
|
|
line.long 0x00 "SHA_MEM2_11,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11F0++0x03
|
|
line.long 0x00 "SHA_MEM2_12,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11F4++0x03
|
|
line.long 0x00 "SHA_MEM2_13,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11F8++0x03
|
|
line.long 0x00 "SHA_MEM2_14,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F11FC++0x03
|
|
line.long 0x00 "SHA_MEM2_15,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1200++0x03
|
|
line.long 0x00 "SHA_MEM2_16,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1204++0x03
|
|
line.long 0x00 "SHA_MEM2_17,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1208++0x03
|
|
line.long 0x00 "SHA_MEM2_18,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F120C++0x03
|
|
line.long 0x00 "SHA_MEM2_19,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1210++0x03
|
|
line.long 0x00 "SHA_MEM2_20,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1214++0x03
|
|
line.long 0x00 "SHA_MEM2_21,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1218++0x03
|
|
line.long 0x00 "SHA_MEM2_22,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F121C++0x03
|
|
line.long 0x00 "SHA_MEM2_23,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1220++0x03
|
|
line.long 0x00 "SHA_MEM2_24,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1224++0x03
|
|
line.long 0x00 "SHA_MEM2_25,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1228++0x03
|
|
line.long 0x00 "SHA_MEM2_26,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F122C++0x03
|
|
line.long 0x00 "SHA_MEM2_27,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1230++0x03
|
|
line.long 0x00 "SHA_MEM2_28,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1234++0x03
|
|
line.long 0x00 "SHA_MEM2_29,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1238++0x03
|
|
line.long 0x00 "SHA_MEM2_30,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F123C++0x03
|
|
line.long 0x00 "SHA_MEM2_31,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1240++0x03
|
|
line.long 0x00 "SHA_MEM2_32,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1244++0x03
|
|
line.long 0x00 "SHA_MEM2_33,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1248++0x03
|
|
line.long 0x00 "SHA_MEM2_34,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F124C++0x03
|
|
line.long 0x00 "SHA_MEM2_35,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1250++0x03
|
|
line.long 0x00 "SHA_MEM2_36,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1254++0x03
|
|
line.long 0x00 "SHA_MEM2_37,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1258++0x03
|
|
line.long 0x00 "SHA_MEM2_38,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F125C++0x03
|
|
line.long 0x00 "SHA_MEM2_39,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1260++0x03
|
|
line.long 0x00 "SHA_MEM2_40,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1264++0x03
|
|
line.long 0x00 "SHA_MEM2_41,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1268++0x03
|
|
line.long 0x00 "SHA_MEM2_42,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F126C++0x03
|
|
line.long 0x00 "SHA_MEM2_43,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1270++0x03
|
|
line.long 0x00 "SHA_MEM2_44,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1274++0x03
|
|
line.long 0x00 "SHA_MEM2_45,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1278++0x03
|
|
line.long 0x00 "SHA_MEM2_46,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F127C++0x03
|
|
line.long 0x00 "SHA_MEM2_47,Shadow memory for fuse word112~159"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1280++0x03
|
|
line.long 0x00 "SHA_REG3_0,Shadow register for fuse word160~167"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1284++0x03
|
|
line.long 0x00 "SHA_REG3_1,Shadow register for fuse word160~167"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1288++0x03
|
|
line.long 0x00 "SHA_REG3_2,Shadow register for fuse word160~167"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F128C++0x03
|
|
line.long 0x00 "SHA_REG3_3,Shadow register for fuse word160~167"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1290++0x03
|
|
line.long 0x00 "SHA_REG3_4,Shadow register for fuse word160~167"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1294++0x03
|
|
line.long 0x00 "SHA_REG3_5,Shadow register for fuse word160~167"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1298++0x03
|
|
line.long 0x00 "SHA_REG3_6,Shadow register for fuse word160~167"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F129C++0x03
|
|
line.long 0x00 "SHA_REG3_7,Shadow register for fuse word160~167"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12A0++0x03
|
|
line.long 0x00 "SHA_MEM3_0,Shadow memory for fuse word168~175"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12A4++0x03
|
|
line.long 0x00 "SHA_MEM3_1,Shadow memory for fuse word168~175"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12A8++0x03
|
|
line.long 0x00 "SHA_MEM3_2,Shadow memory for fuse word168~175"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12AC++0x03
|
|
line.long 0x00 "SHA_MEM3_3,Shadow memory for fuse word168~175"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12B0++0x03
|
|
line.long 0x00 "SHA_MEM3_4,Shadow memory for fuse word168~175"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12B4++0x03
|
|
line.long 0x00 "SHA_MEM3_5,Shadow memory for fuse word168~175"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12B8++0x03
|
|
line.long 0x00 "SHA_MEM3_6,Shadow memory for fuse word168~175"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12BC++0x03
|
|
line.long 0x00 "SHA_MEM3_7,Shadow memory for fuse word168~175"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12C0++0x03
|
|
line.long 0x00 "SHA_REG4_0,Shadow register for fuse word176~179"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12C4++0x03
|
|
line.long 0x00 "SHA_REG4_1,Shadow register for fuse word176~179"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12C8++0x03
|
|
line.long 0x00 "SHA_REG4_2,Shadow register for fuse word176~179"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12CC++0x03
|
|
line.long 0x00 "SHA_REG4_3,Shadow register for fuse word176~179"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12D0++0x03
|
|
line.long 0x00 "SHA_MEM4_0,Shadow memory for fuse word180~183"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12D4++0x03
|
|
line.long 0x00 "SHA_MEM4_1,Shadow memory for fuse word180~183"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12D8++0x03
|
|
line.long 0x00 "SHA_MEM4_2,Shadow memory for fuse word180~183"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12DC++0x03
|
|
line.long 0x00 "SHA_MEM4_3,Shadow memory for fuse word180~183"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12E0++0x03
|
|
line.long 0x00 "SHA_REG5_0,Shadow register for fuse word184~191"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12E4++0x03
|
|
line.long 0x00 "SHA_REG5_1,Shadow register for fuse word184~191"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12E8++0x03
|
|
line.long 0x00 "SHA_REG5_2,Shadow register for fuse word184~191"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12EC++0x03
|
|
line.long 0x00 "SHA_REG5_3,Shadow register for fuse word184~191"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12F0++0x03
|
|
line.long 0x00 "SHA_REG5_4,Shadow register for fuse word184~191"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12F4++0x03
|
|
line.long 0x00 "SHA_REG5_5,Shadow register for fuse word184~191"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12F8++0x03
|
|
line.long 0x00 "SHA_REG5_6,Shadow register for fuse word184~191"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F12FC++0x03
|
|
line.long 0x00 "SHA_REG5_7,Shadow register for fuse word184~191"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1300++0x03
|
|
line.long 0x00 "SHA_MEM5_0,Shadow memory for fuse word192~199"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1304++0x03
|
|
line.long 0x00 "SHA_MEM5_1,Shadow memory for fuse word192~199"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1308++0x03
|
|
line.long 0x00 "SHA_MEM5_2,Shadow memory for fuse word192~199"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F130C++0x03
|
|
line.long 0x00 "SHA_MEM5_3,Shadow memory for fuse word192~199"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1310++0x03
|
|
line.long 0x00 "SHA_MEM5_4,Shadow memory for fuse word192~199"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1314++0x03
|
|
line.long 0x00 "SHA_MEM5_5,Shadow memory for fuse word192~199"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F1318++0x03
|
|
line.long 0x00 "SHA_MEM5_6,Shadow memory for fuse word192~199"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
group ad:0xF05F131C++0x03
|
|
line.long 0x00 "SHA_MEM5_7,Shadow memory for fuse word192~199"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Shadow register for fuse word"
|
|
tree.end
|
|
config 16. 8.
|
|
tree "FS_24M"
|
|
width 27.
|
|
group ad:0xF0660000++0x03
|
|
line.long 0x00 "FS_GLB_CTL,FS24M GLOBAL CONGROL REGISTER"
|
|
bitfld.long 0x00 31. " XTAL_ACTIVE ,xtal clk is chosen for fs_24m inDIcation" "0,1"
|
|
bitfld.long 0x00 30. " RC_ACTIVE ,RC clk is chosen for fs_24m inDIcation" "0,1"
|
|
bitfld.long 0x00 29. " XTAL_RDY ,xtal clock ready inDIcation. when xtal_src_sel is 0, it inDIcate xtal pad clock ready, otherwise it inDIcate ext_24MHz clock ready" "0,1"
|
|
bitfld.long 0x00 28. " RC_RDY ,RC clock ready inDIcation." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "HIB_EXP ,hibernate mode expect xtal clock to be on or off 1: on 0: off" "0,1"
|
|
bitfld.long 0x00 16. " SLP_EXP ,slp mode expect xtal clock to be on or off 1: on 0: off" "0,1"
|
|
bitfld.long 0x00 8. " CMP_FORCE_CLR ,compare counter force clear" "0,1"
|
|
bitfld.long 0x00 5. " EXT_OSC_EN ,1: osc ng is both ext check osc ng and xtal check osc ng 0: osc ng is only xtal check osc ng" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "EXT_XTAL_EN ,1: xtal ng is both ext check xtal ng and osc check xtal ng 0: xtal ng is only osc check xtal ng" "0,1"
|
|
bitfld.long 0x00 3. " FS_OSC_EN ,OSC 24M failsafe enable. 1: when fs_src_sel is osc and osc ng while xtal is ready, fs24M output will auto switch to XTAL24M" "0,1"
|
|
bitfld.long 0x00 2. " FS_XTAL_EN ,XTAL 24M failsafe enable. 1: when fs_src_sel is xtal and xtal ng while osc is ready, fs24M output will auto switch to osc24M" "0,1"
|
|
bitfld.long 0x00 1. " FS_SRC_SEL ,0: from osc24m 1: from xtal (or ext when XTAL_SRC_SEL is 1)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "XTAL_SRC_SEL ,0: xtal from xtal pad 1: xtal from ext_24MHz" "0,1"
|
|
group ad:0xF0660010++0x03
|
|
line.long 0x00 "RC_CTL,RC24M CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FREQ_TUNE_B ,bit7 is reserved. Frequency tune, the central frequency should be 24.576MHz. 400KHz/step. x0000000: fastest x1000000: 24.576MHz x1111111: lowest"
|
|
group ad:0xF0660014++0x03
|
|
line.long 0x00 "RC_RES,RC24M RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " RES ,rc24m reserved register"
|
|
group ad:0xF0660020++0x03
|
|
line.long 0x00 "XTAL_CTL,XTAL CONTROL REGISTGER"
|
|
bitfld.long 0x00 6. " XTAL_RDY_DLY ,0: 1ms 1: 2ms" "0,1"
|
|
bitfld.long 0x00 5. " POE ,0: po output high. po enable. 1: po output inverted xtal clock." "0,1"
|
|
bitfld.long 0x00 4. " SP ,not used." "0,1"
|
|
bitfld.long 0x00 2.--3. " SF ,selected frequency. 00: 1~4MHz 01: 4.1~12MHz 10: 12.1~24MHz 11: 24.1~48MHz" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1. "TE ,XTAL test enable. 0: test DIsable 1: test enable, clk from xtal_i" "0,1"
|
|
bitfld.long 0x00 0. " E0 ,XTAL ENABLE. 0: DISABLE 1: ENABLE E0=1 & TE=0: internal clock generation mode, a suitable quartz crystal should be connected between PADI and PADO. Or a DIfferential signal should be applied between PADI and PADO. E0=0 & .." "0,1"
|
|
group ad:0xF0660024++0x03
|
|
line.long 0x00 "XTAL_RES,XTAL RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " RES ,bit[0]: ext 24m enable bit[1]: xtal clock error injection bit[2]: xtal clock rdy error injection bit[3]: RC clock error injection bit[4]: RC clock rdy error injection bit[5]: fs_clk_24m error injection for fs_refgen bit[6]: .."
|
|
group ad:0xF0660100++0x03
|
|
line.long 0x00 "OSC_CHK_XTAL_EN,OSC CHECK XTAL ENABLE REGISTER"
|
|
bitfld.long 0x00 31. " FORCE_CHK_EN_STA ,force check enable status" "0,1"
|
|
bitfld.long 0x00 30. " HW_CHK_EN_STA ,hardware check enable status" "0,1"
|
|
bitfld.long 0x00 1. " FORCE_CHK_EN ,force check enable, ignore clk ready. 0: DIable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " HW_CHK_EN ,hardware check enable based on clk ready. 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0660104++0x03
|
|
line.long 0x00 "OSC_CHK_XTAL_CTL,OSC CHECK XTAL CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " CLK_NG_MON ,debug purpose" "0,1"
|
|
hexmask.long.word 0x00 3.--18. 1. " CHK_CFG ,clock check frequency. CHK_CFG * cycle number inDIcated by EXT_CFG. default: 16*4= 64cycles"
|
|
bitfld.long 0x00 0.--2. " EXT_CFG ,clock check extension width. 000: 2 cycles per check. 001: 4 cycles per check. 010: 8 cycles per check. 011: 16 cycles per check. 100: 32 cycles per check. 101: 64 cycles per check. 110: 128 cycles per check. 111: 256 cycles per .." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0660108++0x03
|
|
line.long 0x00 "OSC_CHK_XTAL_THRD,OSC CHECK XTAL THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,violation happends when xtal counter reaches CHK_CFG while osc counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when xtal counter reaches CHK_CFG while osc counter less than Low register"
|
|
group ad:0xF0660200++0x03
|
|
line.long 0x00 "XTAL_CHK_OSC_EN,XTAL CHECK OSC ENABLE REGISTER"
|
|
bitfld.long 0x00 31. " FORCE_CHK_EN_STA ,force check enable status" "0,1"
|
|
bitfld.long 0x00 30. " HW_CHK_EN_STA ,hardware check enable status" "0,1"
|
|
bitfld.long 0x00 1. " FORCE_CHK_EN ,force check enable, ignore clk ready. 0: DIable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " HW_CHK_EN ,hardware check enable based on clk ready. 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0660204++0x03
|
|
line.long 0x00 "XTAL_CHK_OSC_CTL,XTAL CHECK OSC CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " CLK_NG_MON ,debug purpose" "0,1"
|
|
hexmask.long.word 0x00 3.--18. 1. " CHK_CFG ,clock check frequency. CHK_CFG * cycle number inDIcated by EXT_CFG. default: 16*4= 64cycles"
|
|
bitfld.long 0x00 0.--2. " EXT_CFG ,clock check extension width. 000: 2 cycles per check. 001: 4 cycles per check. 010: 8 cycles per check. 011: 16 cycles per check. 100: 32 cycles per check. 101: 64 cycles per check. 110: 128 cycles per check. 111: 256 cycles per .." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0660208++0x03
|
|
line.long 0x00 "XTAL_CHK_OSC_THRD,XTAL CHECK OSC THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,violation happends when xtal counter reaches CHK_CFG while osc counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when xtal counter reaches CHK_CFG while osc counter less than Low register"
|
|
group ad:0xF0660300++0x03
|
|
line.long 0x00 "EXT_CHK_XTAL_EN,EXT CHECK XTAL ENABLE REGISTER"
|
|
bitfld.long 0x00 31. " FORCE_CHK_EN_STA ,force check enable status" "0,1"
|
|
bitfld.long 0x00 30. " HW_CHK_EN_STA ,hardware check enable status" "0,1"
|
|
bitfld.long 0x00 1. " FORCE_CHK_EN ,force check enable, ignore clk ready. 0: DIable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " HW_CHK_EN ,hardware check enable based on clk ready. 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0660304++0x03
|
|
line.long 0x00 "EXT_CHK_XTAL_CTL,EXT CHECK XTAL CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " CLK_NG_MON ,debug purpose" "0,1"
|
|
hexmask.long.word 0x00 3.--18. 1. " CHK_CFG ,clock check frequency. CHK_CFG * cycle number inDIcated by EXT_CFG. default: 16*4= 64cycles"
|
|
bitfld.long 0x00 0.--2. " EXT_CFG ,clock check extension width. 000: 2 cycles per check. 001: 4 cycles per check. 010: 8 cycles per check. 011: 16 cycles per check. 100: 32 cycles per check. 101: 64 cycles per check. 110: 128 cycles per check. 111: 256 cycles per .." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0660308++0x03
|
|
line.long 0x00 "EXT_CHK_XTAL_THRD,EXT CHECK XTAL THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,violation happends when xtal counter reaches CHK_CFG while osc counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when xtal counter reaches CHK_CFG while osc counter less than Low register"
|
|
group ad:0xF0660400++0x03
|
|
line.long 0x00 "EXT_CHK_OSC_EN,EXT CHECK OSC ENABLE REGISTER"
|
|
bitfld.long 0x00 31. " FORCE_CHK_EN_STA ,force check enable status" "0,1"
|
|
bitfld.long 0x00 30. " HW_CHK_EN_STA ,hardware check enable status" "0,1"
|
|
bitfld.long 0x00 1. " FORCE_CHK_EN ,force check enable, ignore clk ready. 0: DIable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " HW_CHK_EN ,hardware check enable based on clk ready. 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0660404++0x03
|
|
line.long 0x00 "EXT_CHK_OSC_CTL,EXT CHECK OSC CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " CLK_NG_MON ,debug purpose" "0,1"
|
|
hexmask.long.word 0x00 3.--18. 1. " CHK_CFG ,clock check frequency. CHK_CFG * cycle number inDIcated by EXT_CFG. default: 16*4= 64cycles"
|
|
bitfld.long 0x00 0.--2. " EXT_CFG ,clock check extension width. 000: 2 cycles per check. 001: 4 cycles per check. 010: 8 cycles per check. 011: 16 cycles per check. 100: 32 cycles per check. 101: 64 cycles per check. 110: 128 cycles per check. 111: 256 cycles per .." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0660408++0x03
|
|
line.long 0x00 "EXT_CHK_OSC_THRD,EXT CHECK OSC THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,violation happends when xtal counter reaches CHK_CFG while osc counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when xtal counter reaches CHK_CFG while osc counter less than Low register"
|
|
group ad:0xF0660500++0x03
|
|
line.long 0x00 "RC32K_CHK_CTL,RC 32K CHECK CONTROL REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " FREQ_CNT_STA ,32k frequency recorded every 32k posedge. 32k frequency equals to: 24000(not accurate if 24m is from RC24M)/freq_cnt_sta"
|
|
bitfld.long 0x00 3. " FREQ_VIO_CLR ,freq_vio_sta clear 1: clear 0: not clear set 1 to clear freq_vio_sta, and set to 0 after read back freq_vio_sta is 0 already, if freq_vio_sta is always 1, please check freq_cnt_sta to make sure 32k frequency is within the .." "0,1"
|
|
bitfld.long 0x00 2. " FREQ_VIO_STA ,RC32k or RC24m out of range inDIcation record, can be cleared by freq_vio_clr" "0,1"
|
|
bitfld.long 0x00 1. " MON_EN_STA ,mon_en need to be synced to 24m clock domain from pclk domain. this bit inDIcate mon_en value under 32k clock domain" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "MON_EN ,RC32K frequency monitor enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF0660508++0x03
|
|
line.long 0x00 "RC32K_CHK_THRD,RC32K CHECK THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,high threshold. violation happends when frequency counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when frequency counter less than Low register"
|
|
group ad:0xF0660600++0x03
|
|
line.long 0x00 "ERR_INJ_EN,ERROR INJECTION ENABLE REGISTER"
|
|
bitfld.long 0x00 2. " OUT_INJ_EN ,fs24m output error injection enable, reserved 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_INJ_EN ,IRQ error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " APB_INJ_EN ,APB E2E error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0660604++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF0660608++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF0660610++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF0660614++0x03
|
|
line.long 0x00 "FS_FUSA_INT,FS FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 21. " SWITCH_ERR_CLR ,switch error clear" "0,1"
|
|
bitfld.long 0x00 20. " EXT_CHK_OSC_NG_CLR ,ext check osc ng clear" "0,1"
|
|
bitfld.long 0x00 19. " EXT_CHK_XTAL_NG_CLR ,ext check xtal ng clear" "0,1"
|
|
bitfld.long 0x00 18. " XTAL_CHK_OSC_NG_CLR ,xtal check osc ng clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "OSC_CHK_XTAL_NG_CLR ,osc check xtal ng clear" "0,1"
|
|
bitfld.long 0x00 16. " SYNC_ERR_CLR ,sync err clear" "0,1"
|
|
bitfld.long 0x00 13. " SWITCH_ERR_STA ,switch error status" "0,1"
|
|
bitfld.long 0x00 12. " EXT_CHK_OSC_NG_STA ,ext check osc ng status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "EXT_CHK_XTAL_NG_STA ,ext check xtal ng status" "0,1"
|
|
bitfld.long 0x00 10. " XTAL_CHK_OSC_NG_STA ,xtal check osc ng status" "0,1"
|
|
bitfld.long 0x00 9. " OSC_CHK_XTAL_NG_STA ,osc check xtal ng status" "0,1"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,fusa sync irq status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "SWITCH_ERR_EN ,switch error enable" "0,1"
|
|
bitfld.long 0x00 4. " EXT_CHK_OSC_NG_EN ,ext check osc ng enable" "0,1"
|
|
bitfld.long 0x00 3. " EXT_CHK_XTAL_NG_EN ,ext check xtal ng enable" "0,1"
|
|
bitfld.long 0x00 2. " XTAL_CHK_OSC_NG_EN ,xtal check osc ng enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "OSC_CHK_XTAL_NG_EN ,osc check xtal ng enable" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,fusa sync irq enable" "0,1"
|
|
group ad:0xF0660618++0x03
|
|
line.long 0x00 "FS_ERR_INJ,FS ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 2. " UNC_IRQ_INJ ,unc irq error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR_IRQ_INJ ,cor irq error injection" "0,1"
|
|
bitfld.long 0x00 0. " FS_IRQ_INJ ,fs irq error injection, reserved" "0,1"
|
|
group ad:0xF0660700++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
|
|
bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
|
|
group ad:0xF0660704++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF0660708++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
tree.end
|
|
config 16. 8.
|
|
tree "FS_32K"
|
|
width 27.
|
|
group ad:0xF0030000++0x03
|
|
line.long 0x00 "FS_GLB_CTL,FS24M GLOBAL CONGROL REGISTER"
|
|
bitfld.long 0x00 31. " XTAL_ACTIVE ,xtal clk is chosen for fs_32k inDIcation" "0,1"
|
|
bitfld.long 0x00 30. " RC_ACTIVE ,RC clk is chosen for fs_32k inDIcation" "0,1"
|
|
bitfld.long 0x00 29. " XTAL_RDY ,xtal clock ready inDIcation." "0,1"
|
|
bitfld.long 0x00 28. " RC_RDY ,RC clock ready inDIcation." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "CMP_FORCE_CLR ,compare counter force clear" "0,1"
|
|
bitfld.long 0x00 5. " EXT_OSC_EN ,reserved" "0,1"
|
|
bitfld.long 0x00 4. " EXT_XTAL_EN ,reserved" "0,1"
|
|
bitfld.long 0x00 3. " FS_OSC_EN ,OSC 32K failsafe enable. 1: when fs_src_sel is osc and osc ng while xtal is ready, fs32K output will auto switch to XTAL32K" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "FS_XTAL_EN ,XTAL 32K failsafe enable. 1: when fs_src_sel is xtal and xtal ng while osc is ready, fs32K output will auto switch to osc32K" "0,1"
|
|
bitfld.long 0x00 1. " FS_SRC_SEL ,0: from osc32k 1: from xtal" "0,1"
|
|
bitfld.long 0x00 0. " XTAL_SRC_SEL ,reserved" "0,1"
|
|
group ad:0xF0030010++0x03
|
|
line.long 0x00 "RC_CTL,RC24M CONTROL REGISTER"
|
|
bitfld.long 0x00 0.--3. " FREQ_TUNE_B ,Frequency tune, the central frequency should be 32KHz. 0.5KHz/step. 0000: fastest 1000: 32KHz 1111: lowest" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0030014++0x03
|
|
line.long 0x00 "RC_RES,RC24M RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " RES ,rc32k reserved register Reserve for ROMCODE use"
|
|
group ad:0xF0030020++0x03
|
|
line.long 0x00 "XTAL_CTL,XTAL CONTROL REGISTGER"
|
|
bitfld.long 0x00 6. " XTAL_RDY_DLY ,0: 1ms 1: 2ms" "0,1"
|
|
bitfld.long 0x00 5. " POE ,0: po output high. po enable. 1: po output inverted xtal clock." "0,1"
|
|
bitfld.long 0x00 4. " DS ,not used." "0,1"
|
|
bitfld.long 0x00 1. " TE ,XTAL test enable. 0: test DIsable 1: test enable, clk from xtal_i" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "E0 ,XTAL ENABLE. 0: DISABLE 1: ENABLE" "0,1"
|
|
group ad:0xF0030024++0x03
|
|
line.long 0x00 "XTAL_RES,XTAL RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " RES ,bit[0]: reserved register bit[1]: xtal clock error injection bit[2]: xtal clock rdy error injection bit[3]: RC clock error injection bit[4]: RC clock rdy error injection bit[31:5]:reserved register"
|
|
group ad:0xF0030030++0x03
|
|
line.long 0x00 "LPVD_CTL,LP VOLTAGE DETECTOR CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " BGOK ,bandgap ok status" "0,1"
|
|
bitfld.long 0x00 27. " V33_UV_STA ,v33 under voltage status." "0,1"
|
|
bitfld.long 0x00 26. " V33_OV_STA ,v33 over voltage status." "0,1"
|
|
bitfld.long 0x00 25. " V08_UV_STA ,v08 under voltage status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. "V08_OV_STA ,v08 over voltage status." "0,1"
|
|
bitfld.long 0x00 21. " LPVD_NG_CLR ,low power over voltage detector not good clear 1: clear 0: not clear check status before set it back to 0" "0,1"
|
|
bitfld.long 0x00 20. " LPVD_NG_STA ,low power over voltage detector status. 1: not good, include v08 ov/uv or v33 ov/uv 0: good" "0,1"
|
|
bitfld.long 0x00 19. " V33_UV_MASK ,v33 under voltage mask. 1: mask 0: unmask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. "V33_OV_MASK ,v33 over voltage mask. 1: mask 0: unmask" "0,1"
|
|
bitfld.long 0x00 17. " V08_UV_MASK ,v08 under voltage mask. 1: mask 0: unmask" "0,1"
|
|
bitfld.long 0x00 16. " V08_OV_MASK ,v08 over voltage mask. 1: mask 0: unmask" "0,1"
|
|
bitfld.long 0x00 12.--14. " ATEST_SEL ,low power voltage detector analog test select." "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--11. 1. "CTRL ,low power voltage detector control"
|
|
bitfld.long 0x00 1.--3. " TRIM ,low power voltage detector trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " PD ,low power voltage detector power down 1: power down 0: power on" "0,1"
|
|
group ad:0xF0030100++0x03
|
|
line.long 0x00 "OSC_CHK_XTAL_EN,OSC CHECK XTAL ENABLE REGISTER"
|
|
bitfld.long 0x00 31. " FORCE_CHK_EN_STA ,force check enable status" "0,1"
|
|
bitfld.long 0x00 30. " HW_CHK_EN_STA ,hardware check enable status" "0,1"
|
|
bitfld.long 0x00 1. " FORCE_CHK_EN ,force check enable, ignore clk ready. 0: DIable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " HW_CHK_EN ,hardware check enable based on clk ready. 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0030104++0x03
|
|
line.long 0x00 "OSC_CHK_XTAL_CTL,OSC CHECK XTAL CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " CLK_NG_MON ,debug purpose" "0,1"
|
|
hexmask.long.word 0x00 3.--18. 1. " CHK_CFG ,clock check frequency. CHK_CFG * cycle number inDIcated by EXT_CFG. default: 16*4= 64cycles"
|
|
bitfld.long 0x00 0.--2. " EXT_CFG ,clock check extension width. 000: 2 cycles per check. 001: 4 cycles per check. 010: 8 cycles per check. 011: 16 cycles per check. 100: 32 cycles per check. 101: 64 cycles per check. 110: 128 cycles per check. 111: 256 cycles per .." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0030108++0x03
|
|
line.long 0x00 "OSC_CHK_XTAL_THRD,OSC CHECK XTAL THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,violation happends when xtal counter reaches CHK_CFG while osc counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when xtal counter reaches CHK_CFG while osc counter less than Low register"
|
|
group ad:0xF0030200++0x03
|
|
line.long 0x00 "XTAL_CHK_OSC_EN,XTAL CHECK OSC ENABLE REGISTER"
|
|
bitfld.long 0x00 31. " FORCE_CHK_EN_STA ,force check enable status" "0,1"
|
|
bitfld.long 0x00 30. " HW_CHK_EN_STA ,hardware check enable status" "0,1"
|
|
bitfld.long 0x00 1. " FORCE_CHK_EN ,force check enable, ignore clk ready. 0: DIable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " HW_CHK_EN ,hardware check enable based on clk ready. 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0030204++0x03
|
|
line.long 0x00 "XTAL_CHK_OSC_CTL,XTAL CHECK OSC CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " CLK_NG_MON ,debug purpose" "0,1"
|
|
hexmask.long.word 0x00 3.--18. 1. " CHK_CFG ,clock check frequency. CHK_CFG * cycle number inDIcated by EXT_CFG. default: 16*4= 64cycles"
|
|
bitfld.long 0x00 0.--2. " EXT_CFG ,clock check extension width. 000: 2 cycles per check. 001: 4 cycles per check. 010: 8 cycles per check. 011: 16 cycles per check. 100: 32 cycles per check. 101: 64 cycles per check. 110: 128 cycles per check. 111: 256 cycles per .." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0030208++0x03
|
|
line.long 0x00 "XTAL_CHK_OSC_THRD,XTAL CHECK OSC THRESHOLD REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH ,violation happends when xtal counter reaches CHK_CFG while osc counter larger than High register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW ,low threshold. violation happends when xtal counter reaches CHK_CFG while osc counter less than Low register"
|
|
group ad:0xF0030600++0x03
|
|
line.long 0x00 "ERR_INJ_EN,ERROR INJECTION ENABLE REGISTER"
|
|
bitfld.long 0x00 2. " OUT_INJ_EN ,pll output error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_INJ_EN ,IRQ error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " APB_INJ_EN ,APB E2E error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0030604++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF0030608++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF0030610++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF0030614++0x03
|
|
line.long 0x00 "FS_FUSA_INT,FS FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 19. " SWITCH_ERR_CLR ,switch error clear" "0,1"
|
|
bitfld.long 0x00 18. " XTAL_CHK_OSC_NG_CLR ,xtal check osc ng clear" "0,1"
|
|
bitfld.long 0x00 17. " OSC_CHK_XTAL_NG_CLR ,osc check xtal ng clear" "0,1"
|
|
bitfld.long 0x00 16. " SYNC_ERR_CLR ,sync err clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "SWITCH_ERR_STA ,switch error status" "0,1"
|
|
bitfld.long 0x00 10. " XTAL_CHK_OSC_NG_STA ,xtal check osc ng status" "0,1"
|
|
bitfld.long 0x00 9. " OSC_CHK_XTAL_NG_STA ,osc check xtal ng status" "0,1"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,fusa sync irq status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SWITCH_ERR_EN ,switch error enable" "0,1"
|
|
bitfld.long 0x00 2. " XTAL_CHK_OSC_NG_EN ,xtal check osc ng enable" "0,1"
|
|
bitfld.long 0x00 1. " OSC_CHK_XTAL_NG_EN ,osc check xtal ng enable" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,fusa sync irq enable" "0,1"
|
|
group ad:0xF0030618++0x03
|
|
line.long 0x00 "FS_ERR_INJ,FS ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 3. " LPVD_NG_INJ ,lpvd_ng injection" "0,1"
|
|
bitfld.long 0x00 2. " UNC_IRQ_INJ ,unc irq error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR_IRQ_INJ ,cor irq error injection" "0,1"
|
|
bitfld.long 0x00 0. " FS_IRQ_INJ ,fs irq error injection" "0,1"
|
|
group ad:0xF0030620++0x03
|
|
line.long 0x00 "FS_FUNC_INT,FS_32K FUNCTION INTERRUPT REGISTER"
|
|
bitfld.long 0x00 8. " XTAL_RDY_INT_STA ,xtal ready interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 0. " XTAL_RDY_INT_EN ,xtal ready interrupt enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF0030700++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
|
|
bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
|
|
group ad:0xF0030704++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF0030708++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
tree.end
|
|
config 16. 8.
|
|
tree "GPIO"
|
|
tree "GPIO_SF"
|
|
width 27.
|
|
group ad:0xF0740000++0x03
|
|
line.long 0x00 "DOM_PER0_0,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740004++0x03
|
|
line.long 0x00 "DOM_PER1_0,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740008++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_0,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF074000C++0x03
|
|
line.long 0x00 "DOM_PER0_1,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740010++0x03
|
|
line.long 0x00 "DOM_PER1_1,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740014++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_1,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF0740018++0x03
|
|
line.long 0x00 "DOM_PER0_2,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF074001C++0x03
|
|
line.long 0x00 "DOM_PER1_2,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740020++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_2,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF0740024++0x03
|
|
line.long 0x00 "DOM_PER0_3,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740028++0x03
|
|
line.long 0x00 "DOM_PER1_3,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF074002C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_3,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF0740030++0x03
|
|
line.long 0x00 "DOM_PER0_4,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740034++0x03
|
|
line.long 0x00 "DOM_PER1_4,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740038++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_4,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF074003C++0x03
|
|
line.long 0x00 "DOM_PER0_5,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740040++0x03
|
|
line.long 0x00 "DOM_PER1_5,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740044++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_5,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF0740048++0x03
|
|
line.long 0x00 "DOM_PER0_6,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF074004C++0x03
|
|
line.long 0x00 "DOM_PER1_6,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740050++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_6,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF0740054++0x03
|
|
line.long 0x00 "DOM_PER0_7,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740058++0x03
|
|
line.long 0x00 "DOM_PER1_7,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF074005C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_7,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF0740060++0x03
|
|
line.long 0x00 "DOM_PER0_8,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740064++0x03
|
|
line.long 0x00 "DOM_PER1_8,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740068++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_8,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF074006C++0x03
|
|
line.long 0x00 "DOM_PER0_9,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740070++0x03
|
|
line.long 0x00 "DOM_PER1_9,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740074++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_9,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF0740078++0x03
|
|
line.long 0x00 "DOM_PER0_10,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF074007C++0x03
|
|
line.long 0x00 "DOM_PER1_10,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740080++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_10,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF0740084++0x03
|
|
line.long 0x00 "DOM_PER0_11,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740088++0x03
|
|
line.long 0x00 "DOM_PER1_11,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF074008C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_11,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF0740090++0x03
|
|
line.long 0x00 "DOM_PER0_12,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740094++0x03
|
|
line.long 0x00 "DOM_PER1_12,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0740098++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_12,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF074009C++0x03
|
|
line.long 0x00 "DOM_PER0_13,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF07400A0++0x03
|
|
line.long 0x00 "DOM_PER1_13,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF07400A4++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_13,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF07400A8++0x03
|
|
line.long 0x00 "DOM_PER0_14,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF07400AC++0x03
|
|
line.long 0x00 "DOM_PER1_14,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF07400B0++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_14,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF07400B4++0x03
|
|
line.long 0x00 "DOM_PER0_15,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
group ad:0xF07400B8++0x03
|
|
line.long 0x00 "DOM_PER1_15,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
group ad:0xF07400BC++0x03
|
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line.long 0x00 "DOM_PER_LOCK_15,This register is used to lock domain access permission setting."
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bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
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bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
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bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
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bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
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|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
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|
group ad:0xF0740140++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
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bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
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|
group ad:0xF0740144++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
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group ad:0xF0740148++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
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group ad:0xF074014C++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740150++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740154++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740158++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074015C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740160++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740164++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740168++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074016C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740170++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740174++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740178++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074017C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740180++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740184++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740188++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074018C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740190++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740194++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740198++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074019C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401A0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401A4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401A8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401AC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401B0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401B4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401B8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401BC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401C0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401C4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401C8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401CC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401D0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401D4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401D8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401DC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401E0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401E4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401E8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401EC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401F0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401F4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401F8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07401FC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740200++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740204++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740208++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074020C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740210++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740214++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740218++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074021C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740220++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740224++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740228++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074022C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740230++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740234++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740238++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074023C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740240++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740244++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740248++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074024C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740250++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740254++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740258++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074025C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740260++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740264++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740268++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074026C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740270++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740274++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740278++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074027C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740280++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740284++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740288++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074028C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740290++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740294++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740298++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074029C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402A0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402A4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402A8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402AC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402B0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402B4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402B8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402BC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402C0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402C4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402C8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402CC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402D0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402D4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402D8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402DC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402E0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402E4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402E8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402EC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402F0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402F4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402F8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF07402FC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740300++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740304++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740308++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074030C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740310++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740314++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740318++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074031C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740320++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740324++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740328++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074032C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740330++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740334++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740338++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF074033C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740580++0x03
|
|
line.long 0x00 "GPIO_OEN_0,GPIO OUTPUT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " OEN ,Output enable"
|
|
group ad:0xF0740590++0x03
|
|
line.long 0x00 "GPIO_OEN_1,GPIO OUTPUT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " OEN ,Output enable"
|
|
group ad:0xF07405A0++0x03
|
|
line.long 0x00 "GPIO_OEN_2,GPIO OUTPUT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " OEN ,Output enable"
|
|
group ad:0xF07405B0++0x03
|
|
line.long 0x00 "GPIO_OEN_3,GPIO OUTPUT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " OEN ,Output enable"
|
|
group ad:0xF0740600++0x03
|
|
line.long 0x00 "GPIO_DATA_IN_0,GPIO DATA INPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DIN ,Gpio data input"
|
|
group ad:0xF0740610++0x03
|
|
line.long 0x00 "GPIO_DATA_IN_1,GPIO DATA INPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DIN ,Gpio data input"
|
|
group ad:0xF0740620++0x03
|
|
line.long 0x00 "GPIO_DATA_IN_2,GPIO DATA INPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DIN ,Gpio data input"
|
|
group ad:0xF0740630++0x03
|
|
line.long 0x00 "GPIO_DATA_IN_3,GPIO DATA INPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DIN ,Gpio data input"
|
|
group ad:0xF0740680++0x03
|
|
line.long 0x00 "GPIO_DATA_OUT_0,GPIO DATA OUTPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DOUT ,Gpio data output"
|
|
group ad:0xF0740690++0x03
|
|
line.long 0x00 "GPIO_DATA_OUT_1,GPIO DATA OUTPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DOUT ,Gpio data output"
|
|
group ad:0xF07406A0++0x03
|
|
line.long 0x00 "GPIO_DATA_OUT_2,GPIO DATA OUTPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DOUT ,Gpio data output"
|
|
group ad:0xF07406B0++0x03
|
|
line.long 0x00 "GPIO_DATA_OUT_3,GPIO DATA OUTPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DOUT ,Gpio data output"
|
|
group ad:0xF0740700++0x03
|
|
line.long 0x00 "GPIO_SINT_EN_0,GPIO SYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Synchronous interrupt enable"
|
|
group ad:0xF0740710++0x03
|
|
line.long 0x00 "GPIO_SINT_EN_1,GPIO SYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Synchronous interrupt enable"
|
|
group ad:0xF0740720++0x03
|
|
line.long 0x00 "GPIO_SINT_EN_2,GPIO SYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Synchronous interrupt enable"
|
|
group ad:0xF0740730++0x03
|
|
line.long 0x00 "GPIO_SINT_EN_3,GPIO SYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Synchronous interrupt enable"
|
|
group ad:0xF0740780++0x03
|
|
line.long 0x00 "GPIO_SINT_MASK_0,GPIO SYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Synchronous interrupt mask"
|
|
group ad:0xF0740790++0x03
|
|
line.long 0x00 "GPIO_SINT_MASK_1,GPIO SYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Synchronous interrupt mask"
|
|
group ad:0xF07407A0++0x03
|
|
line.long 0x00 "GPIO_SINT_MASK_2,GPIO SYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Synchronous interrupt mask"
|
|
group ad:0xF07407B0++0x03
|
|
line.long 0x00 "GPIO_SINT_MASK_3,GPIO SYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Synchronous interrupt mask"
|
|
group ad:0xF0740800++0x03
|
|
line.long 0x00 "GPIO_SINT_TYPE_0,GPIO SYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Synchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF0740810++0x03
|
|
line.long 0x00 "GPIO_SINT_TYPE_1,GPIO SYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Synchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF0740820++0x03
|
|
line.long 0x00 "GPIO_SINT_TYPE_2,GPIO SYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Synchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF0740830++0x03
|
|
line.long 0x00 "GPIO_SINT_TYPE_3,GPIO SYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Synchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF0740880++0x03
|
|
line.long 0x00 "GPIO_SINT_POL_0,GPIO SYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Synchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF0740890++0x03
|
|
line.long 0x00 "GPIO_SINT_POL_1,GPIO SYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Synchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF07408A0++0x03
|
|
line.long 0x00 "GPIO_SINT_POL_2,GPIO SYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Synchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF07408B0++0x03
|
|
line.long 0x00 "GPIO_SINT_POL_3,GPIO SYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Synchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF0740900++0x03
|
|
line.long 0x00 "GPIO_SINT_BOE_0,GPIO SYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Synchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF0740910++0x03
|
|
line.long 0x00 "GPIO_SINT_BOE_1,GPIO SYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Synchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF0740920++0x03
|
|
line.long 0x00 "GPIO_SINT_BOE_2,GPIO SYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Synchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF0740930++0x03
|
|
line.long 0x00 "GPIO_SINT_BOE_3,GPIO SYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Synchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF0740980++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_0,GPIO SYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Synchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740990++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_1,GPIO SYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Synchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF07409A0++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_2,GPIO SYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Synchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF07409B0++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_3,GPIO SYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Synchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740A00++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_UNMASK_0,GPIO SYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_MASK ,Synchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740A10++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_UNMASK_1,GPIO SYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_MASK ,Synchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740A20++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_UNMASK_2,GPIO SYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_MASK ,Synchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740A30++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_UNMASK_3,GPIO SYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_MASK ,Synchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740A80++0x03
|
|
line.long 0x00 "GPIO_SINT_EDGE_CLR_0,GPIO SYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Synchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF0740A90++0x03
|
|
line.long 0x00 "GPIO_SINT_EDGE_CLR_1,GPIO SYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Synchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF0740AA0++0x03
|
|
line.long 0x00 "GPIO_SINT_EDGE_CLR_2,GPIO SYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Synchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF0740AB0++0x03
|
|
line.long 0x00 "GPIO_SINT_EDGE_CLR_3,GPIO SYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Synchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF0740B00++0x03
|
|
line.long 0x00 "GPIO_AINT_EN_0,GPIO ASYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Asynchronous interrupt enable"
|
|
group ad:0xF0740B10++0x03
|
|
line.long 0x00 "GPIO_AINT_EN_1,GPIO ASYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Asynchronous interrupt enable"
|
|
group ad:0xF0740B20++0x03
|
|
line.long 0x00 "GPIO_AINT_EN_2,GPIO ASYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Asynchronous interrupt enable"
|
|
group ad:0xF0740B30++0x03
|
|
line.long 0x00 "GPIO_AINT_EN_3,GPIO ASYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Asynchronous interrupt enable"
|
|
group ad:0xF0740B80++0x03
|
|
line.long 0x00 "GPIO_AINT_MASK_0,GPIO ASYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Asynchronous interrupt mask"
|
|
group ad:0xF0740B90++0x03
|
|
line.long 0x00 "GPIO_AINT_MASK_1,GPIO ASYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Asynchronous interrupt mask"
|
|
group ad:0xF0740BA0++0x03
|
|
line.long 0x00 "GPIO_AINT_MASK_2,GPIO ASYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Asynchronous interrupt mask"
|
|
group ad:0xF0740BB0++0x03
|
|
line.long 0x00 "GPIO_AINT_MASK_3,GPIO ASYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Asynchronous interrupt mask"
|
|
group ad:0xF0740C00++0x03
|
|
line.long 0x00 "GPIO_AINT_TYPE_0,GPIO ASYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Asynchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF0740C10++0x03
|
|
line.long 0x00 "GPIO_AINT_TYPE_1,GPIO ASYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Asynchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF0740C20++0x03
|
|
line.long 0x00 "GPIO_AINT_TYPE_2,GPIO ASYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Asynchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF0740C30++0x03
|
|
line.long 0x00 "GPIO_AINT_TYPE_3,GPIO ASYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Asynchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF0740C80++0x03
|
|
line.long 0x00 "GPIO_AINT_POL_0,GPIO ASYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Asynchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF0740C90++0x03
|
|
line.long 0x00 "GPIO_AINT_POL_1,GPIO ASYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Asynchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF0740CA0++0x03
|
|
line.long 0x00 "GPIO_AINT_POL_2,GPIO ASYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Asynchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF0740CB0++0x03
|
|
line.long 0x00 "GPIO_AINT_POL_3,GPIO ASYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Asynchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF0740D00++0x03
|
|
line.long 0x00 "GPIO_AINT_BOE_0,GPIO ASYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Asynchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF0740D10++0x03
|
|
line.long 0x00 "GPIO_AINT_BOE_1,GPIO ASYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Asynchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF0740D20++0x03
|
|
line.long 0x00 "GPIO_AINT_BOE_2,GPIO ASYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Asynchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF0740D30++0x03
|
|
line.long 0x00 "GPIO_AINT_BOE_3,GPIO ASYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Asynchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF0740D80++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_0,GPIO ASYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Asynchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740D90++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_1,GPIO ASYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Asynchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740DA0++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_2,GPIO ASYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Asynchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740DB0++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_3,GPIO ASYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Asynchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740E00++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_UNMASK_0,GPIO ASYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_UNMASK ,Asynchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740E10++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_UNMASK_1,GPIO ASYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_UNMASK ,Asynchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740E20++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_UNMASK_2,GPIO ASYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_UNMASK ,Asynchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740E30++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_UNMASK_3,GPIO ASYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_UNMASK ,Asynchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF0740E80++0x03
|
|
line.long 0x00 "GPIO_AINT_EDGE_CLR_0,GPIO ASYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Asynchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF0740E90++0x03
|
|
line.long 0x00 "GPIO_AINT_EDGE_CLR_1,GPIO ASYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Asynchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF0740EA0++0x03
|
|
line.long 0x00 "GPIO_AINT_EDGE_CLR_2,GPIO ASYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Asynchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF0740EB0++0x03
|
|
line.long 0x00 "GPIO_AINT_EDGE_CLR_3,GPIO ASYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Asynchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF0740F00++0x03
|
|
line.long 0x00 "ERR_INJ_DGSEL,ERROR INJECTION DGSEL ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for error injection dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,error injection dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,error injection permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740F08++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF0740F0C++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF0740F10++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF0740F14++0x03
|
|
line.long 0x00 "GPIO_FUSA_INT,GPIO FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,Sync error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,Sync error enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF0740F18++0x03
|
|
line.long 0x00 "GPIO_INJ_EN,GPIO ERROR INJECTION ENABLE REGISTER"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INJ_EN ,Error injection enable. bit0: irq error injection enable bit1: apb error injection enable bit[7:2] reserved"
|
|
group ad:0xF0740F1C++0x03
|
|
line.long 0x00 "DGPIO_INT_INJ,DGPIO INTERRUPT INJECTION REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " SYNC ,dgpio sync irq error injection"
|
|
hexmask.long.word 0x00 0.--15. 1. " ASYNC ,async irq error injection"
|
|
group ad:0xF0740F20++0x03
|
|
line.long 0x00 "DGPIO_SINT_GRP_INJ,DGPIO SYNC GROUP INTERRUPT INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GRP ,dgpio grp interrupt error injection"
|
|
group ad:0xF0740F24++0x03
|
|
line.long 0x00 "DGPIO_SINT_GRP_INJ,DGPIO SYNC GROUP INTERRUPT INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GRP ,dgpio grp interrupt error injection"
|
|
group ad:0xF0740F30++0x03
|
|
line.long 0x00 "DGPIO_AINT_GRP_INJ,DGPIO ASYNC GROUP INTERRUPT INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GRP ,dgpio grp interrupt error injection"
|
|
group ad:0xF0740F34++0x03
|
|
line.long 0x00 "DGPIO_AINT_GRP_INJ,DGPIO ASYNC GROUP INTERRUPT INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GRP ,dgpio grp interrupt error injection"
|
|
group ad:0xF0740F40++0x03
|
|
line.long 0x00 "DGPIO_E2E_INT_INJ,DGPIO E2E INTERRUPT INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INJ_IRQ ,e2e irq error injection bit[7:3]: reserved bit2: permission error injection bit1: unc error injection bit0: cor error enjection"
|
|
group ad:0xF0740F50++0x03
|
|
line.long 0x00 "PRDATAINJ,PRDATA ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 0. " B0 ,prdata error injection register write 1 to inject error for prdata when err_inj_en is set to 1" "0,1"
|
|
group ad:0xF0740F60++0x03
|
|
line.long 0x00 "GPIO_INT_DGSEL,GPIO INT DGSEL ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio int dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,gpio int dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,gpio int permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740F64++0x03
|
|
line.long 0x00 "GPIO_INT,GPIO INTERRUPT REGISTER"
|
|
bitfld.long 0x00 8. " PER_ERR_STA ,Permission error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 0. " PER_ERR_EN ,Permission error enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF0740F70++0x03
|
|
line.long 0x00 "GPIO_MISC_DGSEL,GPIO MISC DGSEL ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio misc dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,gpio misc dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,gpio misc permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF0740F74++0x03
|
|
line.long 0x00 "GPIO_MISC,GPIO MISC REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MISC ,misc register bit0: permission error to slave error enable"
|
|
group ad:0xF0740F80++0x03
|
|
line.long 0x00 "SGPIO_SUP_DOM,SGPIO SUPER DOMAIN REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock the entire register" "0,1"
|
|
bitfld.long 0x00 5.--6. " PPROT ,pprot for super doman" "0,1,2,3"
|
|
bitfld.long 0x00 4. " SEC_EN ,check pprot enable" "0,1"
|
|
bitfld.long 0x00 0.--3. " DID ,super domain domain id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0740FA0++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF0740FA4++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF0741000++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741004++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741008++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074100C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741010++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741014++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741018++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074101C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741020++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741024++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741028++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074102C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741030++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741034++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741038++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074103C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741040++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741044++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741048++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074104C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741050++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741054++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741058++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074105C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741060++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741064++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741068++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074106C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741070++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741074++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741078++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074107C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741080++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741084++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741088++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074108C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741090++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741094++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741098++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074109C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410A0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410A4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410A8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410AC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410B0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410B4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410B8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410BC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410C0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410C4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410C8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410CC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410D0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410D4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410D8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410DC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410E0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410E4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410E8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410EC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410F0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410F4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410F8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07410FC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741100++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741104++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741108++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074110C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741110++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741114++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741118++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074111C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741120++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741124++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741128++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074112C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741130++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741134++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741138++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074113C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741140++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741144++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741148++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074114C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741150++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741154++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741158++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074115C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741160++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741164++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741168++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074116C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741170++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741174++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741178++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074117C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741180++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741184++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741188++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074118C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741190++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741194++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF0741198++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF074119C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411A0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411A4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411A8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411AC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411B0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411B4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411B8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411BC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411C0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411C4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411C8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411CC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411D0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411D4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411D8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411DC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411E0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411E4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411E8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411EC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411F0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411F4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411F8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF07411FC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
tree.end
|
|
tree "GPIO_AP"
|
|
width 27.
|
|
group ad:0xF3120000++0x03
|
|
line.long 0x00 "DOM_PER0_0,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120004++0x03
|
|
line.long 0x00 "DOM_PER1_0,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120008++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_0,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF312000C++0x03
|
|
line.long 0x00 "DOM_PER0_1,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120010++0x03
|
|
line.long 0x00 "DOM_PER1_1,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120014++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_1,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF3120018++0x03
|
|
line.long 0x00 "DOM_PER0_2,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF312001C++0x03
|
|
line.long 0x00 "DOM_PER1_2,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120020++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_2,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF3120024++0x03
|
|
line.long 0x00 "DOM_PER0_3,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120028++0x03
|
|
line.long 0x00 "DOM_PER1_3,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF312002C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_3,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF3120030++0x03
|
|
line.long 0x00 "DOM_PER0_4,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120034++0x03
|
|
line.long 0x00 "DOM_PER1_4,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120038++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_4,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF312003C++0x03
|
|
line.long 0x00 "DOM_PER0_5,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120040++0x03
|
|
line.long 0x00 "DOM_PER1_5,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120044++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_5,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF3120048++0x03
|
|
line.long 0x00 "DOM_PER0_6,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF312004C++0x03
|
|
line.long 0x00 "DOM_PER1_6,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120050++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_6,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF3120054++0x03
|
|
line.long 0x00 "DOM_PER0_7,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120058++0x03
|
|
line.long 0x00 "DOM_PER1_7,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF312005C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_7,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF3120060++0x03
|
|
line.long 0x00 "DOM_PER0_8,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120064++0x03
|
|
line.long 0x00 "DOM_PER1_8,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120068++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_8,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF312006C++0x03
|
|
line.long 0x00 "DOM_PER0_9,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120070++0x03
|
|
line.long 0x00 "DOM_PER1_9,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120074++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_9,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF3120078++0x03
|
|
line.long 0x00 "DOM_PER0_10,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF312007C++0x03
|
|
line.long 0x00 "DOM_PER1_10,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120080++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_10,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF3120084++0x03
|
|
line.long 0x00 "DOM_PER0_11,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120088++0x03
|
|
line.long 0x00 "DOM_PER1_11,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF312008C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_11,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF3120090++0x03
|
|
line.long 0x00 "DOM_PER0_12,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120094++0x03
|
|
line.long 0x00 "DOM_PER1_12,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF3120098++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_12,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF312009C++0x03
|
|
line.long 0x00 "DOM_PER0_13,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF31200A0++0x03
|
|
line.long 0x00 "DOM_PER1_13,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF31200A4++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_13,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF31200A8++0x03
|
|
line.long 0x00 "DOM_PER0_14,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF31200AC++0x03
|
|
line.long 0x00 "DOM_PER1_14,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF31200B0++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_14,This register is used to lock domain access permission setting."
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|
bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
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|
bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
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|
bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
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|
bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
|
|
group ad:0xF31200B4++0x03
|
|
line.long 0x00 "DOM_PER0_15,This register is used for to control domain0~3 secure and priviledge access permission."
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|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF31200B8++0x03
|
|
line.long 0x00 "DOM_PER1_15,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
group ad:0xF31200BC++0x03
|
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line.long 0x00 "DOM_PER_LOCK_15,This register is used to lock domain access permission setting."
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bitfld.long 0x00 7. " DOM_LOCK_7 ,lock domain access permission setting." "0,1"
|
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bitfld.long 0x00 6. " DOM_LOCK_6 ,lock domain access permission setting." "0,1"
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bitfld.long 0x00 5. " DOM_LOCK_5 ,lock domain access permission setting." "0,1"
|
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bitfld.long 0x00 4. " DOM_LOCK_4 ,lock domain access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM_LOCK_3 ,lock domain access permission setting." "0,1"
|
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bitfld.long 0x00 2. " DOM_LOCK_2 ,lock domain access permission setting." "0,1"
|
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bitfld.long 0x00 1. " DOM_LOCK_1 ,lock domain access permission setting." "0,1"
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bitfld.long 0x00 0. " DOM_LOCK_0 ,lock domain access permission setting." "0,1"
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group ad:0xF3120140++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
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group ad:0xF3120144++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
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group ad:0xF3120148++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
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group ad:0xF312014C++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120150++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
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bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120154++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120158++0x03
|
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line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312015C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120160++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120164++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120168++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312016C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120170++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120174++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120178++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312017C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120180++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120184++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120188++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312018C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120190++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120194++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120198++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312019C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201A0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201A4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201A8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201AC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201B0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201B4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201B8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201BC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201C0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201C4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201C8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201CC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201D0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201D4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201D8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201DC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201E0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201E4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201E8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201EC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201F0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201F4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201F8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31201FC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120200++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120204++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120208++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312020C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120210++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120214++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120218++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312021C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120220++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120224++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120228++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312022C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120230++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120234++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120238++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312023C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120240++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120244++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120248++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312024C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120250++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120254++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120258++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312025C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120260++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120264++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120268++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312026C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120270++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120274++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120278++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312027C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120280++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120284++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120288++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312028C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120290++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120294++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120298++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312029C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202A0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202A4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202A8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202AC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202B0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202B4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202B8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202BC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202C0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202C4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202C8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202CC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202D0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202D4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202D8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202DC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202E0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202E4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202E8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202EC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202F0++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202F4++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202F8++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF31202FC++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120300++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120304++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120308++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312030C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120310++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120314++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120318++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312031C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120320++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120324++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120328++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312032C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120330++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120334++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120338++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF312033C++0x03
|
|
line.long 0x00 "SGPIO_GPIO_DGSEL,SGPIO GPIO DGPIO ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,Gpio dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,Gpio permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120580++0x03
|
|
line.long 0x00 "GPIO_OEN_0,GPIO OUTPUT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " OEN ,Output enable"
|
|
group ad:0xF3120590++0x03
|
|
line.long 0x00 "GPIO_OEN_1,GPIO OUTPUT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " OEN ,Output enable"
|
|
group ad:0xF31205A0++0x03
|
|
line.long 0x00 "GPIO_OEN_2,GPIO OUTPUT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " OEN ,Output enable"
|
|
group ad:0xF31205B0++0x03
|
|
line.long 0x00 "GPIO_OEN_3,GPIO OUTPUT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " OEN ,Output enable"
|
|
group ad:0xF3120600++0x03
|
|
line.long 0x00 "GPIO_DATA_IN_0,GPIO DATA INPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DIN ,Gpio data input"
|
|
group ad:0xF3120610++0x03
|
|
line.long 0x00 "GPIO_DATA_IN_1,GPIO DATA INPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DIN ,Gpio data input"
|
|
group ad:0xF3120620++0x03
|
|
line.long 0x00 "GPIO_DATA_IN_2,GPIO DATA INPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DIN ,Gpio data input"
|
|
group ad:0xF3120630++0x03
|
|
line.long 0x00 "GPIO_DATA_IN_3,GPIO DATA INPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DIN ,Gpio data input"
|
|
group ad:0xF3120680++0x03
|
|
line.long 0x00 "GPIO_DATA_OUT_0,GPIO DATA OUTPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DOUT ,Gpio data output"
|
|
group ad:0xF3120690++0x03
|
|
line.long 0x00 "GPIO_DATA_OUT_1,GPIO DATA OUTPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DOUT ,Gpio data output"
|
|
group ad:0xF31206A0++0x03
|
|
line.long 0x00 "GPIO_DATA_OUT_2,GPIO DATA OUTPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DOUT ,Gpio data output"
|
|
group ad:0xF31206B0++0x03
|
|
line.long 0x00 "GPIO_DATA_OUT_3,GPIO DATA OUTPUT REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DOUT ,Gpio data output"
|
|
group ad:0xF3120700++0x03
|
|
line.long 0x00 "GPIO_SINT_EN_0,GPIO SYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Synchronous interrupt enable"
|
|
group ad:0xF3120710++0x03
|
|
line.long 0x00 "GPIO_SINT_EN_1,GPIO SYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Synchronous interrupt enable"
|
|
group ad:0xF3120720++0x03
|
|
line.long 0x00 "GPIO_SINT_EN_2,GPIO SYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Synchronous interrupt enable"
|
|
group ad:0xF3120730++0x03
|
|
line.long 0x00 "GPIO_SINT_EN_3,GPIO SYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Synchronous interrupt enable"
|
|
group ad:0xF3120780++0x03
|
|
line.long 0x00 "GPIO_SINT_MASK_0,GPIO SYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Synchronous interrupt mask"
|
|
group ad:0xF3120790++0x03
|
|
line.long 0x00 "GPIO_SINT_MASK_1,GPIO SYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Synchronous interrupt mask"
|
|
group ad:0xF31207A0++0x03
|
|
line.long 0x00 "GPIO_SINT_MASK_2,GPIO SYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Synchronous interrupt mask"
|
|
group ad:0xF31207B0++0x03
|
|
line.long 0x00 "GPIO_SINT_MASK_3,GPIO SYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Synchronous interrupt mask"
|
|
group ad:0xF3120800++0x03
|
|
line.long 0x00 "GPIO_SINT_TYPE_0,GPIO SYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Synchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF3120810++0x03
|
|
line.long 0x00 "GPIO_SINT_TYPE_1,GPIO SYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Synchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF3120820++0x03
|
|
line.long 0x00 "GPIO_SINT_TYPE_2,GPIO SYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Synchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF3120830++0x03
|
|
line.long 0x00 "GPIO_SINT_TYPE_3,GPIO SYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Synchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF3120880++0x03
|
|
line.long 0x00 "GPIO_SINT_POL_0,GPIO SYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Synchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF3120890++0x03
|
|
line.long 0x00 "GPIO_SINT_POL_1,GPIO SYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Synchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF31208A0++0x03
|
|
line.long 0x00 "GPIO_SINT_POL_2,GPIO SYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Synchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF31208B0++0x03
|
|
line.long 0x00 "GPIO_SINT_POL_3,GPIO SYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Synchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF3120900++0x03
|
|
line.long 0x00 "GPIO_SINT_BOE_0,GPIO SYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Synchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF3120910++0x03
|
|
line.long 0x00 "GPIO_SINT_BOE_1,GPIO SYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Synchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF3120920++0x03
|
|
line.long 0x00 "GPIO_SINT_BOE_2,GPIO SYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Synchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF3120930++0x03
|
|
line.long 0x00 "GPIO_SINT_BOE_3,GPIO SYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Synchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF3120980++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_0,GPIO SYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Synchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120990++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_1,GPIO SYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Synchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF31209A0++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_2,GPIO SYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Synchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF31209B0++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_3,GPIO SYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Synchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120A00++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_UNMASK_0,GPIO SYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_MASK ,Synchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120A10++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_UNMASK_1,GPIO SYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_MASK ,Synchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120A20++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_UNMASK_2,GPIO SYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_MASK ,Synchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120A30++0x03
|
|
line.long 0x00 "GPIO_SINT_STATUS_UNMASK_3,GPIO SYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_MASK ,Synchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120A80++0x03
|
|
line.long 0x00 "GPIO_SINT_EDGE_CLR_0,GPIO SYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Synchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF3120A90++0x03
|
|
line.long 0x00 "GPIO_SINT_EDGE_CLR_1,GPIO SYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Synchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF3120AA0++0x03
|
|
line.long 0x00 "GPIO_SINT_EDGE_CLR_2,GPIO SYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Synchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF3120AB0++0x03
|
|
line.long 0x00 "GPIO_SINT_EDGE_CLR_3,GPIO SYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Synchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF3120B00++0x03
|
|
line.long 0x00 "GPIO_AINT_EN_0,GPIO ASYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Asynchronous interrupt enable"
|
|
group ad:0xF3120B10++0x03
|
|
line.long 0x00 "GPIO_AINT_EN_1,GPIO ASYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Asynchronous interrupt enable"
|
|
group ad:0xF3120B20++0x03
|
|
line.long 0x00 "GPIO_AINT_EN_2,GPIO ASYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Asynchronous interrupt enable"
|
|
group ad:0xF3120B30++0x03
|
|
line.long 0x00 "GPIO_AINT_EN_3,GPIO ASYNC INTERRUPT ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_EN ,Asynchronous interrupt enable"
|
|
group ad:0xF3120B80++0x03
|
|
line.long 0x00 "GPIO_AINT_MASK_0,GPIO ASYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Asynchronous interrupt mask"
|
|
group ad:0xF3120B90++0x03
|
|
line.long 0x00 "GPIO_AINT_MASK_1,GPIO ASYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Asynchronous interrupt mask"
|
|
group ad:0xF3120BA0++0x03
|
|
line.long 0x00 "GPIO_AINT_MASK_2,GPIO ASYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Asynchronous interrupt mask"
|
|
group ad:0xF3120BB0++0x03
|
|
line.long 0x00 "GPIO_AINT_MASK_3,GPIO ASYNC INTERRUPT MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_MASK ,Asynchronous interrupt mask"
|
|
group ad:0xF3120C00++0x03
|
|
line.long 0x00 "GPIO_AINT_TYPE_0,GPIO ASYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Asynchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF3120C10++0x03
|
|
line.long 0x00 "GPIO_AINT_TYPE_1,GPIO ASYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Asynchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF3120C20++0x03
|
|
line.long 0x00 "GPIO_AINT_TYPE_2,GPIO ASYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Asynchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF3120C30++0x03
|
|
line.long 0x00 "GPIO_AINT_TYPE_3,GPIO ASYNC INTERRUPT TYPE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_TYPE ,Asynchronous interrupt type 0: level mode 1: pulse mode"
|
|
group ad:0xF3120C80++0x03
|
|
line.long 0x00 "GPIO_AINT_POL_0,GPIO ASYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Asynchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF3120C90++0x03
|
|
line.long 0x00 "GPIO_AINT_POL_1,GPIO ASYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Asynchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF3120CA0++0x03
|
|
line.long 0x00 "GPIO_AINT_POL_2,GPIO ASYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Asynchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF3120CB0++0x03
|
|
line.long 0x00 "GPIO_AINT_POL_3,GPIO ASYNC INTERRUPT POLARITY REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_POL ,Asynchronous interrupt polarity 0: low active or negedge active 1: high active or posedge active"
|
|
group ad:0xF3120D00++0x03
|
|
line.long 0x00 "GPIO_AINT_BOE_0,GPIO ASYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Asynchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF3120D10++0x03
|
|
line.long 0x00 "GPIO_AINT_BOE_1,GPIO ASYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Asynchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF3120D20++0x03
|
|
line.long 0x00 "GPIO_AINT_BOE_2,GPIO ASYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Asynchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF3120D30++0x03
|
|
line.long 0x00 "GPIO_AINT_BOE_3,GPIO ASYNC INTERRUPT BOTH EDGE ENABLE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_BOE ,Asynchronous interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive"
|
|
group ad:0xF3120D80++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_0,GPIO ASYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Asynchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120D90++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_1,GPIO ASYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Asynchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120DA0++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_2,GPIO ASYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Asynchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120DB0++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_3,GPIO ASYNC INTERRUPT STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS ,Asynchronous interrupt status. 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120E00++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_UNMASK_0,GPIO ASYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_UNMASK ,Asynchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120E10++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_UNMASK_1,GPIO ASYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_UNMASK ,Asynchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120E20++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_UNMASK_2,GPIO ASYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_UNMASK ,Asynchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120E30++0x03
|
|
line.long 0x00 "GPIO_AINT_STATUS_UNMASK_3,GPIO ASYNC INTERRUPT UNMASK STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS_UNMASK ,Asynchronous interrupt unmasked status 0: interrupt not active 1: interrupt active"
|
|
group ad:0xF3120E80++0x03
|
|
line.long 0x00 "GPIO_AINT_EDGE_CLR_0,GPIO ASYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Asynchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF3120E90++0x03
|
|
line.long 0x00 "GPIO_AINT_EDGE_CLR_1,GPIO ASYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Asynchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF3120EA0++0x03
|
|
line.long 0x00 "GPIO_AINT_EDGE_CLR_2,GPIO ASYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Asynchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF3120EB0++0x03
|
|
line.long 0x00 "GPIO_AINT_EDGE_CLR_3,GPIO ASYNC INTERRUPT CLEAR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " INT_CLR ,Asynchronous edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear"
|
|
group ad:0xF3120F00++0x03
|
|
line.long 0x00 "ERR_INJ_DGSEL,ERROR INJECTION DGSEL ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for error injection dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,error injection dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,error injection permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120F08++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF3120F0C++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF3120F10++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF3120F14++0x03
|
|
line.long 0x00 "GPIO_FUSA_INT,GPIO FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,Sync error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,Sync error enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF3120F18++0x03
|
|
line.long 0x00 "GPIO_INJ_EN,GPIO ERROR INJECTION ENABLE REGISTER"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INJ_EN ,Error injection enable. bit0: irq error injection enable bit1: apb error injection enable bit[7:2] reserved"
|
|
group ad:0xF3120F1C++0x03
|
|
line.long 0x00 "DGPIO_INT_INJ,DGPIO INTERRUPT INJECTION REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " SYNC ,dgpio sync irq error injection"
|
|
hexmask.long.word 0x00 0.--15. 1. " ASYNC ,async irq error injection"
|
|
group ad:0xF3120F20++0x03
|
|
line.long 0x00 "DGPIO_SINT_GRP_INJ,DGPIO SYNC GROUP INTERRUPT INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GRP ,dgpio grp interrupt error injection"
|
|
group ad:0xF3120F24++0x03
|
|
line.long 0x00 "DGPIO_SINT_GRP_INJ,DGPIO SYNC GROUP INTERRUPT INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GRP ,dgpio grp interrupt error injection"
|
|
group ad:0xF3120F30++0x03
|
|
line.long 0x00 "DGPIO_AINT_GRP_INJ,DGPIO ASYNC GROUP INTERRUPT INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GRP ,dgpio grp interrupt error injection"
|
|
group ad:0xF3120F34++0x03
|
|
line.long 0x00 "DGPIO_AINT_GRP_INJ,DGPIO ASYNC GROUP INTERRUPT INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GRP ,dgpio grp interrupt error injection"
|
|
group ad:0xF3120F40++0x03
|
|
line.long 0x00 "DGPIO_E2E_INT_INJ,DGPIO E2E INTERRUPT INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INJ_IRQ ,e2e irq error injection bit[7:3]: reserved bit2: permission error injection bit1: unc error injection bit0: cor error enjection"
|
|
group ad:0xF3120F50++0x03
|
|
line.long 0x00 "PRDATAINJ,PRDATA ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 0. " B0 ,prdata error injection register write 1 to inject error for prdata when err_inj_en is set to 1" "0,1"
|
|
group ad:0xF3120F60++0x03
|
|
line.long 0x00 "GPIO_INT_DGSEL,GPIO INT DGSEL ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio int dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,gpio int dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,gpio int permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120F64++0x03
|
|
line.long 0x00 "GPIO_INT,GPIO INTERRUPT REGISTER"
|
|
bitfld.long 0x00 8. " PER_ERR_STA ,Permission error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 0. " PER_ERR_EN ,Permission error enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF3120F70++0x03
|
|
line.long 0x00 "GPIO_MISC_DGSEL,GPIO MISC DGSEL ALLOCATION REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit for gpio misc dgpio" "0,1"
|
|
bitfld.long 0x00 1.--4. " DGSEL ,gpio misc dgpio information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,gpio misc permission control enable 1: permission align with DGSEL 0: share with all DID" "0,1"
|
|
group ad:0xF3120F74++0x03
|
|
line.long 0x00 "GPIO_MISC,GPIO MISC REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MISC ,misc register bit0: permission error to slave error enable"
|
|
group ad:0xF3120F80++0x03
|
|
line.long 0x00 "SGPIO_SUP_DOM,SGPIO SUPER DOMAIN REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock the entire register" "0,1"
|
|
bitfld.long 0x00 5.--6. " PPROT ,pprot for super doman" "0,1,2,3"
|
|
bitfld.long 0x00 4. " SEC_EN ,check pprot enable" "0,1"
|
|
bitfld.long 0x00 0.--3. " DID ,super domain domain id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF3120FA0++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF3120FA4++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF3121000++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121004++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121008++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312100C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121010++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121014++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121018++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312101C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121020++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121024++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121028++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312102C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121030++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121034++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121038++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312103C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121040++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121044++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121048++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312104C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121050++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121054++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121058++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312105C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121060++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121064++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121068++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312106C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121070++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121074++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121078++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312107C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121080++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121084++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121088++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312108C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121090++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121094++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121098++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312109C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210A0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210A4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210A8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210AC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210B0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210B4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210B8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210BC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210C0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210C4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210C8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210CC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210D0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210D4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210D8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210DC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210E0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210E4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210E8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210EC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210F0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210F4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210F8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31210FC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121100++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121104++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121108++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312110C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121110++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121114++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121118++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312111C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121120++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121124++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121128++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312112C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121130++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121134++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121138++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312113C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121140++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121144++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121148++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312114C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121150++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121154++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121158++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312115C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121160++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121164++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121168++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312116C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121170++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121174++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121178++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312117C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121180++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121184++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121188++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312118C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121190++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121194++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF3121198++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF312119C++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211A0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211A4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211A8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211AC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211B0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211B4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211B8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211BC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211C0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211C4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211C8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211CC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211D0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211D4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211D8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211DC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211E0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211E4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211E8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211EC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211F0++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211F4++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211F8++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
group ad:0xF31211FC++0x03
|
|
line.long 0x00 "GPIO_INT_SHARE,GPIO INTERRUPT SHARE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock bit for EN" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EN ,interrupt share with DGPIO0~15 enable, such as: bit 0 -- DGPIO0. the bit for dgpio of the gpio itself is reserved."
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "IOMUX"
|
|
tree "IOMUX_SF"
|
|
width 28.
|
|
group ad:0xF0631000++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO0,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631004++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO1,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631008++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO2,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063100C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO3,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631010++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO4,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631014++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO5,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631018++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO6,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063101c++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO7,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631020++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO8,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631024++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO9,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631028++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO10,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063102C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO11,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631030++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO12,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631034++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO13,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631038++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO14,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063103C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO15,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631040++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO16,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631044++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO17,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631048++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO18,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063104C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO19,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631050++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO20,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631054++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO21,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631058++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO22,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063105C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO23,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631060++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO24,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631064++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO25,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631068++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO26,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063106C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO27,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631070++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO28,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631074++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO29,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631078++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO30,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063107C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO31,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631080++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO32,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631084++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO33,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631088++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO34,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063108C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO35,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631090++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO36,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631094++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO37,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631098++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO38,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063109C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO39,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310A0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO40,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310A4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO41,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310A8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO42,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310AC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO43,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310B0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO44,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310B4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO45,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310B8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO46,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310BC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO47,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310C0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO48,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310C4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO49,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310C8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO50,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310CC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO51,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310D0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO52,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310D4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO53,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310D8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO54,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310DC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO55,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310E0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO56,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310E4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO57,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310E8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO58,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310EC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO59,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310F0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO60,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310F4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO61,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310F8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO62,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06310FC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO63,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631100++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO64,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631104++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO65,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631108++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO66,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063110C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO67,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631110++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO68,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631114++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO69,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631118++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO70,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063111C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO71,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631120++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO72,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631124++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO73,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631128++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO74,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063112C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO75,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631130++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO76,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631134++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO77,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631138++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO78,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063113C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO79,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631140++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO80,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631144++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO81,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631148++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO82,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063114C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO83,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631150++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO84,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631154++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO85,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631158++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO86,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063115C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO87,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631160++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO88,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631164++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO89,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631168++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO90,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063116C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO91,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631170++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO92,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631174++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO93,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631178++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO94,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063117C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO95,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631180++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO96,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631184++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO97,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631188++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO98,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063118C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO99,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631190++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO100,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631194++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO101,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631198++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO102,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063119C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO103,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311A0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO104,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311A4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO105,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311A8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO106,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311AC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO107,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311B0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO108,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311B4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO109,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311B8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO110,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311BC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO111,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311C0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO112,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311C4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO113,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311C8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO114,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311CC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO115,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311D0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO116,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311D4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO117,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311D8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO118,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311DC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO119,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311E0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO120,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311E4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO121,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311E8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO122,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311EC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO123,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311F0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO124,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311F4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO125,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311F8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO126,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF06311FC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO127,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631200++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO128,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631204++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO129,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631208++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO130,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF063120C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO131,IO PAD config register"
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|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631210++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO132,IO PAD config register"
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|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
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|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
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|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631214++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO133,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
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|
textline " "
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|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0631218++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO134,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF0632000++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO0,pin mux config"
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bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632004++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO1,Ipin mux config"
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|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632008++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO2,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063200C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO3,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632010++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO4,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632014++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO5,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632018++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO6,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063201c++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO7,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632020++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO8,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632024++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO9,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632028++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO10,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063202C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO11,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632030++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO12,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632034++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO13,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632038++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO14,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063203C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO15,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632040++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO16,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632044++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO17,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632048++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO18,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063204C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO19,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632050++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO20,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632054++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO21,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632058++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO22,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063205C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO23,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632060++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO24,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632064++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO25,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632068++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO26,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063206C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO27,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632070++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO28,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632074++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO29,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632078++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO30,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063207C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO31,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632080++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO32,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632084++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO33,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632088++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO34,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063208C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO35,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632090++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO36,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632094++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO37,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632098++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO38,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063209C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO39,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320A0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO40,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320A4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO41,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320A8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO42,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320AC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO43,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320B0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO44,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320B4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO45,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320B8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO46,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320BC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO47,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320C0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO48,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320C4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO49,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320C8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO50,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320CC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO51,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320D0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO52,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320D4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO53,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320D8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO54,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320DC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO55,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320E0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO56,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320E4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO57,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320E8++0x03
|
|
line.long 0x00 "PMUX_CONFIG_IO58,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320EC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO59,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320F0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO60,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320F4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO61,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320F8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO62,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06320FC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO63,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632100++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO64,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632104++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO65,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632108++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO66,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063210C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO67,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632110++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO68,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632114++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO69,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632118++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO70,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063211C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO71,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632120++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO72,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632124++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO73,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632128++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO74,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063212C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO75,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632130++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO76,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632134++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO77,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632138++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO78,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063213C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO79,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632140++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO80,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632144++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO81,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632148++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO82,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063214C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO83,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632150++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO84,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632154++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO85,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632158++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO86,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063215C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO87,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632160++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO88,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632164++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO89,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632168++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO90,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063216C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO91,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632170++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO92,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632174++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO93,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632178++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO94,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063217C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO95,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632180++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO96,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632184++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO97,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632188++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO98,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063218C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO99,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632190++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO100,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632194++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO101,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632198++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO102,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063219C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO103,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321A0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO104,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321A4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO105,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321A8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO106,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321AC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO107,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321B0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO108,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321B4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO109,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321B8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO110,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321BC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO111,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321C0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO112,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321C4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO113,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321C8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO114,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321CC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO115,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321D0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO116,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321D4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO117,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321D8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO118,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321DC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO119,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321E0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO120,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321E4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO121,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321E8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO122,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321EC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO123,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321F0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO124,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321F4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO125,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321F8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO126,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06321FC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO127,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632200++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO128,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632204++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO129,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632208++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO130,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063220C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO131,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632210++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO132,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632214++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO133,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0632218++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO134,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633000++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO0,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633004++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO1,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633008++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO2,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063300C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO3,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633010++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO4,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633014++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO5,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633018++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO6,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063301c++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO7,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633020++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO8,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633024++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO9,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633028++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO10,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063302C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO11,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633030++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO12,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633034++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO13,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633038++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO14,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063303C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO15,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633040++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO16,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633044++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO17,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633048++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO18,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063304C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO19,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633050++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO20,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633054++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO21,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633058++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO22,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063305C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO23,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633060++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO24,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633064++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO25,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633068++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO26,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063306C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO27,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633070++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO28,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633074++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO29,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633078++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO30,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063307C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO31,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633080++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO32,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633084++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO33,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633088++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO34,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063308C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO35,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633090++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO36,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633094++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO37,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633098++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO38,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063309C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO39,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330A0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO40,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330A4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO41,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330A8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO42,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330AC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO43,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330B0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO44,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330B4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO45,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330B8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO46,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330BC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO47,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330C0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO48,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330C4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO49,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330C8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO50,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330CC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO51,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330D0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO52,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330D4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO53,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330D8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO54,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330DC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO55,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330E0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO56,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330E4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO57,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330E8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO58,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330EC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO59,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330F0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO60,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330F4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO61,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330F8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO62,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06330FC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO63,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633100++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO64,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633104++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO65,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633108++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO66,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063310C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO67,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633110++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO68,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633114++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO69,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633118++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO70,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063311C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO71,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633120++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO72,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633124++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO73,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633128++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO74,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063312C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO75,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633130++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO76,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633134++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO77,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633138++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO78,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063313C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO79,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633140++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO80,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633144++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO81,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633148++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO82,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063314C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO83,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633150++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO84,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633154++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO85,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633158++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO86,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063315C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO87,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633160++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO88,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633164++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO89,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633168++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO90,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063316C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO91,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633170++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO92,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633174++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO93,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633178++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO94,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063317C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO95,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633180++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO96,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633184++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO97,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633188++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO98,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063318C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO99,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633190++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO100,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633194++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO101,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633198++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO102,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063319C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO103,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331A0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO104,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331A4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO105,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331A8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO106,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331AC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO107,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331B0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO108,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331B4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO109,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331B8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO110,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331BC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO111,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331C0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO112,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331C4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO113,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331C8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO114,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331CC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO115,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331D0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO116,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331D4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO117,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331D8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO118,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331DC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO119,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331E0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO120,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331E4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO121,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331E8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO122,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331EC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO123,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331F0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO124,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331F4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO125,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331F8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO126,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF06331FC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO127,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633200++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO128,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633204++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO129,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633208++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO130,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF063320C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO131,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633210++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO132,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633214++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO133,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0633218++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO134,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "IOMUX_AP"
|
|
width 28.
|
|
group ad:0xF30E1000++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO0,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1004++0x03
|
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line.long 0x00 "PAD_CONFIG_IO1,IO PAD config register"
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1008++0x03
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|
line.long 0x00 "PAD_CONFIG_IO2,IO PAD config register"
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
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|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E100C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO3,IO PAD config register"
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1010++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO4,IO PAD config register"
|
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1014++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO5,IO PAD config register"
|
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1018++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO6,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E101c++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO7,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1020++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO8,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1024++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO9,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1028++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO10,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E102C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO11,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1030++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO12,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1034++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO13,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1038++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO14,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E103C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO15,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1040++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO16,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1044++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO17,IO PAD config register"
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1048++0x03
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line.long 0x00 "PAD_CONFIG_IO18,IO PAD config register"
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
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|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
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|
textline " "
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bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
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|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E104C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO19,IO PAD config register"
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
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|
textline " "
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bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
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|
group ad:0xF30E1050++0x03
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line.long 0x00 "PAD_CONFIG_IO20,IO PAD config register"
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
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bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1054++0x03
|
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line.long 0x00 "PAD_CONFIG_IO21,IO PAD config register"
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
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|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
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bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1058++0x03
|
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line.long 0x00 "PAD_CONFIG_IO22,IO PAD config register"
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
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bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
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bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E105C++0x03
|
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line.long 0x00 "PAD_CONFIG_IO23,IO PAD config register"
|
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1060++0x03
|
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line.long 0x00 "PAD_CONFIG_IO24,IO PAD config register"
|
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1064++0x03
|
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line.long 0x00 "PAD_CONFIG_IO25,IO PAD config register"
|
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bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
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bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1068++0x03
|
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line.long 0x00 "PAD_CONFIG_IO26,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E106C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO27,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1070++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO28,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1074++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO29,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1078++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO30,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E107C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO31,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1080++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO32,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1084++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO33,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1088++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO34,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E108C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO35,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1090++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO36,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1094++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO37,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1098++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO38,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E109C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO39,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10A0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO40,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10A4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO41,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10A8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO42,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10AC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO43,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10B0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO44,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10B4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO45,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10B8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO46,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10BC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO47,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10C0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO48,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10C4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO49,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10C8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO50,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10CC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO51,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10D0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO52,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10D4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO53,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10D8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO54,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10DC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO55,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10E0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO56,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10E4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO57,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10E8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO58,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10EC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO59,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10F0++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO60,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10F4++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO61,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10F8++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO62,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E10FC++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO63,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1100++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO64,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1104++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO65,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1108++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO66,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E110C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO67,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1110++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO68,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1114++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO69,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1118++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO70,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E111C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO71,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1120++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO72,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1124++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO73,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1128++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO74,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E112C++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO75,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1130++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO76,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1134++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO77,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E1138++0x03
|
|
line.long 0x00 "PAD_CONFIG_IO78,IO PAD config register"
|
|
bitfld.long 0x00 20. " MS ,PAD Mode select, Analog-DIgital combo IO only. -MS=0: Logic LOW passes PAD signal as is. -MS=1:Logic HIGH enble down coversion of PAD signal before passing to core." "0,1"
|
|
bitfld.long 0x00 16. " POE ,PAD Parametric output enable -POE=0: Parametric output DIsable -POE=1: Parametric output enable" "0,1"
|
|
bitfld.long 0x00 12. " IS ,PAD Input select -IS=1: CMOS Schmitt mode -IS=0: CMOS mode" "0,1"
|
|
bitfld.long 0x00 8. " SR ,PAD Slew rate -SR=0: Fast output slew rate -SR=1: Slow output slew rate" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. "DS ,PAD Driver select -DS=00: 2mA output drive strength -DS=10: 4mA output drive strength -DS=01: 8mA output drive strength -DS=11: 12mA output drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PS ,PAD Pull select -PS=1: Logic-HIGH selects pull up -PS=0: Logic-LOW selects pull donw" "0,1"
|
|
bitfld.long 0x00 0. " PE ,PAD Pull enable -PE=0: Logic-HIGH DIsable weak pull device -PE=1: Logic-HIGH enable weak pull device" "0,1"
|
|
group ad:0xF30E2000++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO0,pin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2004++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO1,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2008++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO2,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E200C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO3,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2010++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO4,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2014++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO5,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2018++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO6,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E201c++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO7,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2020++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO8,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2024++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO9,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2028++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO10,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E202C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO11,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2030++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO12,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2034++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO13,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2038++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO14,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E203C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO15,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2040++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO16,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2044++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO17,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2048++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO18,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E204C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO19,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2050++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO20,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2054++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO21,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2058++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO22,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E205C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO23,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2060++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO24,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2064++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO25,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2068++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO26,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E206C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO27,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2070++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO28,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2074++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO29,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2078++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO30,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E207C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO31,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2080++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO32,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2084++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO33,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2088++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO34,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E208C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO35,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2090++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO36,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2094++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO37,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2098++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO38,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E209C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO39,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20A0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO40,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20A4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO41,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20A8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO42,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20AC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO43,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20B0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO44,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20B4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO45,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20B8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO46,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20BC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO47,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20C0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO48,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20C4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO49,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20C8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO50,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20CC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO51,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20D0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO52,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20D4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO53,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20D8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO54,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20DC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO55,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20E0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO56,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20E4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO57,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20E8++0x03
|
|
line.long 0x00 "PMUX_CONFIG_IO58,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20EC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO59,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20F0++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO60,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20F4++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO61,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20F8++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO62,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E20FC++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO63,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2100++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO64,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2104++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO65,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2108++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO66,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E210C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO67,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2110++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO68,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2114++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO69,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2118++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO70,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E211C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO71,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2120++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO72,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2124++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO73,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2128++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO74,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E212C++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO75,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2130++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO76,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2134++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO77,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E2138++0x03
|
|
line.long 0x00 "MUX_CONFIG_IO78,Ipin mux config"
|
|
bitfld.long 0x00 31. " DO_FORCE_VALUE ,PAD DO force value in fault status. When DO_FORCE_EN=1; -DO_FORCE_VALUE=0: PAD fault status is 0 -DO_FORCE_VALUE=1: PAD fault status is 1" "0,1"
|
|
bitfld.long 0x00 30. " DO_FORCE_EN ,PAD DO force enable in fault status. -DO_FORCE_EN=0: PAD fault status configration DIsable -DO_FORCE_EN=1: PAD fault status configration enable" "0,1"
|
|
bitfld.long 0x00 29. " FV ,force input value. When FIN is 1. -FV=0: Input force value is 0. -FV=1: Input force value is 1." "0,1"
|
|
hexmask.long.word 0x00 10.--25. 1. " FIN_IP ,Force input on for each alt function"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. "FIN ,force input config -FIN=0: input force configration DIsable -FIN=1: input force configration enable" "0,1,2,3"
|
|
bitfld.long 0x00 4. " ODE ,open drain enable -ODE=1: enable -ODE=0: DIsable" "0,1"
|
|
bitfld.long 0x00 0.--3. " MUX ,function pin mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3000++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO0,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3004++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO1,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3008++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO2,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E300C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO3,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3010++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO4,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3014++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO5,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3018++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO6,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E301c++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO7,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3020++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO8,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3024++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO9,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3028++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO10,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E302C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO11,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3030++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO12,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3034++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO13,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3038++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO14,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E303C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO15,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3040++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO16,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3044++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO17,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3048++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO18,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E304C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO19,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3050++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO20,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3054++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO21,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3058++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO22,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E305C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO23,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3060++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO24,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3064++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO25,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3068++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO26,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E306C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO27,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3070++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO28,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3074++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO29,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3078++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO30,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E307C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO31,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3080++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO32,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3084++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO33,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3088++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO34,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E308C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO35,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3090++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO36,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3094++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO37,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3098++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO38,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E309C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO39,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30A0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO40,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30A4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO41,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30A8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO42,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30AC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO43,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30B0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO44,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30B4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO45,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30B8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO46,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30BC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO47,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30C0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO48,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30C4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO49,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30C8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO50,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30CC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO51,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30D0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO52,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30D4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO53,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30D8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO54,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30DC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO55,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30E0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO56,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30E4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO57,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30E8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO58,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30EC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO59,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30F0++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO60,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30F4++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO61,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30F8++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO62,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E30FC++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO63,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3100++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO64,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3104++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO65,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3108++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO66,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E310C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO67,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3110++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO68,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3114++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO69,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3118++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO70,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E311C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO71,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3120++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO72,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3124++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO73,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3128++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO74,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E312C++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO75,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3130++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO76,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3134++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO77,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30E3138++0x03
|
|
line.long 0x00 "INPUT_SELECT_IO78,input source select"
|
|
bitfld.long 0x00 0.--3. " SRC_SEL ,Input source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "MAC"
|
|
width 27.
|
|
group ad:0xF07B0000++0x03
|
|
line.long 0x00 "MDA_0,Assign domian for Master 0."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B0004++0x03
|
|
line.long 0x00 "MAA_0,Assign stream ID , secure/privileged attribute for master 0."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0008++0x03
|
|
line.long 0x00 "MDA_1,Assign domian for Master 1."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B000C++0x03
|
|
line.long 0x00 "MAA_1,Assign stream ID , secure/privileged attribute for master 1."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0010++0x03
|
|
line.long 0x00 "MDA_2,Assign domian for Master 2."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B0014++0x03
|
|
line.long 0x00 "MAA_2,Assign stream ID , secure/privileged attribute for master 2."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0018++0x03
|
|
line.long 0x00 "MDA_3,Assign domian for Master 3."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B001C++0x03
|
|
line.long 0x00 "MAA_3,Assign stream ID , secure/privileged attribute for master 3."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0020++0x03
|
|
line.long 0x00 "MDA_4,Assign domian for Master 4."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B0024++0x03
|
|
line.long 0x00 "MAA_4,Assign stream ID , secure/privileged attribute for master 4."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0028++0x03
|
|
line.long 0x00 "MDA_5,Assign domian for Master 5."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B002C++0x03
|
|
line.long 0x00 "MAA_5,Assign stream ID , secure/privileged attribute for master 5."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0030++0x03
|
|
line.long 0x00 "MDA_6,Assign domian for Master 6."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B0034++0x03
|
|
line.long 0x00 "MAA_6,Assign stream ID , secure/privileged attribute for master 6."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0038++0x03
|
|
line.long 0x00 "MDA_7,Assign domian for Master 7."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B003C++0x03
|
|
line.long 0x00 "MAA_7,Assign stream ID , secure/privileged attribute for master 7."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0040++0x03
|
|
line.long 0x00 "MDA_8,Assign domian for Master 8."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B0044++0x03
|
|
line.long 0x00 "MAA_8,Assign stream ID , secure/privileged attribute for master 8."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0048++0x03
|
|
line.long 0x00 "MDA_9,Assign domian for Master 9."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B004C++0x03
|
|
line.long 0x00 "MAA_9,Assign stream ID , secure/privileged attribute for master 9."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0050++0x03
|
|
line.long 0x00 "MDA_10,Assign domian for Master 10."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B0054++0x03
|
|
line.long 0x00 "MAA_10,Assign stream ID , secure/privileged attribute for master 10."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0058++0x03
|
|
line.long 0x00 "MDA_11,Assign domian for Master 11."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B005C++0x03
|
|
line.long 0x00 "MAA_11,Assign stream ID , secure/privileged attribute for master 11."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0060++0x03
|
|
line.long 0x00 "MDA_12,Assign domian for Master 12."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B0064++0x03
|
|
line.long 0x00 "MAA_12,Assign stream ID , secure/privileged attribute for master 12."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0068++0x03
|
|
line.long 0x00 "MDA_13,Assign domian for Master 13."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B006C++0x03
|
|
line.long 0x00 "MAA_13,Assign stream ID , secure/privileged attribute for master 13."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0070++0x03
|
|
line.long 0x00 "MDA_14,Assign domian for Master 14."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B0074++0x03
|
|
line.long 0x00 "MAA_14,Assign stream ID , secure/privileged attribute for master 14."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0078++0x03
|
|
line.long 0x00 "MDA_15,Assign domian for Master 15."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID for master" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B007C++0x03
|
|
line.long 0x00 "MAA_15,Assign stream ID , secure/privileged attribute for master 15."
|
|
bitfld.long 0x00 5. " PRI_LOCK ,Lock write for PRI_OV_EN and PRI bits." "0,1"
|
|
bitfld.long 0x00 4. " PRI_OV_EN ,Master privileged signal override enable" "0,1"
|
|
bitfld.long 0x00 3. " PRI ,0 : user access 1 : Privileged access" "0,1"
|
|
bitfld.long 0x00 2. " SEC_LOCK ,Lock write for SEC_OV_EN and SEC bits." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEC_OV_EN ,Master secure signal override enable" "0,1"
|
|
bitfld.long 0x00 0. " SEC ,0:Secure access 1: Non-secure access" "0,1"
|
|
group ad:0xF07B0200++0x03
|
|
line.long 0x00 "ACS_DID,The domain ID which is permitted to configure access control registers."
|
|
bitfld.long 0x00 31. " LOCK ,Lock write for DID" "0,1"
|
|
bitfld.long 0x00 0.--2. " DID ,Domain ID" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF07B02E0++0x03
|
|
line.long 0x00 "FUNC_INT_STA,Function interrupt status"
|
|
bitfld.long 0x00 1. " REG_ACS_ERR ,Register access error" "0,1"
|
|
bitfld.long 0x00 0. " XPC_ACS_ERR ,MPC/PPC access error" "0,1"
|
|
group ad:0xF07B02E4++0x03
|
|
line.long 0x00 "FUNC_INT_STA_EN,Function interrupt status enable"
|
|
bitfld.long 0x00 1. " REG_ACS_ERR ,Register access error" "0,1"
|
|
bitfld.long 0x00 0. " XPC_ACS_ERR ,MPC/PPC access error" "0,1"
|
|
group ad:0xF07B02E8++0x03
|
|
line.long 0x00 "FUNC_INT_SIG_EN,Function interrupt signal enable"
|
|
bitfld.long 0x00 1. " REG_ACS_ERR ,Register access error" "0,1"
|
|
bitfld.long 0x00 0. " XPC_ACS_ERR ,MPC/PPC access error" "0,1"
|
|
group ad:0xF07B03E0++0x03
|
|
line.long 0x00 "DOM_PER0,This register is used for to control function safety registers domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF07B03E4++0x03
|
|
line.long 0x00 "DOM_PER1,This register is used for to control function safety registers domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF07B03E8++0x03
|
|
line.long 0x00 "DOM_PER_LOCK,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF07B03FC++0x03
|
|
line.long 0x00 "RESP_ERR_DIS,DIsable response error."
|
|
bitfld.long 0x00 31. " ALL_LOCK ,Lock ALL_DIS configure" "0,1"
|
|
bitfld.long 0x00 30. " MAC_LOCK ,Lock MAC_DIS configure" "0,1"
|
|
bitfld.long 0x00 1. " ALL_DIS ,DIsable response error for all the registers access, incluDIng MAC, MPC and PPC." "0,1"
|
|
bitfld.long 0x00 0. " MAC_DIS ,DIsable response error for MAC register access." "0,1"
|
|
group ad:0xF07B0400++0x03
|
|
line.long 0x00 "FUSE_ERR_INT_STA,Fuse error interrupt status register"
|
|
bitfld.long 0x00 0. " FUSE_ERR ,Input fuse signals error" "0,1"
|
|
group ad:0xF07B0404++0x03
|
|
line.long 0x00 "FUSE_ERR_INT_STA_EN,Fuse error interrupt status enable register"
|
|
bitfld.long 0x00 0. " FUSE_ERR ,Input fuse signals error" "0,1"
|
|
group ad:0xF07B0408++0x03
|
|
line.long 0x00 "FUSE_ERR_INT_SIG_EN,Fuse error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " FUSE_ERR ,Input fuse signals error" "0,1"
|
|
group ad:0xF07B0410++0x03
|
|
line.long 0x00 "LSP_CMP_ERR_INT_STA,Lockstep compare error interrupt status register"
|
|
bitfld.long 0x00 5. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 4. " INT_SIG_ERR ,Internal signal compare error" "0,1"
|
|
bitfld.long 0x00 3. " IRQ_ERR ,Output signals compare error" "0,1"
|
|
bitfld.long 0x00 2. " MAS_ERR ,Output signals compare error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "APB_MAS_ERR ,Output signals compare error" "0,1"
|
|
bitfld.long 0x00 0. " APB_SLV_ERR ,Output signals compare error" "0,1"
|
|
group ad:0xF07B0414++0x03
|
|
line.long 0x00 "LSP_CMP_ERR_INT_STA_EN,Lockstep compare error interrupt status enable register"
|
|
bitfld.long 0x00 5. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 4. " INT_SIG_ERR ,Internal signal compare error" "0,1"
|
|
bitfld.long 0x00 3. " IRQ_ERR ,Ouput signals compare error" "0,1"
|
|
bitfld.long 0x00 2. " MAS_ERR ,Ouput signals compare error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "APB_MAS_ERR ,Ouput signals compare error" "0,1"
|
|
bitfld.long 0x00 0. " APB_SLV_ERR ,Ouput signals compare error" "0,1"
|
|
group ad:0xF07B0418++0x03
|
|
line.long 0x00 "LSP_CMP_ERR_INT_SIG_EN,Lockstep compare error interrupt signal enable register"
|
|
bitfld.long 0x00 5. " INPUT_ERR ,Input signal error" "0,1"
|
|
bitfld.long 0x00 4. " INT_SIG_ERR ,Internal signal compare error" "0,1"
|
|
bitfld.long 0x00 3. " IRQ_ERR ,Ouput signals compare error" "0,1"
|
|
bitfld.long 0x00 2. " MAS_ERR ,Ouput signals compare error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "APB_MAS_ERR ,Ouput signals compare error" "0,1"
|
|
bitfld.long 0x00 0. " APB_SLV_ERR ,Ouput signals compare error" "0,1"
|
|
group ad:0xF07B0420++0x03
|
|
line.long 0x00 "APB_SLV_ERR_INT_STA,Apb bus error interrupt status"
|
|
bitfld.long 0x00 5. " PUSER_UNCERR ,Puser parity error" "0,1"
|
|
bitfld.long 0x00 4. " PWDATA_FATAL ,Pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 3. " PWDATA_UNCERR ,Pwdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 2. " PWDATA_CORERR ,pwdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PCTL_UNCERR ,apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 0. " PADDR_UNCERR ,Paddr parity error" "0,1"
|
|
group ad:0xF07B0424++0x03
|
|
line.long 0x00 "APB_SLV_ERR_INT_STA_EN,Apb bus error interrupt status enable"
|
|
bitfld.long 0x00 5. " PUSER_UNCERR ,Status enable for puser parity error." "0,1"
|
|
bitfld.long 0x00 4. " PWDATA_FATAL ,Status enable for pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 3. " PWDATA_UNCERR ,Status enable for pwdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 2. " PWDATA_CORERR ,Status enable for pwdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PCTL_UNCERR ,Status enable for apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 0. " PADDR_UNCERR ,Status enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0428++0x03
|
|
line.long 0x00 "APB_SLV_ERR_INT_SIG_EN,Apb bus error Interrupt signal enable"
|
|
bitfld.long 0x00 5. " PUSER_UNCERR ,Interrupt signal enable for puser parity error." "0,1"
|
|
bitfld.long 0x00 4. " PWDATA_FATAL ,Interrupt signal enable for pwdata fatal error" "0,1"
|
|
bitfld.long 0x00 3. " PWDATA_UNCERR ,Interrupt signal enable for pwdata uncorrectable error." "0,1"
|
|
bitfld.long 0x00 2. " PWDATA_CORERR ,Interrupt Signal enable for pwdata correctable error." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PCTL_UNCERR ,Interrupt signal enable for apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 0. " PADDR_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B042C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_0,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0430++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_0,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0434++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_0,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0438++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_1,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B043C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_1,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0440++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_1,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0444++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_2,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0448++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_2,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B044C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_2,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0450++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_3,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0454++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_3,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0458++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_3,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B045C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_4,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0460++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_4,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0464++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_4,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0468++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_5,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B046C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_5,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0470++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_5,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0474++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_6,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0478++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_6,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B047C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_6,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0480++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_7,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0484++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_7,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0488++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_7,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B048C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_8,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0490++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_8,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0494++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_8,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0498++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_9,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B049C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_9,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B04A0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_9,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B04A4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_10,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B04A8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_10,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B04AC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_10,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B04B0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_11,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B04B4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_11,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B04B8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_11,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B04BC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_12,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B04C0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_12,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B04C4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_12,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B04C8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_13,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B04CC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_13,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B04D0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_13,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B04D4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_14,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B04D8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_14,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B04DC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_14,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B04E0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_15,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B04E4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_15,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B04E8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_15,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B04EC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_16,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B04F0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_16,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B04F4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_16,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B04F8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_17,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B04FC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_17,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0500++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_17,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0504++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_18,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0508++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_18,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B050C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_18,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0510++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_19,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0514++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_19,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0518++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_19,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B051C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_20,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0520++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_20,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0524++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_20,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0528++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_21,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B052C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_21,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0530++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_21,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0534++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_22,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0538++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_22,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B053C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_22,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0540++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_23,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0544++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_23,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0548++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_23,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B054C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_24,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0550++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_24,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0554++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_24,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0558++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_25,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B055C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_25,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0560++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_25,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0564++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_26,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0568++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_26,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B056C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_26,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0570++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_27,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0574++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_27,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0578++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_27,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B057C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_28,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0580++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_28,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0584++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_28,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0588++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_29,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B058C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_29,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B0590++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_29,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B0594++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_30,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B0598++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_30,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B059C++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_30,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B05A0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_31,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B05A4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_31,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B05A8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_31,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B05AC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_32,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B05B0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_32,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B05B4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_32,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B05B8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_33,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B05BC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_33,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B05C0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_33,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B05C4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_34,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B05C8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_34,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B05CC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_34,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B05D0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_35,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B05D4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_35,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B05D8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_35,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B05DC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_36,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B05E0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_36,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B05E4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_36,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B05E8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_37,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B05EC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_37,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B05F0++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_37,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B05F4++0x03
|
|
line.long 0x00 "APB_MAS_ERR_IN_STA_38,APB bus master port error interrupt status"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Presp parity error" "0,1"
|
|
group ad:0xF07B05F8++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_STA_EN_38,Apb bus master port error interrupt status enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Status enable for Presp parity error" "0,1"
|
|
group ad:0xF07B05FC++0x03
|
|
line.long 0x00 "APB_MAS_ERR_INT_SIG_EN_38,Apb bus master port error interrupt signal enable"
|
|
bitfld.long 0x00 0. " PRESP_UNCERR ,Interrupt signal enable for Paddr parity error" "0,1"
|
|
group ad:0xF07B07E8++0x03
|
|
line.long 0x00 "MAS_ATR_ERR_INJ,Master Attribute output error injection"
|
|
hexmask.long.byte 0x00 1.--7. 1. " INJ_BIT ,Error injection select 0~15: mas_pri_ov_en. 16~31: mac_pri 32~47: mac_sec_ov_en 48~63: mac_sec 64~127: mac_DId"
|
|
bitfld.long 0x00 0. " INJ_EN ,Error injection enable" "0,1"
|
|
group ad:0xF07B07EC++0x03
|
|
line.long 0x00 "APB_BUS_ERR_INJ,APB bus interface error injection"
|
|
bitfld.long 0x00 11.--12. " INJ_MODE ,2'b00 - DIsable 2'b01 - parity injection 2'b10 - pwdatacode_s injection 2'b11 - prdatacode_s injection" "0,1,2,3"
|
|
hexmask.long.word 0x00 1.--10. 1. " INJ_BIT ,inj_mode 01 0~3: paddrpty_s 4: pctlpty_s 5: prespty_s 6~7: paddrpty_m 8~8+(MPC_NUM+PPC_NUM)-1: pctlpty_m 8+(MPC_NUM+PPC_NUM)~15+2*(MPC_NUM+PPC_NUM)-1: prespty_m inj_mode 10 0~6: pwdatacode_s inj_mode 11 0~6: prdatacode_s.."
|
|
bitfld.long 0x00 0. " INJ_EN ,apb bus error injection" "0,1"
|
|
group ad:0xF07B07F0++0x03
|
|
line.long 0x00 "DATA_31_0_INJ,Error injection on data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on apb write data"
|
|
group ad:0xF07B07F4++0x03
|
|
line.long 0x00 "ECC_INJ,Error injection on ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for apb write data"
|
|
group ad:0xF07B07F8++0x03
|
|
line.long 0x00 "IRQ_ERR_INJ,IRQ Error injection"
|
|
bitfld.long 0x00 2. " FUNC ,Function irq error" "0,1"
|
|
bitfld.long 0x00 1. " UNCERR ,Uncorrectable error irq error injection." "0,1"
|
|
bitfld.long 0x00 0. " CORERR ,Correctable error irq error injection." "0,1"
|
|
group ad:0xF07B07FC++0x03
|
|
line.long 0x00 "LSP_CMP_INJ,Lockstep compare error injection register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INJ_BIT ,Bit location for bit flip to generate lockstep compare error injection."
|
|
bitfld.long 0x00 4.--7. " INJ_SEL ,Error injection objection selection. 0x0: apb slave signals 0x1: apb master signals 0x2: master signals 0x3: interrupt signals 0x4: internal signal Other value: no select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " INJ_EN ,Lockstep compare error injection enable" "0,1"
|
|
tree.end
|
|
config 16. 8.
|
|
tree "POR"
|
|
tree "POR_SF"
|
|
width 28.
|
|
group ad:0xF0650000++0x03
|
|
line.long 0x00 "POR_FUSA_INT_EN,POR FUSA INTERRUPT ENABLE"
|
|
bitfld.long 0x00 6. " POR_SCR_DVS_UNC_IRQ_EN ,Fusa scr DIverse redundancy uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 5. " POR_WDATA_UNC_IRQ_EN ,Fusa pwdata uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 4. " POR_WDATA_FATAL_EN ,Fusa pwdata fatal enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 3. " POR_CTL1_UNC_IRQ_EN ,Fusa pctl1 uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "POR_CTL0_UNC_IRQ_EN ,Fusa pctl0 uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " POR_ADDR_UNC_IRQ_EN ,Fusa paddr uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " POR_WDATA_COR_IRQ_EN ,Fusa pwdata correctable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0650004++0x03
|
|
line.long 0x00 "POR_FUSA_IRQ_ERR_INJ,POR FUSA interrupt error injection control"
|
|
bitfld.long 0x00 1. " POR_IRQ_ERR_INJ_BIT ,Fusa interrupt error injection bit 0:uncor_irq 1: cor_irq" "0,1"
|
|
bitfld.long 0x00 0. " POR_IRQ_ERR_INJ_EN ,Fusa interrupt error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0650008++0x03
|
|
line.long 0x00 "POR_FUSA_E2E_ERR_INJ,POR_FUSA_E2E_ERR_INJ"
|
|
hexmask.long.byte 0x00 1.--7. 1. " WECC_INJ ,APB E2E wecc error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB E2E wdata error injection enable" "0,1"
|
|
group ad:0xF0650010++0x03
|
|
line.long 0x00 "POR_FUSA_E2E_ERR_INJ_1,POR_FUSA_E2E_ERR_INJ_1"
|
|
hexmask.long 0x00 0.--31. 1. " WDATA_INJ ,APB E2E wdata injection"
|
|
group ad:0xF0650014++0x03
|
|
line.long 0x00 "POR_FUSA_ERR_STA,POR_FUSA_ERR_STA"
|
|
bitfld.long 0x00 6. " POR_SCR_DVS_UNC_ERR_STATUS ,Fusa scr DIverse redundancy uncorrectable error status, write one to clear" "0,1"
|
|
bitfld.long 0x00 5. " POR_WDATA_UNC_ERR_STATUS ,fusa pwdata uncorrectable error status, write one to clear" "0,1"
|
|
bitfld.long 0x00 4. " POR_WDATA_FATAL_STATUS ,fusa pwdata fatal status, write one to clear" "0,1"
|
|
bitfld.long 0x00 3. " POR_CTL1_UNC_ERR_STATUS ,fusa pctl1 uncorrectable error status, write one to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "POR_CTL0_UNC_ERR_STATUS ,fusa pctl0 uncorrectable error status, write one to clear" "0,1"
|
|
bitfld.long 0x00 1. " POR_ADDR_UNC_ERR_STATUS ,fusa paddr uncorrectable error status, write one to clear" "0,1"
|
|
bitfld.long 0x00 0. " POR_WDATA_COR_ERR_STATUS ,fusa pwdata correctable error status, write one to clear" "0,1"
|
|
group ad:0xF0650018++0x03
|
|
line.long 0x00 "POR_CTRL,POR_CTRL"
|
|
bitfld.long 0x00 7. " por_sync_en ,Por control sync enable, active high" "0,1"
|
|
bitfld.long 0x00 4.--6. " por_test ,Por analog DC point testing [2] test enable: 1: enable, 0: DIsable. [1:0] 00:AVDD33 01: biasp 10: DVDD 11: vref 0.3V" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. " por_pvin33_bor_set ,'power supply BOR threshold control bits. 00: -30% 01: -25% 10: -17% 11: -12% '" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " por_pvin08_bor_set ,'power supply BOR threshold control bits. 00: -30% 01: -25% 10: -17% 11: -12% '" "0,1,2,3"
|
|
group ad:0xF0650070++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
|
|
bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
|
|
group ad:0xF0650074++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF0650078++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF065007C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
tree.end
|
|
tree "POR_AP"
|
|
width 28.
|
|
group ad:0xF3050000++0x03
|
|
line.long 0x00 "POR_FUSA_INT_EN,POR FUSA INTERRUPT ENABLE"
|
|
bitfld.long 0x00 6. " POR_SCR_DVS_UNC_IRQ_EN ,Fusa scr DIverse redundancy uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 5. " POR_WDATA_UNC_IRQ_EN ,Fusa pwdata uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 4. " POR_WDATA_FATAL_EN ,Fusa pwdata fatal enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 3. " POR_CTL1_UNC_IRQ_EN ,Fusa pctl1 uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "POR_CTL0_UNC_IRQ_EN ,Fusa pctl0 uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " POR_ADDR_UNC_IRQ_EN ,Fusa paddr uncorrectable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " POR_WDATA_COR_IRQ_EN ,Fusa pwdata correctable interrupt enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF3050004++0x03
|
|
line.long 0x00 "POR_FUSA_IRQ_ERR_INJ,POR FUSA interrupt error injection control"
|
|
bitfld.long 0x00 1. " POR_IRQ_ERR_INJ_BIT ,Fusa interrupt error injection bit 0:uncor_irq 1: cor_irq" "0,1"
|
|
bitfld.long 0x00 0. " POR_IRQ_ERR_INJ_EN ,Fusa interrupt error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF3050008++0x03
|
|
line.long 0x00 "POR_FUSA_E2E_ERR_INJ,POR_FUSA_E2E_ERR_INJ"
|
|
hexmask.long.byte 0x00 1.--7. 1. " WECC_INJ ,APB E2E wecc error injection"
|
|
bitfld.long 0x00 0. " ERR_INJ_EN ,APB E2E wdata error injection enable" "0,1"
|
|
group ad:0xF3050010++0x03
|
|
line.long 0x00 "POR_FUSA_E2E_ERR_INJ_1,POR_FUSA_E2E_ERR_INJ_1"
|
|
hexmask.long 0x00 0.--31. 1. " WDATA_INJ ,APB E2E wdata injection"
|
|
group ad:0xF3050014++0x03
|
|
line.long 0x00 "POR_FUSA_ERR_STA,POR_FUSA_ERR_STA"
|
|
bitfld.long 0x00 6. " POR_SCR_DVS_UNC_ERR_STATUS ,Fusa scr DIverse redundancy uncorrectable error status, write one to clear" "0,1"
|
|
bitfld.long 0x00 5. " POR_WDATA_UNC_ERR_STATUS ,fusa pwdata uncorrectable error status, write one to clear" "0,1"
|
|
bitfld.long 0x00 4. " POR_WDATA_FATAL_STATUS ,fusa pwdata fatal status, write one to clear" "0,1"
|
|
bitfld.long 0x00 3. " POR_CTL1_UNC_ERR_STATUS ,fusa pctl1 uncorrectable error status, write one to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "POR_CTL0_UNC_ERR_STATUS ,fusa pctl0 uncorrectable error status, write one to clear" "0,1"
|
|
bitfld.long 0x00 1. " POR_ADDR_UNC_ERR_STATUS ,fusa paddr uncorrectable error status, write one to clear" "0,1"
|
|
bitfld.long 0x00 0. " POR_WDATA_COR_ERR_STATUS ,fusa pwdata correctable error status, write one to clear" "0,1"
|
|
group ad:0xF3050018++0x03
|
|
line.long 0x00 "POR_CTRL,POR_CTRL"
|
|
bitfld.long 0x00 7. " por_sync_en ,Por control sync enable, active high" "0,1"
|
|
bitfld.long 0x00 4.--6. " por_test ,Por analog DC point testing [2] test enable: 1: enable, 0: DIsable. [1:0] 00:AVDD33 01: biasp 10: DVDD 11: vref 0.3V" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. " por_pvin33_bor_set ,'power supply BOR threshold control bits. 00: -30% 01: -25% 10: -17% 11: -12% '" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " por_pvin08_bor_set ,'power supply BOR threshold control bits. 00: -30% 01: -25% 10: -17% 11: -12% '" "0,1,2,3"
|
|
group ad:0xF3050070++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
|
|
bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
|
|
group ad:0xF3050074++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF3050078++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF305007C++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "PMU"
|
|
width 26.
|
|
group ad:0xF0060000++0x03
|
|
line.long 0x00 "BC_VLD_WINDOW,ON or OFF valid window setting for ButtonControl pin"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BC_OFF_VLD_MAX ,maximum window for valid 'OFF', for ButtonControl pin only valid in level mode when BC_OFF_VLD_MAX_DISABLE is 0. It's used together with the fields in BC_CNT_UNIT."
|
|
hexmask.long.byte 0x00 16.--23. 1. " BC_OFF_VLD_MIN ,minimal window for valid 'OFF', for ButtonControl pin only valid in level mode. It's used together with the fields in BC_CNT_UNIT."
|
|
hexmask.long.byte 0x00 8.--15. 1. " BC_ON_VLD_MAX ,maximum window for valid 'ON', for ButtonControl pin only valid in level mode when BC_ON_VLD_MAX_DISABLE is 0. It's used together with the fields in BC_CNT_UNIT."
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hexmask.long.byte 0x00 0.--7. 1. " BC_ON_VLD_MIN ,minimal window for valid 'ON', for ButtonControl pin only valid in level mode. It's used together with the fields in BC_CNT_UNIT."
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group ad:0xF0060004++0x03
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line.long 0x00 "BC_CTRL_SET,control settings for ButtonControl pin"
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hexmask.long.byte 0x00 24.--31. 1. " PWR_DWN_HW_REQ_ENABLE ,enable the hardware power down request. Each bit enable/DIsable one hardware power down request. 0 - DIsable 1 - enable"
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bitfld.long 0x00 23. " PWR_DWN_REQ_SOFT ,write '1' to trigger power down request. auto clear." "0,1"
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bitfld.long 0x00 21.--22. " BC_FILTER_EDGE ,Select which edge needs to apply the filter for ButtonControl pin. 00 - Rising; 01 - Falling; 1x - Both" "0,1,2,3"
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bitfld.long 0x00 17.--20. " BC_FILTER_CNT ,Filter counter for ButtonControl pin. Filter counter = BC_FILTER_CNT+2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 14.--16. "BC_SAMPLE_INTERVAL ,Sample interval for ButtonControl pin. Sample Interval = 2^ BC_SAMPLE_INTERVAL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 13. " BC_FILTER_BYPASS ,bypass filter for ButtonControl 0 - filter is enabled 1- bypass filter" "0,1"
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bitfld.long 0x00 12. " BC_DISABLE_LOCK ,Lock bit for BC_DISABLE. When it's set, BC_DISABLE can't be updated by software." "0,1"
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bitfld.long 0x00 11. " BC_DISABLE ,DIsable the ButtonControl pin. 0 - enable 1 - DIsable (default) It's written-able only when BC_DISABLE_LOCK is 0." "0,1"
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textline " "
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bitfld.long 0x00 10. "BC_FSM_ENABLE ,Enable the state monitor for ButtonControl. When enabled, only responds the valid power ON request in BC_OFF state, and only respond the valid power OFF request in BC_ON state. For example, if two consecutive power ON .." "0,1"
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bitfld.long 0x00 9. " BC_OFF_EDGE ,Level or edge setting of ButtonControl pin for OFF. 0 - Level 1 - Edge" "0,1"
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bitfld.long 0x00 8. " BC_ON_EDGE ,Level or edge setting of ButtonControl pin for ON. 0 - Level 1 - Edge" "0,1"
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bitfld.long 0x00 7. " BC_OFF_POL ,Polarity of ButtonControl pin for OFF. 0 - high active or rising edge 1 - low active or falling edge" "0,1"
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textline " "
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bitfld.long 0x00 6. "BC_ON_POL ,Polarity of ButtonControl pin for ON. 0 - high active or rising edge 1 - low active or falling edge" "0,1"
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bitfld.long 0x00 5. " BC_OFF_VLD_MAX_DISABLE ,1 to DIsable BC_OFF_VLD_MAX" "0,1"
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bitfld.long 0x00 4. " BC_ON_VLD_MAX_DISABLE ,1 to DIsable BC_ON_VLD_MAX" "0,1"
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bitfld.long 0x00 0.--3. " BC_CNT_UNIT ,Count Unit for ButtonContrl. It's used together with the fields in BC_VLD_WINDOW. The real window setting is equal to BC_ON/OFF_VLD_MIN/MAX * (2^BC_CNT_UNIT). Note: It must be smaller than 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0060008++0x03
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line.long 0x00 "WAKEUP_CTRL,control settins for Wakeup pin 0/1"
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bitfld.long 0x00 31. " WKUP01_AND_ENABLE ,When enabled, generate the wakeup event only when wakeup 0 and wakeup 1 are both active. 1 - enable" "0,1"
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bitfld.long 0x00 30. " WKUP1_DISABLE ,DIsable the wakeup 1 pin 1 - DIsable" "0,1"
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bitfld.long 0x00 29. " WKUP0_DISABLE ,DIsable the wakeup 0 pin 1 - DIsable" "0,1"
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bitfld.long 0x00 28. " WKUP1_POL ,polarity selection for wakeup 1 0 - high active (for level mode), rising edge (or edge mode) 1 - low active (for level mode), falling edge (or edge mode)" "0,1"
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textline " "
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bitfld.long 0x00 27. "WKUP0_POL ,polarity selection for wakeup 0 0 - high active (for level mode), rising edge (or edge mode) 1 - low active (for level mode), falling edge (or edge mode)" "0,1"
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bitfld.long 0x00 26. " WKUP1_EDGE ,level or edge selection for wakeup 1 0 - level 1 - edge" "0,1"
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bitfld.long 0x00 25. " WKUP0_EDGE ,level or edge selection for wakeup 0 0 - level 1 - edge" "0,1"
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bitfld.long 0x00 22. " WAKEUP_IN_RTC_LATCH ,PMU has RTC and OFF state. During RTC state, PMU doesn't respond to wake up event. It only responds to wake up even in OFF state. PMU has this enable bit to latch the wake up event which is happening in RTC state or .." "0,1"
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textline " "
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bitfld.long 0x00 21. "EXT_WAKEUP_EN ,enable external wake up which is generated by ButtonControl pin 1 - enable" "0,1"
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bitfld.long 0x00 20. " INT_WAKEUP_EN ,enable internal wake up event which is generated by RTC perioDIc interrupt 1 - enable" "0,1"
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bitfld.long 0x00 18.--19. " WKUP1_FILTER_EDGE ,select which edge needs to apply the filter for wakeup 1 pins 00 - rising; 01 - falling; 1x - both edge" "0,1,2,3"
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bitfld.long 0x00 14.--17. " WKUP1_FILTER_CNT ,filter counter for wakeup 1 pins filter counter = WKUP_FILTER_CNT +2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 11.--13. "WKUP1_SAMPLE_INTERVAL ,Sample interval setting for wakeup 1 pins sample interval = 2^WAKEUP_SAMPLE_INTERVAL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 10. " WKUP1_FILTER_BYPASS ,filter bypass for wakeup 1 pin 1 - bypass filter" "0,1"
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bitfld.long 0x00 8.--9. " WKUP0_FILTER_EDGE ,select which edge needs to apply the filter for wakeup 0 pins 00 - rising; 01 - falling; 1x - both edge" "0,1,2,3"
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bitfld.long 0x00 4.--7. " WKUP0_FILTER_CNT ,filter counter for wakeup 0 pins filter counter = WKUP_FILTER_CNT +2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 1.--3. "WKUP0_SAMPLE_INTERVAL ,Sample interval setting for wakeup 0 pins sample interval = 2^WAKEUP_SAMPLE_INTERVAL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " WKUP0_FILTER_BYPASS ,filter bypass for wakeup 0 pin 1 - bypass filter" "0,1"
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group ad:0xF006000C++0x03
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line.long 0x00 "PGM_CTRL,controls for power good module"
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bitfld.long 0x00 28.--31. " pwr_on_wdt_en ,enable pwr_on_wdt_cnt for pwr_on[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. " por_tw ,power good time window. It's used to detect whether the power good sequence is illegal. It's expected both power good status (generated by two inDIvidual POR detectors) will be asserted within this time window." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 22.--23. " por_tw_adj ,power good time window adjustment" "0,1,2,3"
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bitfld.long 0x00 20.--21. " HW_REBOOT_REQ_EN ,hardware reboot enable [1] - 1 to reboot the whole system when lockstep error occurs [0] - 1 to reboot the whole system when PWR_UP/SLEEP/HIBERNATE to RUN times out" "0,1,2,3"
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textline " "
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bitfld.long 0x00 16.--19. "wdt_DIv ,interval to increase pwr_on*_wdt_cnt. i.e., every 2^wdt_DIv." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " pwr_on3_wdt_cnt ,timeout settings for pwr_on3. Timeout = pwr_on3_wdt_cnt * (2^wdt_DIv) default 1s" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " pwr_on2_wdt_cnt ,timeout settings for pwr_on2. Timeout = pwr_on2_wdt_cnt * (2^wdt_DIv) default 1s" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " pwr_on1_wdt_cnt ,timeout settings for pwr_on1. Timeout = pwr_on1_wdt_cnt * (2^wdt_DIv) default 1s" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 0.--3. "pwr_on0_wdt_cnt ,timeout settings for pwr_on0. Timeout = pwr_on0_wdt_cnt * (2^wdt_DIv) default 1s" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0060010++0x03
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line.long 0x00 "PWR_CTRL_SET0,setting0 for pwr_ctrl0~3"
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hexmask.long.byte 0x00 24.--31. 1. " RTC_PWR_CTRL_SET0 ,false ON/OFF and Auto/Manual setting for pwr_ctrl3:0] in RTC state. [7] - on/off for pwr_ctrl0 [6] - auto/manual for pwr_ctrl0 [5] - on/off for pwr_ctrl1 [4] - auto/manual for pwr_ctrl1 [3] - on/off for pwr_ctrl2 [2.."
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hexmask.long.byte 0x00 16.--23. 1. " RUN_PWR_CTRL_SET0 ,ON/OFF and Auto/Manual setting for pwr_ctrl3:0] in RUN state. [7] - on/off for pwr_ctrl0 [6] - auto/manual for pwr_ctrl0 [5] - on/off for pwr_ctrl1 [4] - auto/manual for pwr_ctrl1 [3] - on/off for pwr_ctrl2 [2.."
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hexmask.long.byte 0x00 8.--15. 1. " SLEEP_PWR_CTRL_SET0 ,ON/OFF and Auto/Manual setting for pwr_ctrl3:0] in SLEEP state. [7] - on/off for pwr_ctrl0 [6] - auto/manual for pwr_ctrl0 [5] - on/off for pwr_ctrl1 [4] - auto/manual for pwr_ctrl1 [3] - on/off for pwr_ctrl2.."
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hexmask.long.byte 0x00 0.--7. 1. " HIBERNATE_PWR_CTRL_SET0 ,ON/OFF and Auto/Manual setting for pwr_ctrl3:0] in HIBERNATE state. [7] - on/off for pwr_ctrl0 [6] - auto/manual for pwr_ctrl0 [5] - on/off for pwr_ctrl1 [4] - auto/manual for pwr_ctrl1 [3] - on/off for pwr_ctrl2.."
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group ad:0xF0060014++0x03
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line.long 0x00 "PWR_CTRL_SET1,setting1 for pwr_ctrl0~3"
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bitfld.long 0x00 31. " PWR_UP_RUN_MIN_DELAY_ENABLE ,enable pwr_up_run_min_delay. When enabled, the state transition from PWR_UP state to RUN state must be > pwr_up_run_min_delay. SW should set this bit ONLY when i. all the status of pwr_ctrl0-3 pins don't change when state.." "0,1"
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bitfld.long 0x00 30. " SLEEP_RUN_MIN_DELAY_ENABLE ,enable sleep_run_min_delay. When enabled, the state transition from SLEEP state to RUN state must be > sleep_run_min_delay. SW should set this bit ONLY when i. all the status of pwr_ctrl0-3 pins don't change when .." "0,1"
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bitfld.long 0x00 29. " HIBERNATE_RUN_MIN_DELAY_ENABLE ,enable hibernate_run_min_delay. When enabled, the state transition from HIBERNATE state to RUN state must be > hibernate_run_min_delay. SW should set this bit ONLY when i. all the status of pwr_ctrl0-3 pins don't.." "0,1"
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bitfld.long 0x00 20.--23. " PWR_CTRL_POL ,polarity of pwr_ctrl0-3 0 - high active (high means ON) 1 - low active (low means ON) [3] - pwr_ctrl3 [2] - pwr_ctrl2 [1] - pwr_ctrl1 [0] - pwr_ctrl0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 12.--15. "SW_PWR_CTRL_EN ,pwr_ctrl0-3 override enable 1 - override enable 0 - override DIsable [3] - pwr_ctrl3 [2] - pwr_ctrl2 [1] - pwr_ctrl1 [0] - pwr_ctrl0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SW_PWR_CTRL ,pwr_ctrl0-3 override value [3] - pwr_ctrl3 [2] - pwr_ctrl2 [1] - pwr_ctrl1 [0] - pwr_ctrl0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0060018++0x03
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line.long 0x00 "PWR_UP_PWR_CTRL_DELAY,delay setting in PWR_UP state for pwr_ctrl0-3"
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bitfld.long 0x00 30.--31. " PWR_UP_PWR_CTRL_MAX ,inDIcate which pwr_ctrl delay is the max one in PWR_UP state 00 - pwr_ctrl0 is the max one 01 - pwr_ctrl1 is the max one 10 - pwr_ctrl2 is the max one 11 - pwr_ctrl3 is the max one" "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " PWR_UP_PWR_CTRL_DELAY ,delay setting in PWR_UP state for pwr_ctrl0-3 pins: [23:22] - pwr_up_pwr_ctrl3_delay_adj [21:18] - pwr_up_pwr_ctrl3_delay [17:16] - pwr_up_pwr_ctrl2_delay_adj [15:12] - pwr_up_pwr_ctrl2_delay [11:10] - .."
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group ad:0xF006001C++0x03
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line.long 0x00 "RUN_PWR_CTRL_DELAY,delay setting in RUN state for pwr_ctrl0-3"
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bitfld.long 0x00 30.--31. " RUN_PWR_CTRL_MAX ,inDIcate which pwr_ctrl delay is the max one in RUN state 00 - pwr_ctrl0 is the max one 01 - pwr_ctrl1 is the max one 10 - pwr_ctrl2 is the max one 11 - pwr_ctrl3 is the max one" "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " RUN_PWR_CTRL_DELAY ,delay setting in RUN state for pwr_ctrl0-3 pins: [23:22] - run_pwr_ctrl3_delay_adj [21:18] - run_pwr_ctrl3_delay [17:16] - run_pwr_ctrl2_delay_adj [15:12] - run_pwr_ctrl2_delay [11:10] - run_pwr_ctrl1_delay_adj [9:.."
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group ad:0xF0060020++0x03
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line.long 0x00 "SLEEP_PWR_CTRL_DELAY,delay setting in SLEEP state for pwr_ctrl0-3"
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bitfld.long 0x00 30.--31. " SLEEP_PWR_CTRL_MAX ,inDIcate which pwr_ctrl delay is the max one in SLEEP state 00 - pwr_ctrl0 is the max one 01 - pwr_ctrl1 is the max one 10 - pwr_ctrl2 is the max one 11 - pwr_ctrl3 is the max one" "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " SLEEP_PWR_CTRL_DELAY ,delay setting in SLEEP state for pwr_ctrl0-3 pins: [23:22] - sleep_pwr_ctrl3_delay_adj [21:18] - sleep_pwr_ctrl3_delay [17:16] - sleep_pwr_ctrl2_delay_adj [15:12] - sleep_pwr_ctrl2_delay [11:10] - .."
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group ad:0xF0060024++0x03
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line.long 0x00 "HIBERNATE_PWR_CTRL_DELAY,delay setting in HIBERNATE state for pwr_ctrl0-3"
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bitfld.long 0x00 30.--31. " HIBERNATE_PWR_CTRL_MAX ,inDIcate which pwr_ctrl delay is the max one in HIBERNATE state 00 - pwr_ctrl0 is the max one 01 - pwr_ctrl1 is the max one 10 - pwr_ctrl2 is the max one 11 - pwr_ctrl3 is the max one" "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " HIBERNATE_PWR_CTRL_DELAY ,delay setting in HIBERNATE state for pwr_ctrl0-3 pins: [23:22] - hibernate_pwr_ctrl3_delay_adj [21:18] - hibernate_pwr_ctrl3_delay [17:16] - hibernate_pwr_ctrl2_delay_adj [15:12] - hibernate_pwr_ctrl2_delay [11:10.."
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group ad:0xF0060028++0x03
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line.long 0x00 "RTC_PWR_CTRL_DELAY,delay setting in RTC state for pwr_ctrl0-3"
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bitfld.long 0x00 30.--31. " RTC_PWR_CTRL_MAX ,inDIcate which pwr_ctrl delay is the max one in RTC state 00 - pwr_ctrl0 is the max one 01 - pwr_ctrl1 is the max one 10 - pwr_ctrl2 is the max one 11 - pwr_ctrl3 is the max one" "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " RTC_PWR_CTRL_DELAY ,delay setting in RTC state for pwr_ctrl0-3 pins: [23:22] - rtc_pwr_ctrl3_delay_adj [21:18] - rtc_pwr_ctrl3_delay [17:16] - rtc_pwr_ctrl2_delay_adj [15:12] - rtc_pwr_ctrl2_delay [11:10] - rtc_pwr_ctrl1_delay_adj [9:.."
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group ad:0xF0060030++0x03
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line.long 0x00 "RUN_PWR_ON_SET,setting for pwr_on0~3 in RUN state"
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hexmask.long.tbyte 0x00 0.--17. 1. " RUN_PWR_ON_SET ,pwr_on control settings in RUN state [17] - SF power ON(1) or OFF(0) in RUN state [16] - AP power ON(1) or OFF(0) in RUN state [15:14] - pwr_on3 control target in RUN state (00 - SF; 01 - AP; 1x - not SF/AP) [13.."
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group ad:0xF0060034++0x03
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line.long 0x00 "SLEEP_PWR_ON_SET,setting for pwr_on0~3 in SLEEP state"
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hexmask.long.tbyte 0x00 0.--17. 1. " SLEEP_PWR_ON_SET ,pwr_on control settings in SLEEP state [17] - SF power ON(1) or OFF(0) in SLEEP state [16] - AP power ON(1) or OFF(0) in SLEEP state [15:14] - pwr_on3 control target in SLEEP state (00 - SF; 01 - AP; 1x - not SF/.."
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group ad:0xF0060038++0x03
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line.long 0x00 "HIBERNATE_PWR_ON_SET,setting for pwr_on0~3 in HIBERNATE state"
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hexmask.long.tbyte 0x00 0.--17. 1. " HIBERNATE_PWR_ON_SET ,pwr_on control settings in HIBERNATE state [17] - SF power ON(1) or OFF(0) in HIBERNATE state [16] - AP power ON(1) or OFF(0) in HIBERNATE state [15:14] - pwr_on3 control target in HIBERNATE state (00 - SF; 01 - .."
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group ad:0xF006003C++0x03
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line.long 0x00 "RTC_PWR_ON_SET,setting for pwr_on0~3 in RTC state"
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bitfld.long 0x00 31. " RTC_TO_OFF_SF_HV_PG_DISABLE ,DIsable SF HV power not good check when switching from RTC state to OFF state. 0 - switching from RTC state to OFF state only when the power down counter is done and SF/AP power are not good. 1 - switching from RTC state .." "0,1"
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bitfld.long 0x00 30. " RTC_TO_OFF_SF_LV_PG_DISABLE ,DIsable SF LV power not good check when switching from RTC state to OFF state. 0 - switching from RTC state to OFF state only when the power down counter is done and SF/AP power are not good. 1 - switching from RTC.." "0,1"
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bitfld.long 0x00 29. " RTC_TO_OFF_AP_HV_PG_DISABLE ,DIsable AP HV power not good check when switching from RTC state to OFF state. 0 - switching from RTC state to OFF state only when the power down counter is done and SF/AP power are not good. 1 - switching from .." "0,1"
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bitfld.long 0x00 28. " RTC_TO_OFF_AP_LV_PG_DISABLE ,DIsable AP LV power not good check when switching from RTC state to OFF state. 0 - switching from RTC state to OFF state only when the power down counter is done and SF/AP power are not good. 1 - switching from RTC .." "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--17. 1. "RTC_PWR_ON_SET ,pwr_on control settings in RTC state [17] - SF power ON(1) or OFF(0) in RTC state (reserved!) [16] - AP power ON(1) or OFF(0) in RTC state (reserved!) [15:14] - pwr_on3 control target in RTC state (00 - SF; 01 - .."
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group ad:0xF0060040++0x03
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line.long 0x00 "PWR_UP_PWR_ON_DELAY,Delay setting of pwr_on0~3 in PWR_UP state"
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bitfld.long 0x00 30.--31. " PWR_UP_PWR_ON_AP_MAX ,inDIcate which pwr_on delay(related to AP power) is the max one in PWR_UP state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one" "0,1,2,3"
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bitfld.long 0x00 28.--29. " PWR_UP_PWR_ON_SF_MAX ,inDIcate which pwr_on delay (related to SF power) is the max one in PWR_UP state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one.." "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " PWR_UP_PWR_ON_DELAY ,delay setting in PWR_UP state for pwr_on0-3 pins: [23:22] - hibernate_pwr_on3_delay_adj [21:18] - hibernate_pwr_on3_delay [17:16] - hibernate_pwr_on2_delay_adj [15:12] - hibernate_pwr_on2_delay [11:10] - .."
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group ad:0xF0060044++0x03
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line.long 0x00 "RUN_PWR_ON_DELAY,Delay setting of pwr_on0~3 in RUN state"
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bitfld.long 0x00 30.--31. " RUN_PWR_ON_AP_MAX ,inDIcate which pwr_on delay(related to AP power) is the max one in RUN state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one" "0,1,2,3"
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bitfld.long 0x00 28.--29. " RUN_PWR_ON_SF_MAX ,inDIcate which pwr_on delay (related to SF power) is the max one in RUN state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one.." "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " RUN_PWR_ON_DELAY ,delay setting in RUN state for pwr_on0-3 pins: [23:22] - hibernate_pwr_on3_delay_adj [21:18] - hibernate_pwr_on3_delay [17:16] - hibernate_pwr_on2_delay_adj [15:12] - hibernate_pwr_on2_delay [11:10] - .."
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group ad:0xF0060048++0x03
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line.long 0x00 "SLEEP_PWR_ON_DELAY,Delay setting of pwr_on0~3 in SLEEP state"
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bitfld.long 0x00 30.--31. " SLEEP_PWR_ON_AP_MAX ,inDIcate which pwr_on delay(related to AP power) is the max one in SLEEP state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one" "0,1,2,3"
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bitfld.long 0x00 28.--29. " SLEEP_PWR_ON_SF_MAX ,inDIcate which pwr_on delay (related to SF power) is the max one in SLEEP state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one.." "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " SLEEP_PWR_ON_DELAY ,delay setting in SLEEP state for pwr_on0-3 pins: [23:22] - hibernate_pwr_on3_delay_adj [21:18] - hibernate_pwr_on3_delay [17:16] - hibernate_pwr_on2_delay_adj [15:12] - hibernate_pwr_on2_delay [11:10] - .."
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group ad:0xF006004C++0x03
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line.long 0x00 "HIBERNATE_PWR_ON_DELAY,Delay setting of pwr_on0~3 in HIBERNATE state"
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bitfld.long 0x00 30.--31. " HIBERNATE_PWR_ON_AP_MAX ,inDIcate which pwr_on delay(related to AP power) is the max one in HIBERNATE state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one" "0,1,2,3"
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bitfld.long 0x00 28.--29. " HIBERNATE_PWR_ON_SF_MAX ,inDIcate which pwr_on delay (related to SF power) is the max one in HIBERNATE state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one.." "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " HIBERNATE_PWR_ON_DELAY ,delay setting in HIBERNATE state for pwr_on0-3 pins: [23:22] - hibernate_pwr_on3_delay_adj [21:18] - hibernate_pwr_on3_delay [17:16] - hibernate_pwr_on2_delay_adj [15:12] - hibernate_pwr_on2_delay [11:10] - .."
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group ad:0xF0060050++0x03
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line.long 0x00 "RTC_PWR_ON_DELAY,Delay setting of pwr_on0~3 in RTC state"
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bitfld.long 0x00 30.--31. " RTC_PWR_ON_AP_MAX ,inDIcate which pwr_on delay(related to AP power) is the max one in RTC state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one" "0,1,2,3"
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bitfld.long 0x00 28.--29. " RTC_PWR_ON_SF_MAX ,inDIcate which pwr_on delay (related to SF power) is the max one in RTC state 00 - pwr_on0 is the max one 01 - pwr_on1 is the max one 10 - pwr_on2 is the max one 11 - pwr_on3 is the max one.." "0,1,2,3"
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hexmask.long.tbyte 0x00 0.--23. 1. " RTC_PWR_ON_DELAY ,delay setting in RTC state for pwr_on0-3 pins: [23:22] - hibernate_pwr_on3_delay_adj [21:18] - hibernate_pwr_on3_delay [17:16] - hibernate_pwr_on2_delay_adj [15:12] - hibernate_pwr_on2_delay [11:10] - .."
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group ad:0xF0060054++0x03
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line.long 0x00 "SW_OVERRIDE,software override controls"
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bitfld.long 0x00 31. " SW_SF_HV_ISO_EN_ASSERT ,Write '1' to force sf_hv_iso_en asserted. When this bit is set, sf_hv_iso_en keeps asserted. When it's asserted, SW_SF_HV_ISO_EN_DEASSERT bit ignored. It's NOT self-clear bit, and it's for debug only." "0,1"
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bitfld.long 0x00 30. " SW_SF_HV_ISO_EN_DEASSERT ,Write '1' to force sf_hv_iso_en de-asserted. When this bit is set, sf_hv_iso_en keeps de-asserted. It's lower priority than SW_SF_HV_ISO_EN_ASSERT. It's NOT self-clear bit, and it's for debug only." "0,1"
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bitfld.long 0x00 29. " SW_AP_HV_ISO_EN_ASSERT ,Write '1' to force ap_hv_iso_en asserted. When this bit is set, ap_hv_iso_en keeps asserted. When it's asserted, SW_AP_HV_ISO_EN_DEASSERT bit ignored. It's NOT self-clear bit, and it's for debug only." "0,1"
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bitfld.long 0x00 28. " SW_AP_HV_ISO_EN_DEASSERT ,Write '1' to force ap_hv_iso_en de-asserted. When this bit is set, ap_hv_iso_en keeps de-asserted. It's lower priority than SW_AP_HV_ISO_EN_ASSERT. It's NOT self-clear bit, and it's for debug only." "0,1"
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textline " "
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bitfld.long 0x00 27. "SW_SF_POR_B_ASSERT ,write to assert sf_por_b. It's a self cleared bit. Be careful!!! Once this bit is set, sf_por_b keeps asserted, unless software set SW_SF_POR_B_DEASSERT bit." "0,1"
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bitfld.long 0x00 26. " SW_SF_POR_B_DEASSERT ,write to de-assert sf_por_b. It's a self cleared bit." "0,1"
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bitfld.long 0x00 25. " SW_SF_ISO_EN_ASSERT ,write to assert sf_iso_en. It's a self cleared bit." "0,1"
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bitfld.long 0x00 24. " SW_SF_ISO_EN_DEASSERT ,write to de-assert sf_iso_en. It's a self cleared bit." "0,1"
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textline " "
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bitfld.long 0x00 23. "SW_AP_POR_B_ASSERT ,write to assert ap_por_b. It's a self cleared bit. Be careful!!! Once this bit is set, ap_por_b keeps asserted, unless software set SW_AP_POR_B_DEASSERT bit." "0,1"
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bitfld.long 0x00 22. " SW_AP_POR_B_DEASSERT ,write to de-assert ap_por_b. It's a self cleared bit." "0,1"
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bitfld.long 0x00 21. " SW_AP_ISO_EN_ASSERT ,write to assert ap_iso_en. It's a self cleared bit." "0,1"
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bitfld.long 0x00 20. " SW_AP_ISO_EN_DEASSERT ,write to de-assert ap_iso_en. It's a self cleared bit." "0,1"
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textline " "
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bitfld.long 0x00 19. "SW_AP_HV_ISO_EN_EN ,override enable of ap_hv_iso_en" "0,1"
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bitfld.long 0x00 18. " SW_AP_HV_ISO_EN ,override value of ap_hv_iso_en" "0,1"
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bitfld.long 0x00 17. " SW_SF_HV_ISO_EN_EN ,override enable of sf_hv_iso_en" "0,1"
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bitfld.long 0x00 16. " SW_SF_HV_ISO_EN ,override value of sf_hv_iso_en" "0,1"
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textline " "
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bitfld.long 0x00 15. "SW_AP_ISO_EN_EN ,override enable of ap_iso_en" "0,1"
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bitfld.long 0x00 14. " SW_AP_ISO_EN ,override value of ap_iso_en" "0,1"
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bitfld.long 0x00 13. " SW_SF_ISO_EN_EN ,override enable of sf_iso_en" "0,1"
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bitfld.long 0x00 12. " SW_SF_ISO_EN ,override value of sf_iso_en" "0,1"
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textline " "
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bitfld.long 0x00 11. "SW_AP_POR_B_EN ,override enable of ap_por_b" "0,1"
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bitfld.long 0x00 10. " SW_AP_POR_B ,override value of ap_por_b" "0,1"
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bitfld.long 0x00 9. " SW_SF_POR_B_EN ,override enable of sf_por_b" "0,1"
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bitfld.long 0x00 8. " SW_SF_POR_B ,override value of sf_por_b" "0,1"
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textline " "
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bitfld.long 0x00 4.--7. "SW_PWR_ON_EN ,override enable of pwr_on0-3 [3] - pwr_on3 [2] - pwr_on2 [1] - pwr_on1 [0] - pwr_on0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SW_PWR_ON ,override value of pwr_on0-3 [3] - pwr_on3 [2] - pwr_on2 [1] - pwr_on1 [0] - pwr_on0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0060058++0x03
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line.long 0x00 "PG_LP_MODE_CTRL,power good and lp_mode controls"
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bitfld.long 0x00 28.--31. " run_lp_mode ,lp_mode[3:0] in run state [3] - lp_mode[3] [2] - lp_mode[2] [1] - lp_mode[1] [0] - lp_mode[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. " sleep_lp_mode ,lp_mode[3:0] in sleep state [3] - lp_mode[3] [2] - lp_mode[2] [1] - lp_mode[1] [0] - lp_mode[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. " hibernate_lp_mode ,lp_mode[3:0] in hibernate state [3] - lp_mode[3] [2] - lp_mode[2] [1] - lp_mode[1] [0] - lp_mode[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 17. " RTC_LV_MONITOR ,monitor rtc_sf_lv_pg/sf_lv_pg and rtc_ap_lv_pg/ap_lv_pg, when enabled Once rtc_sf_lv_pg and sf_lv_pg or rtc_ap_lv_pg and ap_lv_pg is de-asserted, asserts the sf_lv_iso_en/sf_por_b or ap_lv_iso_en/ap_por_b; Once .." "0,1"
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textline " "
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bitfld.long 0x00 16. "RTC_HV_MONITOR ,monitor rtc_sf_hv_pg and rtc_ap_hv_pg, when enabled Once rtc_sf_hv_pg or rtc_ap_hv_pg is de-asserted, asserts the sf_hv_iso_en or ap_hv_iso_en; Once rtc_sf_hv_pg or rtc_ap_hv_pg is re-asserted, de-asserts the sf_hv_iso_en .." "0,1"
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bitfld.long 0x00 15. " RTC_SF_HV_PG_DISABLE ,DIsable rtc_sf_hv_pg 1 - DIsable" "0,1"
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bitfld.long 0x00 14. " SF_HV_PG_DISABLE ,DIsable sf_hv_pg 1 - DIsable" "0,1"
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bitfld.long 0x00 13. " RTC_AP_HV_PG_DISABLE ,DIsable rtc_ap_hv_pg 1 - DIsable" "0,1"
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textline " "
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bitfld.long 0x00 12. "AP_HV_PG_DISABLE ,DIsable ap_hv_pg 1 - DIsable" "0,1"
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bitfld.long 0x00 11. " RTC_SF_LV_PG_DISABLE ,DIsable rtc_sf_lv_pg 1 - DIsable" "0,1"
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bitfld.long 0x00 10. " SF_LV_PG_DISABLE ,DIsable sf_lv_pg 1 - DIsable" "0,1"
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bitfld.long 0x00 9. " RTC_AP_LV_PG_DISABLE ,DIsable rtc_ap_lv_pg 1 - DIsable" "0,1"
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textline " "
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bitfld.long 0x00 8. "AP_LV_PG_DISABLE ,DIsable ap_lv_pg 1 - DIsable" "0,1"
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bitfld.long 0x00 4.--7. " SW_LP_MODE_EN ,override enable of LP_MODE[3:0] [3] - lp_mode[3] [2] - lp_mode[2] [1] - lp_mode[1] [0] - lp_mode[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SW_LP_MODE ,override value of LP_MODE[3:0] [3] - lp_mode[3] [2] - lp_mode[2] [1] - lp_mode[1] [0] - lp_mode[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF006005C++0x03
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line.long 0x00 "MIN_DELAY_STATE_TRAN,minimal delay for state transition"
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hexmask.long.byte 0x00 24.--29. 1. " HIBERNATE_RUN_DELAY_MIN ,minimum delay setting between HIBERNATE and RUN state. [5:4] - delay_adj [3:0] - delay Delay = 2^(*_delay) x (*_delay_adjx2+1)"
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hexmask.long.byte 0x00 16.--21. 1. " SLEEP_RUN_DELAY_MIN ,minimum delay setting between SLEEP and RUN state. [5:4] - delay_adj [3:0] - delay Delay = 2^(*_delay) x (*_delay_adjx2+1)"
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hexmask.long.byte 0x00 8.--13. 1. " PWR_UP_RUN_DELAY_MIN ,minimum delay setting between power up and run state. [5:4] - delay_adj [3:0] - delay Delay = 2^(*_delay) x (*_delay_adjx2+1)"
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hexmask.long.byte 0x00 0.--5. 1. " PWR_ON_ISO_DELAY ,delay setting between power good and de-asserting isolation enable signal: [5:4] - pg to isolation de-assertion delay_adj [3:0] - pg to isolation de-assertion delay Delay = 2^(*_delay) x (*_delay_adjx2+1.."
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group ad:0xF0060060++0x03
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line.long 0x00 "LP_CTRL_ON_FRC,force hw_pwr_ctrl*, hw_pwr_on*, lp_mode* to 0 or 1"
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bitfld.long 0x00 23. " pwr_on3_assert ,write to assert pwr_on3. It's a self cleared bit." "0,1"
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bitfld.long 0x00 22. " pwr_on2_assert ,write to assert pwr_on2. It's a self cleared bit." "0,1"
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bitfld.long 0x00 21. " pwr_on1_assert ,write to assert pwr_on1. It's a self cleared bit." "0,1"
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bitfld.long 0x00 20. " pwr_on0_assert ,write to assert pwr_on0. It's a self cleared bit." "0,1"
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textline " "
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bitfld.long 0x00 19. "pwr_on3_deassert ,write to de-assert pwr_on3. It's a self cleared bit." "0,1"
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bitfld.long 0x00 18. " pwr_on2_deassert ,write to de-assert pwr_on2. It's a self cleared bit." "0,1"
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bitfld.long 0x00 17. " pwr_on1_deassert ,write to de-assert pwr_on1. It's a self cleared bit." "0,1"
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bitfld.long 0x00 16. " pwr_on0_deassert ,write to de-assert pwr_on0. It's a self cleared bit." "0,1"
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textline " "
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bitfld.long 0x00 15. "pwr_ctrl3_assert ,write to assert pwr_ctrl3. It's a self cleared bit." "0,1"
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bitfld.long 0x00 14. " pwr_ctrl2_assert ,write to assert pwr_ctrl2. It's a self cleared bit." "0,1"
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bitfld.long 0x00 13. " pwr_ctrl1_assert ,write to assert pwr_ctrl1. It's a self cleared bit." "0,1"
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bitfld.long 0x00 12. " pwr_ctrl0_assert ,write to assert pwr_ctrl0. It's a self cleared bit." "0,1"
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textline " "
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bitfld.long 0x00 11. "pwr_ctrl3_deassert ,write to de-assert pwr_ctrl3. It's a self cleared bit." "0,1"
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bitfld.long 0x00 10. " pwr_ctrl2_deassert ,write to de-assert pwr_ctrl2. It's a self cleared bit." "0,1"
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bitfld.long 0x00 9. " pwr_ctrl1_deassert ,write to de-assert pwr_ctrl1. It's a self cleared bit." "0,1"
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bitfld.long 0x00 8. " pwr_ctrl0_deassert ,write to de-assert pwr_ctrl0. It's a self cleared bit." "0,1"
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textline " "
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bitfld.long 0x00 7. "lp_mode3_assert ,write to assert lp_mode3. It's a self cleared bit." "0,1"
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bitfld.long 0x00 6. " lp_mode2_assert ,write to assert lp_mode2. It's a self cleared bit." "0,1"
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bitfld.long 0x00 5. " lp_mode1_assert ,write to assert lp_mode1. It's a self cleared bit." "0,1"
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bitfld.long 0x00 4. " lp_mode0_assert ,write to assert lp_mode0. It's a self cleared bit." "0,1"
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textline " "
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bitfld.long 0x00 3. "lp_mode3_deassert ,write to de-assert lp_mode3. It's a self cleared bit." "0,1"
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bitfld.long 0x00 2. " lp_mode2_deassert ,write to de-assert lp_mode2. It's a self cleared bit." "0,1"
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bitfld.long 0x00 1. " lp_mode1_deassert ,write to de-assert lp_mode1. It's a self cleared bit." "0,1"
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bitfld.long 0x00 0. " lp_mode0_deassert ,write to de-assert lp_mode0. It's a self cleared bit." "0,1"
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group ad:0xF0060064++0x03
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line.long 0x00 "PMU_SW_RESET,software reset"
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bitfld.long 0x00 23.--24. " PWR_DOWN_WAKEUP_EN ,enable power down and auto wake up sequence for fatal errors: [0]: 1 - to enable power down and auto wake up sequence when SWM reset checking is failing; [1]: 1 - reserved" "0,1,2,3"
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bitfld.long 0x00 22. " PWR_DOWN_WAKEUP_TST ,set 1 to trigger auto powerdown and auto wakeup flow. It's valid only when PWR_DOWN_WAKEUP_EN[0] is set. It's a self-clear bit. After setting this bit, if PWR_DOWN_WAKEUP_EN[0] is set, PMU will trigger auto power .." "0,1"
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bitfld.long 0x00 5. " PMU_AP_POR_B_TOGGLE ,set 1 to assert and then de-assert AP_POR_B It's a self-clear bit. After setting this bit, ap_por_b is asserted for one 32Khz clock cycle, then ap_por_b is de-asserted automatically." "0,1"
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bitfld.long 0x00 4. " PMU_SF_POR_B_TOGGLE ,set 1 to assert and then de-assert SF_POR_B It's a self-clear bit. After setting this bit, sf_por_b is asserted for one 32Khz clock cycle, then sf_por_b is de-asserted automatically." "0,1"
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textline " "
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bitfld.long 0x00 1. "PMU_SW_RESET_LOCK ,set 1 to lock pmu_sw_reset bit." "0,1"
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bitfld.long 0x00 0. " pmu_sw_reset ,write 1 to trigger warm reset. It triggers the global reset, and it is self-cleared two 32Khz cycles later." "0,1"
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group ad:0xF0060068++0x03
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line.long 0x00 "PMU_INT,Interrupt of PMU"
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hexmask.long.word 0x00 16.--28. 1. " pmu_int_en ,interrupt enable bits for PMU_INT[15:0]"
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bitfld.long 0x00 12. " pwr_down_req ,power down request: 1. BC triggered power down; 2. Software triggered power down; 3. Hardware triggered power down;" "0,1"
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bitfld.long 0x00 11. " swm_fatal ,PMU detected SMC is not well-reseted." "0,1"
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bitfld.long 0x00 10. " swm_warn ,SWM request from SMC is illegal: 1. illegal swm[3:0] from SMC. i.e., none one hot; 2. swm[3:0] changes from SLEEP to HIBERNATE, or from HIBERNATE to SLEEP; 3. swm_req from SMC is deasserted before swm_ack from PMU is.." "0,1"
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textline " "
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bitfld.long 0x00 9. "RSV1 ,Reserved" "0,1"
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bitfld.long 0x00 8. " RSV0 ,Reserved" "0,1"
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bitfld.long 0x00 7. " LOCKSTEP_ERR_REBOOTED ,lockstep error triggered reboot happened" "0,1"
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bitfld.long 0x00 6. " HIBERNATE_TO_RUN_REBOOTED ,hibernate to run timeout triggered reboot happened" "0,1"
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textline " "
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bitfld.long 0x00 5. "SLEEP_TO_RUN_REBOOTED ,sleep to run timeout triggered reboot happened" "0,1"
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bitfld.long 0x00 4. " PWRUP_TO_RUN_REBOOTED ,pwr_up to run timeout triggered reboot happened" "0,1"
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bitfld.long 0x00 3. " pwr_on3_wdt_err ,interrupt of pwr_on3 to pwr_rdy timeout" "0,1"
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bitfld.long 0x00 2. " pwr_on2_wdt_err ,interrupt of pwr_on2 to pwr_rdy timeout" "0,1"
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textline " "
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bitfld.long 0x00 1. "pwr_on1_wdt_err ,interrupt of pwr_on1 to pwr_rdy timeout" "0,1"
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bitfld.long 0x00 0. " pwr_on0_wdt_err ,interrupt of pwr_on0 to pwr_rdy timeout" "0,1"
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group ad:0xF006006C++0x03
|
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line.long 0x00 "PMU_COR_UNCOR_INT,correctable/uncorrectable Interrupts of PMU"
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bitfld.long 0x00 24. " pmu_cor_int_en ,interrupt enable bits for PMU_COR_INT[7:0] [24] - enable bit of the PMU APB write data correctable error interrupt" "0,1"
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bitfld.long 0x00 16.--20. " pmu_uncor_int_en ,interrupt enable bits for PMU_COR_UNCOR_INT[7:0] [20] - enable bit of the PMU APB write data fatal error interrupt [19] - enable bit of the PMU APB write data un-correctable error interrupt [18] - enable bit of the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8. " pmu_pwdata_cor_err ,interrupt of PMU APB write data correctable error" "0,1"
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bitfld.long 0x00 4. " pmu_pwdata_fatal_err ,interrupt of PMU APB write data fatal error" "0,1"
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textline " "
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bitfld.long 0x00 3. "pmu_pwdata_unc_err ,interrupt of PMU APB write data un-correctable error" "0,1"
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bitfld.long 0x00 2. " pmu_paddr_unc_err ,interrupt of PMU APB address un-correctable error interrupt for APB write" "0,1"
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bitfld.long 0x00 1. " pmu_pn_pair_err ,interrupt of *_p/*_n signal pair compare error" "0,1"
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bitfld.long 0x00 0. " pmu_lockstep_err ,interrupt of PMU lockstep error" "0,1"
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group ad:0xF0060070++0x03
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line.long 0x00 "SRCS_BITS,32bits state retention bits"
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hexmask.long 0x00 0.--31. 1. " SRCS_BITS ,state retention control signal bits low 16 bits can only be reseted by cold reset (power on reset); high 16 bits can be reseted by cold reset or PMU's software reset."
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group ad:0xF0060074++0x03
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line.long 0x00 "SRCS_BITS_SET,32bits state retention bits."
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hexmask.long 0x00 0.--31. 1. " SRCS_BITS ,write '1' will set the corresponDIng state retention control signal bits low 16 bits can only be reseted by cold reset (power on reset); high 16 bits can be reseted by cold reset or PMU's software reset."
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group ad:0xF0060078++0x03
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line.long 0x00 "SRCS_BITS_CLR,32bits state retention bits."
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hexmask.long 0x00 0.--31. 1. " SRCS_BITS ,write '1' will clear the corresponDIng state retention control signal bits low 16 bits can only be reseted by cold reset (power on reset); high 16 bits can be reseted by cold reset or PMU's software reset."
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group ad:0xF006007C++0x03
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line.long 0x00 "SRCS_BITS_TOG,32bits state retention bits."
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hexmask.long 0x00 0.--31. 1. " SRCS_BITS ,write '1' will toggle the corresponDIng state retention control signal bits low 16 bits can only be reseted by cold reset (power on reset); high 16 bits can be reseted by cold reset or PMU's software reset."
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|
group ad:0xF0060080++0x03
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|
line.long 0x00 "PMU_DOWN_UP_STATUS,PMU power down request and wake up event source status"
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|
bitfld.long 0x00 15. " PWR_DWN_SOURCE11 ,PMU power down request source11: External power down request by BC button" "0,1"
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|
bitfld.long 0x00 14. " PWR_DWN_SOURCE10 ,PMU power down request source10: software power down request" "0,1"
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|
bitfld.long 0x00 13. " PWR_DWN_SOURCE9 ,PMU power down request source9: SoC internal emergency power down request[7]" "0,1"
|
|
bitfld.long 0x00 12. " PWR_DWN_SOURCE8 ,PMU power down request source8: SoC internal emergency power down request[6]" "0,1"
|
|
textline " "
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|
bitfld.long 0x00 11. "PWR_DWN_SOURCE7 ,PMU power down request source7: SoC internal emergency power down request[5]" "0,1"
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|
bitfld.long 0x00 10. " PWR_DWN_SOURCE6 ,PMU power down request source6: SoC internal emergency power down request[4]" "0,1"
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|
bitfld.long 0x00 9. " PWR_DWN_SOURCE5 ,PMU power down request source5: SoC internal emergency power down request[3]" "0,1"
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|
bitfld.long 0x00 8. " PWR_DWN_SOURCE4 ,PMU power down request source4: SoC internal emergency power down request[2]" "0,1"
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|
textline " "
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|
bitfld.long 0x00 7. "PWR_DWN_SOURCE3 ,PMU power down request source3: SoC internal emergency power down request[1]" "0,1"
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|
bitfld.long 0x00 6. " PWR_DWN_SOURCE2 ,PMU power down request source2: SoC internal emergency power down request[0]" "0,1"
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|
bitfld.long 0x00 5. " PWR_DWN_SOURCE1 ,PMU power down request source1: Reserved" "0,1"
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|
bitfld.long 0x00 4. " PWR_DWN_SOURCE0 ,PMU power down request source0: SMC reset check fail" "0,1"
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|
textline " "
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|
bitfld.long 0x00 3. "WAKEUP_SOURCE3 ,PMU wake up source3: auto wake up which is triggered by hardware power down request (lockstep error or SMC reset check error)" "0,1"
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|
bitfld.long 0x00 2. " WAKEUP_SOURCE2 ,PMU wake up source2: wake up by wake up button" "0,1"
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|
bitfld.long 0x00 1. " WAKEUP_SOURCE1 ,PMU wake up source1: wake up by SoC RealTimeCounter perioDIc interrupt" "0,1"
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|
bitfld.long 0x00 0. " WAKEUP_SOURCE0 ,PMU wake up source0: wake up by external power on request by BC button" "0,1"
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|
group ad:0xF0060084++0x03
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|
line.long 0x00 "PMU_STATE,PMU internal state machine"
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|
bitfld.long 0x00 15. " RTC_AP_HV_PG ,status of RTC_AP_HV_PG" "0,1"
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|
bitfld.long 0x00 14. " RTC_AP_LV_PG ,status of RTC_AP_LV_PG" "0,1"
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|
bitfld.long 0x00 13. " RTC_SF_HV_PG ,status of RTC_SF_HV_PG" "0,1"
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|
bitfld.long 0x00 12. " RTC_SF_LV_PG ,status of RTC_SF_LV_PG" "0,1"
|
|
textline " "
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|
bitfld.long 0x00 11. "AP_HV_PG ,status of AP_HV_PG" "0,1"
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|
bitfld.long 0x00 10. " AP_LV_PG ,status of AP_LV_PG" "0,1"
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|
bitfld.long 0x00 9. " SF_HV_PG ,status of SF_HV_PG" "0,1"
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|
bitfld.long 0x00 8. " SF_LV_PG ,status of SF_LV_PG" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. "PWR_RDY ,power ready status of the power supplies which are controlled by pwr_on[3:0], after asserting/de-asserting pwr_on[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--2. " PMU_STATE ,PMU state machine: 000: PWR_UP 001: RUN 010: SLEEP 011: HIBERNATE 100: RTC 101: OFF" "0,1,2,3,4,5,6,7"
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|
group ad:0xF0060088++0x03
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|
line.long 0x00 "ERR_INJECTION,Error injection"
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|
bitfld.long 0x00 31. " err_inj_en ,Error injection enable" "0,1"
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|
hexmask.long.byte 0x00 16.--23. 1. " err_inj_en_sel ,select which function enables error injection. Only one bit should be set to 1. [16] - lockstep is selected to inject error. [17] - pmu_irq is selected to inject error. [18] - pmu apb write monitor is selected to .."
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|
hexmask.long.byte 0x00 0.--7. 1. " err_inject_bits ,the bit which injects the error"
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|
group ad:0xF006008C++0x03
|
|
line.long 0x00 "ERR_INJECTION_WDATA,Error injection bits for APB wdata[31:0] of apb wdata monitor."
|
|
hexmask.long 0x00 0.--31. 1. " err_injection_wdata ,Error injection bits for APB wdata[31:0] of apb wdata monitor."
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|
group ad:0xF00600F0++0x03
|
|
line.long 0x00 "ISTC_DEBUG,ISTC debug controls. See details in ISTC chapter. Can only be reset by HW POR (EXT_POR pad or INT_POR from POR cell). Can't be reset by SW POR."
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|
hexmask.long 0x00 0.--31. 1. " ISTC_DEBUG ,ISTC debug controls. See details in ISTC chapter. Can only be reset by HW POR (EXT_POR pad or INT_POR from POR cell). Can't be reset by SW POR."
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|
group ad:0xF0068000++0x03
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|
line.long 0x00 "PMU_LOCKSTEP_STATUS,PMU read status in 'update' window. Software should follow below flow to check the lockstep correctness between core #0 and core #1: 1. read core #0 register bits, offset #A, get rd_data_0; 2. read core #1 register bits, offset #A.."
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|
hexmask.long.word 0x00 16.--31. 1. " CUR_RD_ADDR ,The latest PMU core #0 or #1 read address."
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|
bitfld.long 0x00 2. " PRE2_RD_UPDATE ,PMU 2nd previous core #0 or core #1 read happens during PMU core #1 software register bits are in updating cycle. Here, '2nd previous means the read before previous read'." "0,1"
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|
bitfld.long 0x00 1. " PRE_RD_UPDATE ,PMU previous core #0 or core #1 read happens during PMU core #1 software register bits are in updating cycle." "0,1"
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|
bitfld.long 0x00 0. " CUR_RD_UPDATE ,PMU latest core #0 or core #1 read happens during PMU core #1 software register bits are in updating cycle." "0,1"
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|
group ad:0xF0068004++0x03
|
|
line.long 0x00 "PMU_APB_INT,PMU APB domain interrupts status"
|
|
bitfld.long 0x00 3. " APB_PN_CHK_ERR ,_P/_N pair check error interrupt status of PMU APB domain. write '1' to clear" "0,1"
|
|
bitfld.long 0x00 2. " APB_PCTL_UNC_ERR ,PCTL un-correctable error interrupt status of PMU APB domain. write '1' to clear" "0,1"
|
|
bitfld.long 0x00 1. " APB_PADDR_UNC_ERR ,PADDR un-correctable error interrupt status of PMU APB domain. write '1' to clear" "0,1"
|
|
bitfld.long 0x00 0. " APB_LKSTEP_ERR ,lock step error interrupt status of PMU APB domain. write '1' to clear" "0,1"
|
|
group ad:0xF0068008++0x03
|
|
line.long 0x00 "PMU_APB_INT_EN,PMU APB domain interrupts enable"
|
|
bitfld.long 0x00 3. " APB_PN_CHK_ERR_EN ,_P/_N check error interrupt enable of PMU APB domain." "0,1"
|
|
bitfld.long 0x00 2. " APB_PCTL_UNC_ERR_EN ,PCTL un-correctable error interrupt enable of PMU APB domain." "0,1"
|
|
bitfld.long 0x00 1. " APB_PADDR_UNC_ERR_EN ,PADDR un-correctable error interrupt enable of PMU APB domain." "0,1"
|
|
bitfld.long 0x00 0. " APB_LKSTEP_ERR_EN ,lock step error interrupt enable of PMU APB domain." "0,1"
|
|
group ad:0xF006800C++0x03
|
|
line.long 0x00 "APB_ERR_INJECTION,Error injection of PMU APB clock domain"
|
|
bitfld.long 0x00 8. " APB_ERROR_INJ_EN ,Error injection enable of PMU APB clock domain" "0,1"
|
|
bitfld.long 0x00 7. " APB_ERROR_INJ_SEL ,Error injection selection of PMU APB clock domain 0 - lockstep of APB clock domain error injection is selected 1 - uncor_int_n of APB clock domain error injection is selected" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " APB_ERROR_INJ_BIT ,Error injection bits of PMU APB clock domain"
|
|
tree.end
|
|
config 16. 8.
|
|
tree "RSTGEN"
|
|
tree "RSTGEN_SF"
|
|
width 27.
|
|
group ad:0xF0690000++0x03
|
|
line.long 0x00 "DOM_PER0_0,This register is used to control domain0~3 secure and priviledge access permission."
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bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
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bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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group ad:0xF0690004++0x03
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line.long 0x00 "DOM_PER1_0,This register is used for to control domain4~7 secure and priviledge access permission."
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bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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textline " "
|
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bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
group ad:0xF0690008++0x03
|
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line.long 0x00 "DOM_PER_LOCK_0,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
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bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF069000C++0x03
|
|
line.long 0x00 "DOM_PER0_1,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690010++0x03
|
|
line.long 0x00 "DOM_PER1_1,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690014++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_1,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0690018++0x03
|
|
line.long 0x00 "DOM_PER0_2,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF069001C++0x03
|
|
line.long 0x00 "DOM_PER1_2,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690020++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_2,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0690024++0x03
|
|
line.long 0x00 "DOM_PER0_3,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690028++0x03
|
|
line.long 0x00 "DOM_PER1_3,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF069002C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_3,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0690030++0x03
|
|
line.long 0x00 "DOM_PER0_4,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690034++0x03
|
|
line.long 0x00 "DOM_PER1_4,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690038++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_4,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF069003C++0x03
|
|
line.long 0x00 "DOM_PER0_5,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690040++0x03
|
|
line.long 0x00 "DOM_PER1_5,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690044++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_5,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0690048++0x03
|
|
line.long 0x00 "DOM_PER0_6,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF069004C++0x03
|
|
line.long 0x00 "DOM_PER1_6,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690050++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_6,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0690054++0x03
|
|
line.long 0x00 "DOM_PER0_7,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0690058++0x03
|
|
line.long 0x00 "DOM_PER1_7,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF069005C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_7,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0690200++0x03
|
|
line.long 0x00 "GLOBAL_RESET_RS,This register is used for assign rule space for global reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0690204++0x03
|
|
line.long 0x00 "GLOBAL_RESET_CONTROL,This register is used for global reset control"
|
|
bitfld.long 0x00 31. " SS_RDY ,ss ready inDIcation for saf: ap_sys ready inDIcation for ap: DIsp_ss/ap_ss ready inDIcation" "0,1"
|
|
bitfld.long 0x00 29. " TEST_IST_EN ,test state ist done fail or timeout trigger cold_rst_req enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 28. " SW_GLB_RST ,software global reset." "0,1"
|
|
bitfld.long 0x00 27. " SW_GLB_RST_EN ,software global reset enable 0: DIsable 1: enable" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 19.--26. 1. "RST_REQ_EN ,reset request cause global reset enable 0: DIsable 1: enable"
|
|
hexmask.long.byte 0x00 11.--18. 1. " WDT2_EN ,WDT2 cause global reset enable 0: DIsable 1: enable bit[7:6]: reserved bit[5]: wdt6_int_rst_req bit[4]: wdt6_int_rst_req bit[3]: wdt4_int_rst_req bit[2]: wdt4_int_rst_req bit[1]: wdt2_int_rst_req bit[0]: reserved.."
|
|
hexmask.long.byte 0x00 3.--10. 1. " WDT1_EN ,WDT1 cause global reset enable 0: DIsable 1: enable bit[7:6]: reserved bit[5]: wdt5_int_rst_req bit[4]: wdt5_int_rst_req bit[3]: wdt3_int_rst_req bit[2]: wdt3_int_rst_req bit[1]: wdt1_int_rst_req bit[0]: reserved.."
|
|
bitfld.long 0x00 2. " SEC_VIO_EN ,security violation cause global reset enable 0: DIsable 1: enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEM_EN ,sem cause global reset enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " SYS_PANIC_EN ,system panic cause global reset enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0690208++0x03
|
|
line.long 0x00 "GLOBAL_RESET_STA,GLOBAL RESET STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GLB_STA_LAST ,global reset status for the last time. If multiple reset source comes nearly the same time, only the first one will be recorded. For rstgen_sf: bit[31:25]: reserved bit[24]: wdt6_int_rst_req. bit[23]: wdt6_int_rst_req. bit[22]: .."
|
|
group ad:0xF069020C++0x03
|
|
line.long 0x00 "GLOBAL_RESET_STA_ALL,GLOBAL RESET STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GLB_STA_ALL ,global reset status for all the time. If multiple reset source comes nearly the same time, only the first one will be recorded. For rstgen_sf: bit[31:25]: reserved bit[24]: wdt6_int_rst_req. bit[23]: wdt6_int_rst_req. bit[22]: .."
|
|
group ad:0xF0690210++0x03
|
|
line.long 0x00 "GLOBAL_ERR_STA_ALL,GLOBAL ERROR STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_STA_ALL ,rstgen record error status input for all the time no matter it triggers global reset or not For rstgen_sf: bit[31:25]: reserved bit[24]: wdt6_int_rst_req. bit[23]: wdt6_int_rst_req. bit[22]: wdt4_int_rst_req. bit[21]: .."
|
|
group ad:0xF0691000++0x03
|
|
line.long 0x00 "IST_RESET_RS,This register is used for assign rule space for ist reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691004++0x03
|
|
line.long 0x00 "IST_RESET_CONTROL,This register is used for ist reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 6. " AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691100++0x03
|
|
line.long 0x00 "MISSION_RESET_RS_0,This register is used for assign rule space for mission reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691104++0x03
|
|
line.long 0x00 "MISSION_RESET_CONTROL_0,This register is used for mission reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 28. " LOCK ,lock bit, set to 1 to lock run_mode/slp_mode/hib_mode/auto_clr_rst_b and lock itself." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691200++0x03
|
|
line.long 0x00 "LATENT_RESET_RS_0,This register is used for assign rule space for latent reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691204++0x03
|
|
line.long 0x00 "LATENT_RESET_CONTROL_0,This register is used for latent reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 28. " LOCK ,lock bit, set to 1 to lock run_mode/slp_mode/hib_mode/auto_clr_rst_b and lock itself." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691300++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_0,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691304++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_0,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691308++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_1,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069130C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_1,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691310++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_2,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691314++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_2,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691318++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_3,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069131C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_3,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691320++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_4,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691324++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_4,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691328++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_5,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069132C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_5,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691330++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_6,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691334++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_6,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691338++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_7,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069133C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_7,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691340++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_8,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691344++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_8,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691348++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_9,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069134C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_9,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691350++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_10,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691354++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_10,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691358++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_11,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069135C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_11,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691360++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_12,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691364++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_12,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691368++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_13,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069136C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_13,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691370++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_14,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691374++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_14,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691378++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_15,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069137C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_15,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691380++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_16,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691384++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_16,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691388++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_17,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069138C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_17,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691390++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_18,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691394++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_18,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691398++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_19,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069139C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_19,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913A0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_20,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913A4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_20,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913A8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_21,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913AC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_21,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913B0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_22,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913B4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_22,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913B8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_23,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913BC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_23,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913C0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_24,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913C4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_24,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913C8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_25,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913CC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_25,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913D0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_26,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913D4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_26,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913D8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_27,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913DC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_27,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913E0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_28,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913E4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_28,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913E8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_29,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913EC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_29,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913F0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_30,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913F4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_30,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06913F8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_31,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06913FC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_31,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691400++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_32,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691404++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_32,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691408++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_33,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069140C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_33,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691410++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_34,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691414++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_34,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691418++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_35,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069141C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_35,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691420++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_36,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691424++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_36,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691428++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_37,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069142C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_37,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691430++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_38,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691434++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_38,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691438++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_39,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069143C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_39,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691440++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_40,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691444++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_40,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691448++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_41,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069144C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_41,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691450++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_42,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691454++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_42,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691458++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_43,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069145C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_43,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691460++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_44,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691464++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_44,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691468++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_45,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069146C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_45,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691470++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_46,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691474++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_46,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691478++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_47,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069147C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_47,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691480++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_48,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691484++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_48,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691488++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_49,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069148C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_49,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691490++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_50,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691494++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_50,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691498++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_51,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069149C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_51,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914A0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_52,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914A4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_52,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914A8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_53,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914AC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_53,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914B0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_54,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914B4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_54,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914B8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_55,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914BC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_55,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914C0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_56,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914C4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_56,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914C8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_57,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914CC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_57,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914D0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_58,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914D4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_58,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914D8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_59,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914DC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_59,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914E0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_60,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914E4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_60,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914E8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_61,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914EC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_61,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914F0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_62,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914F4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_62,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF06914F8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_63,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF06914FC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_63,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691A00++0x03
|
|
line.long 0x00 "CORE_RESET_RS_0,This register is used for assign rule space for core reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691A04++0x03
|
|
line.long 0x00 "CORE_RESET_CONTROL_0,This register is used for core reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 5. " RST_REQ_EN ,reset request enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 4. " WDT2_RST_EN ,wdt2 reset enable 0: DIsable 1: enable wdt1 reset or wdt2 reset will trigger core reset happen" "0,1"
|
|
bitfld.long 0x00 3. " WDT1_RST_EN ,wdt1 reset enable 0: DIsable 1: enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691B00++0x03
|
|
line.long 0x00 "DBG_RESET_RS,This register is used for assign rule space for dbg reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0691B04++0x03
|
|
line.long 0x00 "DBG_RESET_CONTROL,This register is used for dbg reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8. " DBG_REQ_EN ,dbg request enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF0691C00++0x03
|
|
line.long 0x00 "SW_RESET_PASSWORD_CONTROL,SW RESET PASSWORD CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock for this registere" "0,1"
|
|
bitfld.long 0x00 0. " EN ,sw reset password enable 0: no need password 1: password needed" "0,1"
|
|
group ad:0xF0691C04++0x03
|
|
line.long 0x00 "SW_RESET_PASSWORD,This register is used for protecting un-expected sw reset"
|
|
hexmask.long 0x00 0.--31. 1. " PW ,sw reset password"
|
|
group ad:0xF0692000++0x03
|
|
line.long 0x00 "GENERAL_REG_RS_0,This register is used for assign rule space for general reigster"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0692004++0x03
|
|
line.long 0x00 "GENERAL_REG_0,This register is used for general purpose"
|
|
hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
|
|
group ad:0xF0692008++0x03
|
|
line.long 0x00 "GENERAL_REG_RS_1,This register is used for assign rule space for general reigster"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069200C++0x03
|
|
line.long 0x00 "GENERAL_REG_1,This register is used for general purpose"
|
|
hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
|
|
group ad:0xF0692010++0x03
|
|
line.long 0x00 "GENERAL_REG_RS_2,This register is used for assign rule space for general reigster"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0692014++0x03
|
|
line.long 0x00 "GENERAL_REG_2,This register is used for general purpose"
|
|
hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
|
|
group ad:0xF0692018++0x03
|
|
line.long 0x00 "GENERAL_REG_RS_3,This register is used for assign rule space for general reigster"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069201C++0x03
|
|
line.long 0x00 "GENERAL_REG_3,This register is used for general purpose"
|
|
hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
|
|
group ad:0xF0692020++0x03
|
|
line.long 0x00 "GENERAL_REG_RS_4,This register is used for assign rule space for general reigster"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0692024++0x03
|
|
line.long 0x00 "GENERAL_REG_4,This register is used for general purpose"
|
|
hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
|
|
group ad:0xF0692028++0x03
|
|
line.long 0x00 "GENERAL_REG_RS_5,This register is used for assign rule space for general reigster"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069202C++0x03
|
|
line.long 0x00 "GENERAL_REG_5,This register is used for general purpose"
|
|
hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
|
|
group ad:0xF0692030++0x03
|
|
line.long 0x00 "GENERAL_REG_RS_6,This register is used for assign rule space for general reigster"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0692034++0x03
|
|
line.long 0x00 "GENERAL_REG_6,This register is used for general purpose"
|
|
hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
|
|
group ad:0xF0692038++0x03
|
|
line.long 0x00 "GENERAL_REG_RS_7,This register is used for assign rule space for general reigster"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF069203C++0x03
|
|
line.long 0x00 "GENERAL_REG_7,This register is used for general purpose"
|
|
hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
|
|
group ad:0xF0693000++0x03
|
|
line.long 0x00 "BOOT_MODE_RS,This register is used for assign rule space for boot mode"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0693004++0x03
|
|
line.long 0x00 "BOOT_MODE,This register is used for record boot mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " BOOT_MODE ,boot mode [3:0]: boot pin [6:4]: ecc for debug"
|
|
group ad:0xF0693100++0x03
|
|
line.long 0x00 "RESET_FLOW_TIME_RS,This register is used for assign rule space for reset flow time"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0693104++0x03
|
|
line.long 0x00 "RESET_FLOW_TIME_CONTROL,This register is used for global reset flow time"
|
|
bitfld.long 0x00 23.--27. " T4 ,T4 time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. " T3 ,T3 time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 10.--17. 1. " T2 ,T2 time"
|
|
bitfld.long 0x00 5.--9. " T1 ,T1 time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. "T0 ,T0 time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0693200++0x03
|
|
line.long 0x00 "RSTGEN_RES_RS,This register is used for assign rule space for rstgen reserve register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0693204++0x03
|
|
line.long 0x00 "RSTGEN_RES,RSTGEN RESERVE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " RES ,reserve register for future use"
|
|
group ad:0xF0693300++0x03
|
|
line.long 0x00 "RSTGEN_MISC_RS,This register is used for assign rule space for rstgen misc register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0693304++0x03
|
|
line.long 0x00 "RSTGEN_MISC,RSTGEN MISC REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MISC ,bit[31:2]: reserved bit[1]: cold reset gating rstgen clk DIsable. bit[0]: enable for permission error as apbslverr"
|
|
group ad:0xF0693400++0x03
|
|
line.long 0x00 "RSTGEN_SUP_DOM,RSTGEN SUPER DOMAIN REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock the entire register" "0,1"
|
|
bitfld.long 0x00 5.--6. " PPROT ,pprot for super doman" "0,1,2,3"
|
|
bitfld.long 0x00 4. " SEC_EN ,check pprot enable" "0,1"
|
|
bitfld.long 0x00 0.--3. " DID ,super domain domain id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0693500++0x03
|
|
line.long 0x00 "RSTGEN_TOUT_RS,This register is used for assign rule space for rstgen timeouit register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0693504++0x03
|
|
line.long 0x00 "RSTGEN_IST_TOUT,RSTGEN IST TIMEOUT REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOUT_VAL ,timeout value"
|
|
group ad:0xF0693508++0x03
|
|
line.long 0x00 "RSTGEN_BTI_TOUT,RSTGEN BTI TIMEOUT REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOUT_VAL ,timeout value"
|
|
group ad:0xF0694000++0x03
|
|
line.long 0x00 "RSTGEN_FUSA_RS,This register is used for assign rule space for rstgen fusa register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0694004++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 23. " PADDR_INT_CLR ,paddr uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 22. " PUSER_INT_CLR ,puser uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 21. " PCTRL1_INT_CLR ,pctrl1 uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 20. " PCTRL0_INT_CLR ,pctrl0 uncorrectable error interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "PWDAT_C_INT_CLR ,pwdata correctable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " PWDAT_U_INT_CLR ,pwdata uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " PWDAT_F_INT_CLR ,pwdata fatal error interrupt clear" "0,1"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. "PUSER_INT_STA ,puser uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 11. " PWDAT_C_INT_STA ,pwdata correctable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status." "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. " PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF0694008++0x03
|
|
line.long 0x00 "APB_LKSTEP_INT,APB LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 19. " SYNC_ERR_INT_CLR ,sync error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " RESP_ERR_INT_CLR ,response parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " REQ_ERR_INT_CLR ,request parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 16. " CMP_ERR_INT_CLR ,lockstep compare interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "SYNC_ERR_INT_STA ,sync error status" "0,1"
|
|
bitfld.long 0x00 10. " RESP_ERR_INT_STA ,response parity error status" "0,1"
|
|
bitfld.long 0x00 9. " REQ_ERR_INT_STA ,request parity error status" "0,1"
|
|
bitfld.long 0x00 8. " CMP_ERR_INT_STA ,lockstep compare error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SYNC_ERR_INT_EN ,apb sync error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " RESP_ERR_INT_EN ,apb response parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " REQ_ERR_INT_EN ,apb request parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_ERR_INT_EN ,lockstep compare interrupt enable" "0,1"
|
|
group ad:0xF069400C++0x03
|
|
line.long 0x00 "RSTGEN_FUSA_INT,RSTGEN INTERNAL FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 21. " BTI_TOUT_ERR_CLR ,bti timeout error clear" "0,1"
|
|
bitfld.long 0x00 20. " LKSTEP_CMP_ERR_CLR ,rstgen core lockstep compare error clear" "0,1"
|
|
bitfld.long 0x00 19. " SYNC_ERR_CLR ,internal sync check error clear" "0,1"
|
|
bitfld.long 0x00 18. " BOOT_MODE_CHK_ERR_CLR ,boot mode ded check error clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "SWM_TRANS_ERR_CLR ,swm transfer error clear" "0,1"
|
|
bitfld.long 0x00 16. " SWM_CHK_ERR_CLR ,swm one hot check error clear" "0,1"
|
|
bitfld.long 0x00 13. " BTI_TOUT_ERR_STA ,bti timeout error status" "0,1"
|
|
bitfld.long 0x00 12. " LKSTEP_CMP_ERR_STA ,rstgen core lockstep compare error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "SYNC_ERR_STA ,internal sync check error status" "0,1"
|
|
bitfld.long 0x00 10. " BOOT_MODE_CHK_ERR_STA ,boot mode ded check error status" "0,1"
|
|
bitfld.long 0x00 9. " SWM_TRANS_ERR_STA ,swm transfer error status" "0,1"
|
|
bitfld.long 0x00 8. " SWM_CHK_ERR_STA ,swm one hot check error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "BTI_TOUT_ERR_EN ,bti timeout error enable" "0,1"
|
|
bitfld.long 0x00 4. " LKSTEP_CMP_ERR_EN ,rstgen core lockstep compare error enable" "0,1"
|
|
bitfld.long 0x00 3. " SYNC_ERR_EN ,internal sync check error enable" "0,1"
|
|
bitfld.long 0x00 2. " BOOT_MODE_CHK_ERR_EN ,boot mode ded check error enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SWM_TRANS_ERR_EN ,swm transfer error enable" "0,1"
|
|
bitfld.long 0x00 0. " SWM_CHK_ERR_EN ,swm one hot check error enable" "0,1"
|
|
group ad:0xF0694010++0x03
|
|
line.long 0x00 "WDT_LKSTEP_INT,WDT LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 18. " IST_TOUT_ERR_INT_CLR ,ist timeout error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " SYNC_ERR_INT_CLR ,sync error interrupt clear" "0,1"
|
|
bitfld.long 0x00 16. " CMP_ERR_INT_CLR ,lockstep compare interrupt clear" "0,1"
|
|
bitfld.long 0x00 10. " IST_TOUT_ERR_INT_STA ,ist timeout error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "SYNC_ERR_INT_STA ,sync error status" "0,1"
|
|
bitfld.long 0x00 8. " CMP_ERR_INT_STA ,lockstep compare error status" "0,1"
|
|
bitfld.long 0x00 2. " IST_TOUT_ERR_INT_EN ,ist timeout error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " SYNC_ERR_INT_EN ,apb sync error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CMP_ERR_INT_EN ,lockstep compare interrupt enable" "0,1"
|
|
group ad:0xF0694100++0x03
|
|
line.long 0x00 "RSTGEN_INJ_EN,RSTGEN ERROR INJECTION ENABLE"
|
|
hexmask.long.word 0x00 0.--15. 1. " INJ_EN ,error injection enable bit[0]: irq error injection enable. bit[1]: rstgen lkstep error injection enable. bit[2]: aapb lkstep error injection enable bit[3]: aapb req error injection enable bit[4]: aapb output error injection .."
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|
group ad:0xF0694104++0x03
|
|
line.long 0x00 "RSTGEN_INJ_BIT,RSTGEN ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 29.--31. " IRQ_INJ ,irq inj: bit0: inj for unc_irq bit1: inj for cor_irq bit2: inj for rstgen_irq" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ERR_INJ_BIT ,error injection bit bit[3:0]: aapb resp/ded error injection bit. bit[17:8]: rstgen lkstep error injection bit. bit[25:18]: rstgen dout error injection bit. bit[28:26]: ist timeout value error injection bit."
|
|
group ad:0xF0694108++0x03
|
|
line.long 0x00 "RSTGEN_INJ_BIT_1,RSTGEN ERROR INJECTION REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " ERR_INJ_BIT ,error injection bit bit[7:0]: aapb lkstep injection bit. bit[11:8]: aapb req/ded error injection bit. bit[15:12]: aapb output error injection bit."
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|
group ad:0xF069410C++0x03
|
|
line.long 0x00 "RSTGEN_INJ_BIT_2,RSTGEN ERROR INJECTION REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " ERR_INJ_BIT ,error injection bit bit[1:0]: wdt output error injection bit[2]: reserved bit[5:3]: wdt lkstep cmp error injection bit[15:6]: reserved"
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|
group ad:0xF0694200++0x03
|
|
line.long 0x00 "RSTGEN_FUNC_INT_RS,This register is used for assign rule space for rstgen function interrupt register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0694204++0x03
|
|
line.long 0x00 "RSTGEN_FUNC_INT,RSTGEN FUNC INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " ACCESS_PER_ERR_CLR ,access permission check error clear" "0,1"
|
|
bitfld.long 0x00 8. " ACCESS_PER_ERR_STA ,access permission check error status" "0,1"
|
|
bitfld.long 0x00 0. " ACCESS_PER_ERR_EN ,access permission check error enable" "0,1"
|
|
tree.end
|
|
tree "RSTGEN_AP"
|
|
width 27.
|
|
group ad:0xF30D0000++0x03
|
|
line.long 0x00 "DOM_PER0_0,This register is used to control domain0~3 secure and priviledge access permission."
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|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
group ad:0xF30D0004++0x03
|
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line.long 0x00 "DOM_PER1_0,This register is used for to control domain4~7 secure and priviledge access permission."
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bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
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bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0008++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_0,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30D000C++0x03
|
|
line.long 0x00 "DOM_PER0_1,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0010++0x03
|
|
line.long 0x00 "DOM_PER1_1,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0014++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_1,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30D0018++0x03
|
|
line.long 0x00 "DOM_PER0_2,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D001C++0x03
|
|
line.long 0x00 "DOM_PER1_2,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0020++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_2,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30D0024++0x03
|
|
line.long 0x00 "DOM_PER0_3,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0028++0x03
|
|
line.long 0x00 "DOM_PER1_3,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D002C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_3,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30D0030++0x03
|
|
line.long 0x00 "DOM_PER0_4,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0034++0x03
|
|
line.long 0x00 "DOM_PER1_4,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0038++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_4,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30D003C++0x03
|
|
line.long 0x00 "DOM_PER0_5,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0040++0x03
|
|
line.long 0x00 "DOM_PER1_5,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0044++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_5,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30D0048++0x03
|
|
line.long 0x00 "DOM_PER0_6,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D004C++0x03
|
|
line.long 0x00 "DOM_PER1_6,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0050++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_6,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30D0054++0x03
|
|
line.long 0x00 "DOM_PER0_7,This register is used to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D0058++0x03
|
|
line.long 0x00 "DOM_PER1_7,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF30D005C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_7,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF30D0200++0x03
|
|
line.long 0x00 "GLOBAL_RESET_RS,This register is used for assign rule space for global reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D0204++0x03
|
|
line.long 0x00 "GLOBAL_RESET_CONTROL,This register is used for global reset control"
|
|
bitfld.long 0x00 31. " SS_RDY ,ss ready inDIcation for saf: ap_sys ready inDIcation for ap: DIsp_ss/ap_ss ready inDIcation" "0,1"
|
|
bitfld.long 0x00 29. " TEST_IST_EN ,test state ist done fail or timeout trigger cold_rst_req enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 28. " SW_GLB_RST ,software global reset." "0,1"
|
|
bitfld.long 0x00 27. " SW_GLB_RST_EN ,software global reset enable 0: DIsable 1: enable" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 19.--26. 1. "RST_REQ_EN ,reset request cause global reset enable 0: DIsable 1: enable"
|
|
hexmask.long.byte 0x00 11.--18. 1. " WDT2_EN ,WDT2 cause global reset enable 0: DIsable 1: enable bit[7:6]: reserved bit[5]: wdt6_int_rst_req bit[4]: wdt6_int_rst_req bit[3]: wdt4_int_rst_req bit[2]: wdt4_int_rst_req bit[1]: wdt2_int_rst_req bit[0]: reserved.."
|
|
hexmask.long.byte 0x00 3.--10. 1. " WDT1_EN ,WDT1 cause global reset enable 0: DIsable 1: enable bit[7:6]: reserved bit[5]: wdt5_int_rst_req bit[4]: wdt5_int_rst_req bit[3]: wdt3_int_rst_req bit[2]: wdt3_int_rst_req bit[1]: wdt1_int_rst_req bit[0]: reserved.."
|
|
bitfld.long 0x00 2. " SEC_VIO_EN ,security violation cause global reset enable 0: DIsable 1: enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SEM_EN ,sem cause global reset enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " SYS_PANIC_EN ,system panic cause global reset enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF30D0208++0x03
|
|
line.long 0x00 "GLOBAL_RESET_STA,GLOBAL RESET STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GLB_STA_LAST ,global reset status for the last time. If multiple reset source comes nearly the same time, only the first one will be recorded. For rstgen_sf: bit[31:25]: reserved bit[24]: wdt6_int_rst_req. bit[23]: wdt6_int_rst_req. bit[22]: .."
|
|
group ad:0xF30D020C++0x03
|
|
line.long 0x00 "GLOBAL_RESET_STA_ALL,GLOBAL RESET STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " GLB_STA_ALL ,global reset status for all the time. If multiple reset source comes nearly the same time, only the first one will be recorded. For rstgen_sf: bit[31:25]: reserved bit[24]: wdt6_int_rst_req. bit[23]: wdt6_int_rst_req. bit[22]: .."
|
|
group ad:0xF30D0210++0x03
|
|
line.long 0x00 "GLOBAL_ERR_STA_ALL,GLOBAL ERROR STATUS REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_STA_ALL ,rstgen record error status input for all the time no matter it triggers global reset or not For rstgen_sf: bit[31:25]: reserved bit[24]: wdt6_int_rst_req. bit[23]: wdt6_int_rst_req. bit[22]: wdt4_int_rst_req. bit[21]: .."
|
|
group ad:0xF30D1000++0x03
|
|
line.long 0x00 "IST_RESET_RS,This register is used for assign rule space for ist reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1004++0x03
|
|
line.long 0x00 "IST_RESET_CONTROL,This register is used for ist reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 6. " AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1100++0x03
|
|
line.long 0x00 "MISSION_RESET_RS_0,This register is used for assign rule space for mission reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1104++0x03
|
|
line.long 0x00 "MISSION_RESET_CONTROL_0,This register is used for mission reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 28. " LOCK ,lock bit, set to 1 to lock run_mode/slp_mode/hib_mode/auto_clr_rst_b and lock itself." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1200++0x03
|
|
line.long 0x00 "LATENT_RESET_RS_0,This register is used for assign rule space for latent reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1204++0x03
|
|
line.long 0x00 "LATENT_RESET_CONTROL_0,This register is used for latent reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 28. " LOCK ,lock bit, set to 1 to lock run_mode/slp_mode/hib_mode/auto_clr_rst_b and lock itself." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1300++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_0,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1304++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_0,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1308++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_1,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D130C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_1,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1310++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_2,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1314++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_2,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1318++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_3,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D131C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_3,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1320++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_4,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1324++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_4,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1328++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_5,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D132C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_5,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1330++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_6,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1334++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_6,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1338++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_7,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D133C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_7,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1340++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_8,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1344++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_8,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1348++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_9,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D134C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_9,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1350++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_10,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1354++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_10,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1358++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_11,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D135C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_11,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1360++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_12,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1364++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_12,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1368++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_13,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D136C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_13,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1370++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_14,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1374++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_14,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1378++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_15,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D137C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_15,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1380++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_16,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1384++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_16,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1388++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_17,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D138C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_17,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1390++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_18,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1394++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_18,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1398++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_19,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D139C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_19,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13A0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_20,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13A4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_20,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13A8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_21,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13AC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_21,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13B0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_22,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13B4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_22,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13B8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_23,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13BC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_23,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13C0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_24,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13C4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_24,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13C8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_25,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13CC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_25,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13D0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_26,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13D4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_26,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13D8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_27,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13DC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_27,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13E0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_28,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13E4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_28,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13E8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_29,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13EC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_29,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13F0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_30,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13F4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_30,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D13F8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_31,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D13FC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_31,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1400++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_32,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1404++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_32,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1408++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_33,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D140C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_33,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1410++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_34,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1414++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_34,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1418++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_35,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D141C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_35,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1420++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_36,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1424++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_36,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1428++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_37,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D142C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_37,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1430++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_38,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1434++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_38,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1438++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_39,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D143C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_39,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1440++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_40,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1444++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_40,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1448++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_41,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D144C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_41,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1450++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_42,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1454++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_42,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1458++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_43,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D145C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_43,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1460++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_44,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1464++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_44,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1468++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_45,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D146C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_45,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1470++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_46,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1474++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_46,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1478++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_47,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D147C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_47,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1480++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_48,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1484++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_48,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1488++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_49,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D148C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_49,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1490++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_50,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D1494++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_50,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D1498++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_51,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D149C++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_51,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14A0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_52,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14A4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_52,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14A8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_53,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14AC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_53,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14B0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_54,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14B4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_54,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14B8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_55,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14BC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_55,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14C0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_56,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14C4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_56,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14C8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_57,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14CC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_57,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14D0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_58,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14D4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_58,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14D8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_59,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14DC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_59,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14E0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_60,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14E4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_60,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14E8++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_61,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14EC++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_61,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
|
|
bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
|
|
bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
|
|
group ad:0xF30D14F0++0x03
|
|
line.long 0x00 "MODULE_RESET_RS_62,This register is used for assign rule space for module reset control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D14F4++0x03
|
|
line.long 0x00 "MODULE_RESET_CONTROL_62,This register is used for module reset control"
|
|
bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
|
|
bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
|
|
bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
|
|
bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
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bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
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group ad:0xF30D14F8++0x03
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line.long 0x00 "MODULE_RESET_RS_63,This register is used for assign rule space for module reset control"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D14FC++0x03
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line.long 0x00 "MODULE_RESET_CONTROL_63,This register is used for module reset control"
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bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
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bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
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bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
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bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
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bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
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group ad:0xF30D1A00++0x03
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line.long 0x00 "CORE_RESET_RS_0,This register is used for assign rule space for core reset control"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D1A04++0x03
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line.long 0x00 "CORE_RESET_CONTROL_0,This register is used for core reset control"
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bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
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bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
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bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
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bitfld.long 0x00 8.--11. " BTI_TOUT_VAL ,bti handshake timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
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bitfld.long 0x00 5. " RST_REQ_EN ,reset request enable 0: DIsable 1: enable" "0,1"
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bitfld.long 0x00 4. " WDT2_RST_EN ,wdt2 reset enable 0: DIsable 1: enable wdt1 reset or wdt2 reset will trigger core reset happen" "0,1"
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bitfld.long 0x00 3. " WDT1_RST_EN ,wdt1 reset enable 0: DIsable 1: enable" "0,1"
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textline " "
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bitfld.long 0x00 2. "SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
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group ad:0xF30D1B00++0x03
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line.long 0x00 "DBG_RESET_RS,This register is used for assign rule space for dbg reset control"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D1B04++0x03
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line.long 0x00 "DBG_RESET_CONTROL,This register is used for dbg reset control"
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bitfld.long 0x00 31. " RMON_O ,reset monitor at output point" "0,1"
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bitfld.long 0x00 30. " RMON_I ,reset monitor at internal trigger point" "0,1"
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bitfld.long 0x00 29. " RSTA ,real time reset status" "0,1"
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bitfld.long 0x00 8. " DBG_REQ_EN ,dbg request enable" "0,1"
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textline " "
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bitfld.long 0x00 6. "AUTO_CLR_RST_B ,write 1 to generate a auto clear reset." "0,1"
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bitfld.long 0x00 2. " SLP_MODE ,sleep mode setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 1. " HIB_MODE ,hibernate mode setting. 0: off 1: on" "0,1"
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bitfld.long 0x00 0. " RUN_MODE ,run mode setting. 0: off 1: on" "0,1"
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group ad:0xF30D1C00++0x03
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line.long 0x00 "SW_RESET_PASSWORD_CONTROL,SW RESET PASSWORD CONTROL REGISTER"
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bitfld.long 0x00 31. " LOCK ,lock for this registere" "0,1"
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bitfld.long 0x00 0. " EN ,sw reset password enable 0: no need password 1: password needed" "0,1"
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group ad:0xF30D1C04++0x03
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line.long 0x00 "SW_RESET_PASSWORD,This register is used for protecting un-expected sw reset"
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hexmask.long 0x00 0.--31. 1. " PW ,sw reset password"
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group ad:0xF30D2000++0x03
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line.long 0x00 "GENERAL_REG_RS_0,This register is used for assign rule space for general reigster"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D2004++0x03
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line.long 0x00 "GENERAL_REG_0,This register is used for general purpose"
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hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
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group ad:0xF30D2008++0x03
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line.long 0x00 "GENERAL_REG_RS_1,This register is used for assign rule space for general reigster"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D200C++0x03
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line.long 0x00 "GENERAL_REG_1,This register is used for general purpose"
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hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
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group ad:0xF30D2010++0x03
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line.long 0x00 "GENERAL_REG_RS_2,This register is used for assign rule space for general reigster"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D2014++0x03
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line.long 0x00 "GENERAL_REG_2,This register is used for general purpose"
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hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
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group ad:0xF30D2018++0x03
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line.long 0x00 "GENERAL_REG_RS_3,This register is used for assign rule space for general reigster"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D201C++0x03
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line.long 0x00 "GENERAL_REG_3,This register is used for general purpose"
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hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
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group ad:0xF30D2020++0x03
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line.long 0x00 "GENERAL_REG_RS_4,This register is used for assign rule space for general reigster"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D2024++0x03
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line.long 0x00 "GENERAL_REG_4,This register is used for general purpose"
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hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
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group ad:0xF30D2028++0x03
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line.long 0x00 "GENERAL_REG_RS_5,This register is used for assign rule space for general reigster"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D202C++0x03
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line.long 0x00 "GENERAL_REG_5,This register is used for general purpose"
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hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
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group ad:0xF30D2030++0x03
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line.long 0x00 "GENERAL_REG_RS_6,This register is used for assign rule space for general reigster"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D2034++0x03
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line.long 0x00 "GENERAL_REG_6,This register is used for general purpose"
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hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
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group ad:0xF30D2038++0x03
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line.long 0x00 "GENERAL_REG_RS_7,This register is used for assign rule space for general reigster"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D203C++0x03
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line.long 0x00 "GENERAL_REG_7,This register is used for general purpose"
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hexmask.long 0x00 0.--31. 1. " GENERAL ,general register"
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group ad:0xF30D3000++0x03
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line.long 0x00 "BOOT_MODE_RS,This register is used for assign rule space for boot mode"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D3004++0x03
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line.long 0x00 "BOOT_MODE,This register is used for record boot mode"
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hexmask.long.byte 0x00 0.--6. 1. " BOOT_MODE ,boot mode [3:0]: boot pin [6:4]: ecc for debug"
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group ad:0xF30D3100++0x03
|
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line.long 0x00 "RESET_FLOW_TIME_RS,This register is used for assign rule space for reset flow time"
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
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group ad:0xF30D3104++0x03
|
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line.long 0x00 "RESET_FLOW_TIME_CONTROL,This register is used for global reset flow time"
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bitfld.long 0x00 23.--27. " T4 ,T4 time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 18.--22. " T3 ,T3 time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 10.--17. 1. " T2 ,T2 time"
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bitfld.long 0x00 5.--9. " T1 ,T1 time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
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bitfld.long 0x00 0.--4. "T0 ,T0 time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group ad:0xF30D3200++0x03
|
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line.long 0x00 "RSTGEN_RES_RS,This register is used for assign rule space for rstgen reserve register"
|
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D3204++0x03
|
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line.long 0x00 "RSTGEN_RES,RSTGEN RESERVE REGISTER"
|
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hexmask.long 0x00 0.--31. 1. " RES ,reserve register for future use"
|
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group ad:0xF30D3300++0x03
|
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line.long 0x00 "RSTGEN_MISC_RS,This register is used for assign rule space for rstgen misc register"
|
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bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D3304++0x03
|
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line.long 0x00 "RSTGEN_MISC,RSTGEN MISC REGISTER"
|
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hexmask.long 0x00 0.--31. 1. " MISC ,bit[31:2]: reserved bit[1]: cold reset gating rstgen clk DIsable. bit[0]: enable for permission error as apbslverr"
|
|
group ad:0xF30D3400++0x03
|
|
line.long 0x00 "RSTGEN_SUP_DOM,RSTGEN SUPER DOMAIN REGISTER"
|
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bitfld.long 0x00 31. " LOCK ,lock the entire register" "0,1"
|
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bitfld.long 0x00 5.--6. " PPROT ,pprot for super doman" "0,1,2,3"
|
|
bitfld.long 0x00 4. " SEC_EN ,check pprot enable" "0,1"
|
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bitfld.long 0x00 0.--3. " DID ,super domain domain id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF30D3500++0x03
|
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line.long 0x00 "RSTGEN_TOUT_RS,This register is used for assign rule space for rstgen timeouit register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
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bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D3504++0x03
|
|
line.long 0x00 "RSTGEN_IST_TOUT,RSTGEN IST TIMEOUT REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOUT_VAL ,timeout value"
|
|
group ad:0xF30D3508++0x03
|
|
line.long 0x00 "RSTGEN_BTI_TOUT,RSTGEN BTI TIMEOUT REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOUT_VAL ,timeout value"
|
|
group ad:0xF30D4000++0x03
|
|
line.long 0x00 "RSTGEN_FUSA_RS,This register is used for assign rule space for rstgen fusa register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D4004++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 23. " PADDR_INT_CLR ,paddr uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 22. " PUSER_INT_CLR ,puser uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 21. " PCTRL1_INT_CLR ,pctrl1 uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 20. " PCTRL0_INT_CLR ,pctrl0 uncorrectable error interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "PWDAT_C_INT_CLR ,pwdata correctable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " PWDAT_U_INT_CLR ,pwdata uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " PWDAT_F_INT_CLR ,pwdata fatal error interrupt clear" "0,1"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. "PUSER_INT_STA ,puser uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 11. " PWDAT_C_INT_STA ,pwdata correctable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status." "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. " PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF30D4008++0x03
|
|
line.long 0x00 "APB_LKSTEP_INT,APB LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 19. " SYNC_ERR_INT_CLR ,sync error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " RESP_ERR_INT_CLR ,response parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " REQ_ERR_INT_CLR ,request parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 16. " CMP_ERR_INT_CLR ,lockstep compare interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "SYNC_ERR_INT_STA ,sync error status" "0,1"
|
|
bitfld.long 0x00 10. " RESP_ERR_INT_STA ,response parity error status" "0,1"
|
|
bitfld.long 0x00 9. " REQ_ERR_INT_STA ,request parity error status" "0,1"
|
|
bitfld.long 0x00 8. " CMP_ERR_INT_STA ,lockstep compare error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SYNC_ERR_INT_EN ,apb sync error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " RESP_ERR_INT_EN ,apb response parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " REQ_ERR_INT_EN ,apb request parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_ERR_INT_EN ,lockstep compare interrupt enable" "0,1"
|
|
group ad:0xF30D400C++0x03
|
|
line.long 0x00 "RSTGEN_FUSA_INT,RSTGEN INTERNAL FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 21. " BTI_TOUT_ERR_CLR ,bti timeout error clear" "0,1"
|
|
bitfld.long 0x00 20. " LKSTEP_CMP_ERR_CLR ,rstgen core lockstep compare error clear" "0,1"
|
|
bitfld.long 0x00 19. " SYNC_ERR_CLR ,internal sync check error clear" "0,1"
|
|
bitfld.long 0x00 18. " BOOT_MODE_CHK_ERR_CLR ,boot mode ded check error clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "SWM_TRANS_ERR_CLR ,swm transfer error clear" "0,1"
|
|
bitfld.long 0x00 16. " SWM_CHK_ERR_CLR ,swm one hot check error clear" "0,1"
|
|
bitfld.long 0x00 13. " BTI_TOUT_ERR_STA ,bti timeout error status" "0,1"
|
|
bitfld.long 0x00 12. " LKSTEP_CMP_ERR_STA ,rstgen core lockstep compare error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "SYNC_ERR_STA ,internal sync check error status" "0,1"
|
|
bitfld.long 0x00 10. " BOOT_MODE_CHK_ERR_STA ,boot mode ded check error status" "0,1"
|
|
bitfld.long 0x00 9. " SWM_TRANS_ERR_STA ,swm transfer error status" "0,1"
|
|
bitfld.long 0x00 8. " SWM_CHK_ERR_STA ,swm one hot check error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "BTI_TOUT_ERR_EN ,bti timeout error enable" "0,1"
|
|
bitfld.long 0x00 4. " LKSTEP_CMP_ERR_EN ,rstgen core lockstep compare error enable" "0,1"
|
|
bitfld.long 0x00 3. " SYNC_ERR_EN ,internal sync check error enable" "0,1"
|
|
bitfld.long 0x00 2. " BOOT_MODE_CHK_ERR_EN ,boot mode ded check error enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "SWM_TRANS_ERR_EN ,swm transfer error enable" "0,1"
|
|
bitfld.long 0x00 0. " SWM_CHK_ERR_EN ,swm one hot check error enable" "0,1"
|
|
group ad:0xF30D4010++0x03
|
|
line.long 0x00 "WDT_LKSTEP_INT,WDT LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 18. " IST_TOUT_ERR_INT_CLR ,ist timeout error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " SYNC_ERR_INT_CLR ,sync error interrupt clear" "0,1"
|
|
bitfld.long 0x00 16. " CMP_ERR_INT_CLR ,lockstep compare interrupt clear" "0,1"
|
|
bitfld.long 0x00 10. " IST_TOUT_ERR_INT_STA ,ist timeout error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "SYNC_ERR_INT_STA ,sync error status" "0,1"
|
|
bitfld.long 0x00 8. " CMP_ERR_INT_STA ,lockstep compare error status" "0,1"
|
|
bitfld.long 0x00 2. " IST_TOUT_ERR_INT_EN ,ist timeout error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " SYNC_ERR_INT_EN ,apb sync error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "CMP_ERR_INT_EN ,lockstep compare interrupt enable" "0,1"
|
|
group ad:0xF30D4100++0x03
|
|
line.long 0x00 "RSTGEN_INJ_EN,RSTGEN ERROR INJECTION ENABLE"
|
|
hexmask.long.word 0x00 0.--15. 1. " INJ_EN ,error injection enable bit[0]: irq error injection enable. bit[1]: rstgen lkstep error injection enable. bit[2]: aapb lkstep error injection enable bit[3]: aapb req error injection enable bit[4]: aapb output error injection .."
|
|
group ad:0xF30D4104++0x03
|
|
line.long 0x00 "RSTGEN_INJ_BIT,RSTGEN ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 29.--31. " IRQ_INJ ,irq inj: bit0: inj for unc_irq bit1: inj for cor_irq bit2: inj for rstgen_irq" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ERR_INJ_BIT ,error injection bit bit[3:0]: aapb resp/ded error injection bit. bit[17:8]: rstgen lkstep error injection bit. bit[25:18]: rstgen dout error injection bit. bit[28:26]: ist timeout value error injection bit."
|
|
group ad:0xF30D4108++0x03
|
|
line.long 0x00 "RSTGEN_INJ_BIT_1,RSTGEN ERROR INJECTION REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " ERR_INJ_BIT ,error injection bit bit[7:0]: aapb lkstep injection bit. bit[11:8]: aapb req/ded error injection bit. bit[15:12]: aapb output error injection bit."
|
|
group ad:0xF30D410C++0x03
|
|
line.long 0x00 "RSTGEN_INJ_BIT_2,RSTGEN ERROR INJECTION REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " ERR_INJ_BIT ,error injection bit bit[1:0]: wdt output error injection bit[2]: reserved bit[5:3]: wdt lkstep cmp error injection bit[15:6]: reserved"
|
|
group ad:0xF30D4200++0x03
|
|
line.long 0x00 "RSTGEN_FUNC_INT_RS,This register is used for assign rule space for rstgen function interrupt register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF30D4204++0x03
|
|
line.long 0x00 "RSTGEN_FUNC_INT,RSTGEN FUNC INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " ACCESS_PER_ERR_CLR ,access permission check error clear" "0,1"
|
|
bitfld.long 0x00 8. " ACCESS_PER_ERR_STA ,access permission check error status" "0,1"
|
|
bitfld.long 0x00 0. " ACCESS_PER_ERR_EN ,access permission check error enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "SMC"
|
|
width 19.
|
|
group ad:0xF0640000++0x03
|
|
line.long 0x00 "DOM_PER0_0,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640004++0x03
|
|
line.long 0x00 "DOM_PER1_0,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640008++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_0,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF064000C++0x03
|
|
line.long 0x00 "DOM_PER0_1,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640010++0x03
|
|
line.long 0x00 "DOM_PER1_1,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640014++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_1,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0640018++0x03
|
|
line.long 0x00 "DOM_PER0_2,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
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|
group ad:0xF064001C++0x03
|
|
line.long 0x00 "DOM_PER1_2,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640020++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_2,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0640024++0x03
|
|
line.long 0x00 "DOM_PER0_3,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640028++0x03
|
|
line.long 0x00 "DOM_PER1_3,This register is used for to control domain4~7 secure and priviledge access permission."
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|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF064002C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_3,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0640030++0x03
|
|
line.long 0x00 "DOM_PER0_4,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640034++0x03
|
|
line.long 0x00 "DOM_PER1_4,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640038++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_4,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF064003C++0x03
|
|
line.long 0x00 "DOM_PER0_5,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640040++0x03
|
|
line.long 0x00 "DOM_PER1_5,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640044++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_5,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0640048++0x03
|
|
line.long 0x00 "DOM_PER0_6,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF064004C++0x03
|
|
line.long 0x00 "DOM_PER1_6,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640050++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_6,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0640054++0x03
|
|
line.long 0x00 "DOM_PER0_7,This register is used for to control domain0~3 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM3_USE_PER ,Domain3 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM3_PRI_PER ,Domain3 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM3_NSE_PER ,Domain3 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM3_SEC_PER ,Domain3 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM2_USE_PER ,Domain2 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM2_PRI_PER ,Domain2 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM2_NSE_PER ,Domain2 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM2_SEC_PER ,Domain2 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM1_USE_PER ,Domain1 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM1_PRI_PER ,Domain1 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM1_NSE_PER ,Domain1 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM1_SEC_PER ,Domain1 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM0_USE_PER ,Domain0 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM0_PRI_PER ,Domain0 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM0_NSE_PER ,Domain0 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM0_SEC_PER ,Domain0 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF0640058++0x03
|
|
line.long 0x00 "DOM_PER1_7,This register is used for to control domain4~7 secure and priviledge access permission."
|
|
bitfld.long 0x00 30.--31. " DOM7_USE_PER ,Domain7 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " DOM7_PRI_PER ,Domain7 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " DOM7_NSE_PER ,Domain7 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DOM7_SEC_PER ,Domain7 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. "DOM6_USE_PER ,Domain6 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " DOM6_PRI_PER ,Domain6 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " DOM6_NSE_PER ,Domain6 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " DOM6_SEC_PER ,Domain6 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. "DOM5_USE_PER ,Domain5 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " DOM5_PRI_PER ,Domain5 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " DOM5_NSE_PER ,Domain5 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DOM5_SEC_PER ,Domain5 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "DOM4_USE_PER ,Domain4 user access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DOM4_PRI_PER ,Domain4 privileged access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " DOM4_NSE_PER ,Domain4 non-secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DOM4_SEC_PER ,Domain4 secure access permission 2'b11 : NONE 2'b10 : WO 2'b01 : RO 2'b00 : RW" "0,1,2,3"
|
|
group ad:0xF064005C++0x03
|
|
line.long 0x00 "DOM_PER_LOCK_7,This register is used to lock domain access permission setting."
|
|
bitfld.long 0x00 7. " DOM7_LOCK ,lock domain 7 access permission setting." "0,1"
|
|
bitfld.long 0x00 6. " DOM6_LOCK ,lock domain 6 access permission setting." "0,1"
|
|
bitfld.long 0x00 5. " DOM5_LOCK ,lock domain 5 access permission setting." "0,1"
|
|
bitfld.long 0x00 4. " DOM4_LOCK ,lock domain 4 access permission setting." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "DOM3_LOCK ,lock domain 3 access permission setting." "0,1"
|
|
bitfld.long 0x00 2. " DOM2_LOCK ,lock domain 2 access permission setting." "0,1"
|
|
bitfld.long 0x00 1. " DOM1_LOCK ,lock domain 1 access permission setting." "0,1"
|
|
bitfld.long 0x00 0. " DOM0_LOCK ,lock domain 0 access permission setting." "0,1"
|
|
group ad:0xF0640200++0x03
|
|
line.long 0x00 "SAF_DOM_RS,This register is used for assign rule space for safe domain control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign in this RS. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0640204++0x03
|
|
line.long 0x00 "AP_DOM_RS,This register is used for assign rule space for ap domain control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0640208++0x03
|
|
line.long 0x00 "SOC_DOM_RS,This register is used for assign rule space for soc domain control"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641000++0x03
|
|
line.long 0x00 "SAF_GLB_CTL,SAFE DOMAIN GLOBAL CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " WFI_DIS ,wfi DIsable, check swm status before enable this bit 1: wfi DIsable 0: wfi enable" "0,1"
|
|
bitfld.long 0x00 3. " LP_MODE ,safe domain low power mode. 0: slp mode 1: hib mode" "0,1"
|
|
bitfld.long 0x00 0.--2. " PRI_CORE ,safe domain primary core" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0641008++0x03
|
|
line.long 0x00 "SAF_LP_CTL,SAFE DOMAIN LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 4. " SW_PWR_GATE ,software power gate" "0,1"
|
|
bitfld.long 0x00 3. " SW_ISO_EN ,software isolation enable" "0,1"
|
|
bitfld.long 0x00 2. " SW_PD_EN ,software power down enable" "0,1"
|
|
bitfld.long 0x00 1. " HIB_PD_EN ,hib mode power down enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SLP_PD_EN ,slp mode power down enable" "0,1"
|
|
group ad:0xF064100C++0x03
|
|
line.long 0x00 "SAF_LP_DLY_CTL,SAFE DOMAIN LOW POWER DELAY CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 12.--19. 1. " ISO_DIS ,isolation DIsable delay"
|
|
bitfld.long 0x00 8.--11. " PO ,power on delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PG ,power gate delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " ISO_EN ,isolation enable delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0641010++0x03
|
|
line.long 0x00 "SAF_LP_CTL,SAFE DOMAIN LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 4. " SW_PWR_GATE ,software power gate" "0,1"
|
|
bitfld.long 0x00 3. " SW_ISO_EN ,software isolation enable" "0,1"
|
|
bitfld.long 0x00 2. " SW_PD_EN ,software power down enable" "0,1"
|
|
bitfld.long 0x00 1. " HIB_PD_EN ,hib mode power down enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SLP_PD_EN ,slp mode power down enable" "0,1"
|
|
group ad:0xF0641014++0x03
|
|
line.long 0x00 "SAF_LP_DLY_CTL,SAFE DOMAIN LOW POWER DELAY CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 12.--19. 1. " ISO_DIS ,isolation DIsable delay"
|
|
bitfld.long 0x00 8.--11. " PO ,power on delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PG ,power gate delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " ISO_EN ,isolation enable delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0641018++0x03
|
|
line.long 0x00 "SAF_LP_CTL,SAFE DOMAIN LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 4. " SW_PWR_GATE ,software power gate" "0,1"
|
|
bitfld.long 0x00 3. " SW_ISO_EN ,software isolation enable" "0,1"
|
|
bitfld.long 0x00 2. " SW_PD_EN ,software power down enable" "0,1"
|
|
bitfld.long 0x00 1. " HIB_PD_EN ,hib mode power down enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SLP_PD_EN ,slp mode power down enable" "0,1"
|
|
group ad:0xF064101C++0x03
|
|
line.long 0x00 "SAF_LP_DLY_CTL,SAFE DOMAIN LOW POWER DELAY CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 12.--19. 1. " ISO_DIS ,isolation DIsable delay"
|
|
bitfld.long 0x00 8.--11. " PO ,power on delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PG ,power gate delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " ISO_EN ,isolation enable delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0641020++0x03
|
|
line.long 0x00 "SAF_LP_CTL,SAFE DOMAIN LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 4. " SW_PWR_GATE ,software power gate" "0,1"
|
|
bitfld.long 0x00 3. " SW_ISO_EN ,software isolation enable" "0,1"
|
|
bitfld.long 0x00 2. " SW_PD_EN ,software power down enable" "0,1"
|
|
bitfld.long 0x00 1. " HIB_PD_EN ,hib mode power down enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SLP_PD_EN ,slp mode power down enable" "0,1"
|
|
group ad:0xF0641024++0x03
|
|
line.long 0x00 "SAF_LP_DLY_CTL,SAFE DOMAIN LOW POWER DELAY CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 12.--19. 1. " ISO_DIS ,isolation DIsable delay"
|
|
bitfld.long 0x00 8.--11. " PO ,power on delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PG ,power gate delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " ISO_EN ,isolation enable delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0641060++0x03
|
|
line.long 0x00 "SAF_RAM_LP_CTL,SAFE DOMAIN RAM LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 9.--11. " SW_RAM_LP_SETTING ,sw ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " HIB_RAM_LP_SETTING ,hib mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. " SLP_RAM_LP_SETTING ,slp mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SW_RAM_PD_EN ,software ram low power mode enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "HIB_RAM_PD_EN ,hib mode ram power down enable" "0,1"
|
|
bitfld.long 0x00 0. " SLP_RAM_PD_EN ,slp mode ram power down enable" "0,1"
|
|
group ad:0xF0641064++0x03
|
|
line.long 0x00 "SAF_RAM_LP_CTL,SAFE DOMAIN RAM LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 9.--11. " SW_RAM_LP_SETTING ,sw ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " HIB_RAM_LP_SETTING ,hib mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. " SLP_RAM_LP_SETTING ,slp mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SW_RAM_PD_EN ,software ram low power mode enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "HIB_RAM_PD_EN ,hib mode ram power down enable" "0,1"
|
|
bitfld.long 0x00 0. " SLP_RAM_PD_EN ,slp mode ram power down enable" "0,1"
|
|
group ad:0xF0641068++0x03
|
|
line.long 0x00 "SAF_RAM_LP_CTL,SAFE DOMAIN RAM LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 9.--11. " SW_RAM_LP_SETTING ,sw ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " HIB_RAM_LP_SETTING ,hib mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. " SLP_RAM_LP_SETTING ,slp mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SW_RAM_PD_EN ,software ram low power mode enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "HIB_RAM_PD_EN ,hib mode ram power down enable" "0,1"
|
|
bitfld.long 0x00 0. " SLP_RAM_PD_EN ,slp mode ram power down enable" "0,1"
|
|
group ad:0xF064106C++0x03
|
|
line.long 0x00 "SAF_RAM_LP_CTL,SAFE DOMAIN RAM LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 9.--11. " SW_RAM_LP_SETTING ,sw ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " HIB_RAM_LP_SETTING ,hib mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. " SLP_RAM_LP_SETTING ,slp mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SW_RAM_PD_EN ,software ram low power mode enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "HIB_RAM_PD_EN ,hib mode ram power down enable" "0,1"
|
|
bitfld.long 0x00 0. " SLP_RAM_PD_EN ,slp mode ram power down enable" "0,1"
|
|
group ad:0xF0641070++0x03
|
|
line.long 0x00 "SAF_RAM_LP_CTL,SAFE DOMAIN RAM LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 9.--11. " SW_RAM_LP_SETTING ,sw ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " HIB_RAM_LP_SETTING ,hib mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. " SLP_RAM_LP_SETTING ,slp mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SW_RAM_PD_EN ,software ram low power mode enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "HIB_RAM_PD_EN ,hib mode ram power down enable" "0,1"
|
|
bitfld.long 0x00 0. " SLP_RAM_PD_EN ,slp mode ram power down enable" "0,1"
|
|
group ad:0xF0641114++0x03
|
|
line.long 0x00 "SAF_TIMEOUT,SAFE DOMAIN TIMEOUT SETTING REGISTER"
|
|
bitfld.long 0x00 31. " WKUP_EN ,timeout wakeup during lp process enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 30. " WDT_EN ,wdt enable for handshake time monitor. 1: enable 0: DIsable" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CKGEN_HK ,timeout value for ckgen swm handshake"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RSTGEN_HK ,timeout value for rstgen swm handshake"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "MODE_REQ_TRANS ,timeout value for mode trans request"
|
|
group ad:0xF0641118++0x03
|
|
line.long 0x00 "SAF_MISC,SAFE DOMAIN MISC REGISTER"
|
|
bitfld.long 0x00 9. " ILL_TRANS_WKUP_EN ,swm illegal transfer wakeup enable, if illegal swm handshake received during low power process, wakeup will be happen when this bit set to 1. 0: DIsable 1: enable" "0,1"
|
|
hexmask.long.byte 0x00 1.--8. 1. " IRQ_MASK_DLY ,interrupt mask delay, the delay time between wakeup interrupt received to swm mode transition. If wakeup interrupts are detected by SMC before swm mode transition. then the transition is aborted. SMC send interrupt un-mask .."
|
|
bitfld.long 0x00 0. " LP_TRANS_REQ ,lp mode transition request sw can set this bit to 1 to start a wdt counter, if wdt counter timeout before it enter into low power, irq will be generated." "0,1"
|
|
group ad:0xF0641200++0x03
|
|
line.long 0x00 "AP_GLB_CTL,AP DOMAIN GLOBAL CONTROL REGISTER"
|
|
bitfld.long 0x00 8. " WFI_DIS ,wfi DIsable, check swm status before enable this bit 1: wfi DIsable 0: wfi enable" "0,1"
|
|
bitfld.long 0x00 5. " WKUP_ALIGN2SAF ,ap domain wakeup align with saf enable" "0,1"
|
|
bitfld.long 0x00 4. " LP_ALIGN2SAF ,ap domain lp align with saf enable" "0,1"
|
|
bitfld.long 0x00 3. " LP_MODE ,ap domain low power mode. 0: slp mode 1: hib mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. "PRI_CORE ,ap domain primary core" "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0641208++0x03
|
|
line.long 0x00 "AP_LP_CTL,AP DOMAIN LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 4. " SW_PWR_GATE ,software power gate" "0,1"
|
|
bitfld.long 0x00 3. " SW_ISO_EN ,software isolation enable" "0,1"
|
|
bitfld.long 0x00 2. " SW_PD_EN ,software power down enable" "0,1"
|
|
bitfld.long 0x00 1. " HIB_PD_EN ,hib mode power down enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SLP_PD_EN ,slp mode power down enable" "0,1"
|
|
group ad:0xF064120C++0x03
|
|
line.long 0x00 "AP_LP_DLY_CTL,AP DOMAIN LOW POWER DELAY CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 12.--19. 1. " ISO_DIS ,isolation DIsable delay"
|
|
bitfld.long 0x00 8.--11. " PO ,power on delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PG ,power gate delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " ISO_EN ,isolation enable delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0641210++0x03
|
|
line.long 0x00 "AP_LP_CTL,AP DOMAIN LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 4. " SW_PWR_GATE ,software power gate" "0,1"
|
|
bitfld.long 0x00 3. " SW_ISO_EN ,software isolation enable" "0,1"
|
|
bitfld.long 0x00 2. " SW_PD_EN ,software power down enable" "0,1"
|
|
bitfld.long 0x00 1. " HIB_PD_EN ,hib mode power down enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "SLP_PD_EN ,slp mode power down enable" "0,1"
|
|
group ad:0xF0641214++0x03
|
|
line.long 0x00 "AP_LP_DLY_CTL,AP DOMAIN LOW POWER DELAY CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 12.--19. 1. " ISO_DIS ,isolation DIsable delay"
|
|
bitfld.long 0x00 8.--11. " PO ,power on delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PG ,power gate delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " ISO_EN ,isolation enable delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0641260++0x03
|
|
line.long 0x00 "AP_RAM_LP_CTL,AP DOMAIN RAM LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 9.--11. " SW_RAM_LP_SETTING ,sw ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " HIB_RAM_LP_SETTING ,hib mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. " SLP_RAM_LP_SETTING ,slp mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SW_RAM_PD_EN ,software ram low power mode enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "HIB_RAM_PD_EN ,hib mode ram power down enable" "0,1"
|
|
bitfld.long 0x00 0. " SLP_RAM_PD_EN ,slp mode ram power down enable" "0,1"
|
|
group ad:0xF0641264++0x03
|
|
line.long 0x00 "AP_RAM_LP_CTL,AP DOMAIN RAM LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 9.--11. " SW_RAM_LP_SETTING ,sw ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " HIB_RAM_LP_SETTING ,hib mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. " SLP_RAM_LP_SETTING ,slp mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SW_RAM_PD_EN ,software ram low power mode enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "HIB_RAM_PD_EN ,hib mode ram power down enable" "0,1"
|
|
bitfld.long 0x00 0. " SLP_RAM_PD_EN ,slp mode ram power down enable" "0,1"
|
|
group ad:0xF0641268++0x03
|
|
line.long 0x00 "AP_RAM_LP_CTL,AP DOMAIN RAM LOW POWER CONTROL REGISTER"
|
|
bitfld.long 0x00 9.--11. " SW_RAM_LP_SETTING ,sw ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " HIB_RAM_LP_SETTING ,hib mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. " SLP_RAM_LP_SETTING ,slp mode ram low power setting. {PG_EN,RET1N,RET2N}" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SW_RAM_PD_EN ,software ram low power mode enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "HIB_RAM_PD_EN ,hib mode ram power down enable" "0,1"
|
|
bitfld.long 0x00 0. " SLP_RAM_PD_EN ,slp mode ram power down enable" "0,1"
|
|
group ad:0xF0641314++0x03
|
|
line.long 0x00 "AP_TIMEOUT,AP DOMAIN TIMEOUT SETTING REGISTER"
|
|
bitfld.long 0x00 31. " WKUP_EN ,timeout wakeup during lp process enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 30. " WDT_EN ,wdt enable for handshake time monitor. 1: enable 0: DIsable" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CKGEN_HK ,timeout value for ckgen swm handshake"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RSTGEN_HK ,timeout value for rstgen swm handshake"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. "MODE_REQ_TRANS ,timeout value for mode trans request"
|
|
group ad:0xF0641318++0x03
|
|
line.long 0x00 "AP_MISC,AP DOMAIN MISC REGISTER"
|
|
bitfld.long 0x00 9. " ILL_TRANS_WKUP_EN ,swm illegal transfer wakeup enable, if illegal swm handshake received during low power process, wakeup will be happen when this bit set to 1. 0: DIsable 1: enable" "0,1"
|
|
hexmask.long.byte 0x00 1.--8. 1. " IRQ_MASK_DLY ,interrupt mask delay, the delay time between wakeup interrupt received to swm mode transition. If wakeup interrupts are detected by SMC before swm mode transition. then the transition is aborted. SMC send interrupt un-mask .."
|
|
bitfld.long 0x00 0. " LP_TRANS_REQ ,lp mode transition request sw can set this bit to 1 to start a wdt counter, if wdt counter timeout before it enter into low power, irq will be generated." "0,1"
|
|
group ad:0xF0641400++0x03
|
|
line.long 0x00 "SOC_GLB_CTL,SOC GLOBAL CONTROL REGISTER"
|
|
bitfld.long 0x00 0. " AP_OFF ,ap domain power off, smc will only handshake with saf domain." "0,1"
|
|
group ad:0xF0641404++0x03
|
|
line.long 0x00 "SOC_HIB_RC_DIS,SOC HIB MODE RC24M DISABLE REGISTER"
|
|
bitfld.long 0x00 0. " RC_DIS_EN ,hib mode rc24m DIsable enable 0: rc24m not DIsable 1: rc24m DIsable" "0,1"
|
|
group ad:0xF0641408++0x03
|
|
line.long 0x00 "SOC_PRE_DIV,SOC PRE DIVIDER NUMBER REGISTER"
|
|
hexmask.long.word 0x00 8.--17. 1. " DIV_NUM_32K ,pre DIv number for clk32k"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV_NUM_24M ,pre DIv number for clk24m"
|
|
group ad:0xF064140C++0x03
|
|
line.long 0x00 "SOC_SWM_TIMEOUT,SWM TIMEOUT SETTING REGISTER"
|
|
bitfld.long 0x00 31. " WKUP_EN ,timeout wakeup during lp process enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 30. " WDT_EN ,wdt enable for handshake time monitor. 1: enable 0: DIsable" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PMU_HK ,timeout value for pmu swm handshake"
|
|
group ad:0xF0641410++0x03
|
|
line.long 0x00 "SOC_WKUP_CTL,SOC WAKEUP CONTROL REGISTER"
|
|
bitfld.long 0x00 31. " LP2WKUP_TOUT_WKUP_EN ,timeout between lp to timeout wakeup enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 23. " WKUP_WDT_EN ,wakeup wdt enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 18.--22. " SW_WKUP_ACK ,software wakeup acknowledge register bit0: cr5_saf bit1: cr5_sp0 bit2: cr5_sp1 bit3: cr5_sx0 bit4: cr5_sx1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17. " WKUP_DONE_SRC_SEL ,wakeup done event source sel. 0: SOC to RUN state 1: all active cpu acknowledge done" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. "LP2WKUP_WDT_EN ,wdt enable between lp to wakeup event receive. 1: enable 0: DIsable" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " LP2WKUP_VAL ,time between lp to wakeup event receive."
|
|
group ad:0xF0641414++0x03
|
|
line.long 0x00 "SOC_WKUP_TIMEOUT,WAKEUP TIMEOUT SETTING REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " WKUP_ACK ,timeout value for wakeup event receive to all active cpu acknowledge done"
|
|
hexmask.long.word 0x00 0.--15. 1. " SOC_RUN ,timeout value for wakeup event receive to soc goes into RUN state"
|
|
group ad:0xF0641418++0x03
|
|
line.long 0x00 "SMC_WKUP_IRQ,SMC WAKEUP CORE IRQ REGISTER"
|
|
bitfld.long 0x00 24.--28. " WKUP_IRQ_STA ,smc wakeup irq status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " WKUP_CLR ,SMC wakeup core irq clear, auto clear bit0: cr5_saf bit1: cr5_sp0 bit2: cr5_sp1 bit3: cr5_sx0 bit4: cr5_sx1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " ERR_WKUP_EN ,SMC error wakeup core irq enable bit0: cr5_saf bit1: cr5_sp0 bit2: cr5_sp1 bit3: cr5_sx0 bit4: cr5_sx1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " BK_WKUP_EN ,SMC wakeup core irq enable bit0: cr5_saf bit1: cr5_sp0 bit2: cr5_sp1 bit3: cr5_sx0 bit4: cr5_sx1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF064141C++0x03
|
|
line.long 0x00 "SOC_MISC,SOC MISC REGISTER"
|
|
bitfld.long 0x00 9. " ILL_TRANS_WKUP_EN ,swm illegal transfer wakeup enable" "0,1"
|
|
bitfld.long 0x00 0. " FIRST_PMU_HK_OK ,power on reset pmu handshake ok status 1: ok 0: fail" "0,1"
|
|
group ad:0xF0641450++0x03
|
|
line.long 0x00 "SMC_SW_SWM,SMC SOFTWARE TRIGGER SWM REGISTER"
|
|
bitfld.long 0x00 24. " PMU_SWM_OK ,pmu sw swm result 1: handshake ok 0: handshake not ok or not done yet. need to write 0 to clear it" "0,1"
|
|
bitfld.long 0x00 22.--23. " PMU_SWM_O ,pmu sw swm mode 2'b00: run 2'b01: slp 2'b10: hib 2'b11: rtc" "0,1,2,3"
|
|
bitfld.long 0x00 21. " PMU_SWM_TRIGGER ,pmu sw swm trigger. write one to trigger swm handshake. auto clear" "0,1"
|
|
bitfld.long 0x00 20. " PMU_SWM_EN ,pmu sw swm enable 1: enable 0: DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "SAF_RSTGEN_SWM_OK ,saf rstgen sw swm result 1: handshake ok 0: handshake not ok or not done yet. need to write 0 to clear it" "0,1"
|
|
bitfld.long 0x00 17.--18. " SAF_RSTGEN_SWM_O ,saf rstgen sw swm mode 2'b00: run 2'b01: slp 2'b10: hib 2'b11: rtc" "0,1,2,3"
|
|
bitfld.long 0x00 16. " SAF_RSTGEN_SWM_TRIGGER ,saf rstgen sw swm trigger. write one to trigger swm handshake. auto clear" "0,1"
|
|
bitfld.long 0x00 15. " SAF_RSTGEN_SWM_EN ,saf rstgen sw swm enable 1: enable 0: DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. "SAF_CKGEN_SWM_OK ,saf ckgen sw swm result 1: handshake ok 0: handshake not ok or not done yet. need to write 0 to clear it" "0,1"
|
|
bitfld.long 0x00 12.--13. " SAF_CKGEN_SWM_O ,saf ckgen sw swm mode 2'b00: run 2'b01: slp 2'b10: hib 2'b11: rtc" "0,1,2,3"
|
|
bitfld.long 0x00 11. " SAF_CKGEN_SWM_TRIGGER ,saf ckgen sw swm trigger. write one to trigger swm handshake. auto clear" "0,1"
|
|
bitfld.long 0x00 10. " SAF_CKGEN_SWM_EN ,saf ckgen sw swm enable 1: enable 0: DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "AP_RSTGEN_SWM_OK ,ap rstgen sw swm result 1: handshake ok 0: handshake not ok or not done yet. need to write 0 to clear it" "0,1"
|
|
bitfld.long 0x00 7.--8. " AP_RSTGEN_SWM_O ,ap rstgen sw swm mode 2'b00: run 2'b01: slp 2'b10: hib 2'b11: rtc" "0,1,2,3"
|
|
bitfld.long 0x00 6. " AP_RSTGEN_SWM_TRIGGER ,ap rstgen sw swm trigger. write one to trigger swm handshake. auto clear" "0,1"
|
|
bitfld.long 0x00 5. " AP_RSTGEN_SWM_EN ,ap rstgen sw swm enable 1: enable 0: DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "AP_CKGEN_SWM_OK ,ap ckgen sw swm result 1: handshake ok 0: handshake not ok or not done yet. need to write 0 to clear it" "0,1"
|
|
bitfld.long 0x00 2.--3. " AP_CKGEN_SWM_O ,ap ckgen sw swm mode 2'b00: run 2'b01: slp 2'b10: hib 2'b11: rtc" "0,1,2,3"
|
|
bitfld.long 0x00 1. " AP_CKGEN_SWM_TRIGGER ,ap ckgen sw swm trigger. write one to trigger swm handshake. auto clear" "0,1"
|
|
bitfld.long 0x00 0. " AP_CKGEN_SWM_EN ,ap ckgen sw swm enable 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF0641500++0x03
|
|
line.long 0x00 "SOC_CMON_RS,SOC CLOCK MONITOR RULE SPACE REGISTER 1"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641504++0x03
|
|
line.long 0x00 "SOC_CMON,SOC CLOCK MONITOR REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " MON_FREQ ,frequency recorded, can be cleared by software write all 0"
|
|
bitfld.long 0x00 15. " MON_FREQ_UPD ,frequency updated inDIcation, software can polling this bit to know frequency has been recorded yet. And this bit can be cleared by software write it to 0" "0,1"
|
|
bitfld.long 0x00 2. " ACTIVE_LOSS_DIS ,active loss event DIsable 1: DIsable 0: enable" "0,1"
|
|
bitfld.long 0x00 1. " FORCE_MON_EN ,clk32k monitor clk24m force enable. check will active ignore 32k/24m status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "HW_MON_EN ,clk32k monitor clk24m hw enable. check will active when xtal 32k active and 24M active" "0,1"
|
|
group ad:0xF0641508++0x03
|
|
line.long 0x00 "SOC_CMON_RC,SOC CLOCK MONITOR RC CHECK SETTING REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW_THRD ,low threshold"
|
|
group ad:0xF064150C++0x03
|
|
line.long 0x00 "SOC_CMON_XTAL,SOC CLOCK MONITOR XTAL CHECK SETTING REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGH_THRD ,high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOW_THRD ,low threshold"
|
|
group ad:0xF0641600++0x03
|
|
line.long 0x00 "CORE_IRQ_MASK_RS,CORE SPECIFIC IRQ MASK RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641604++0x03
|
|
line.long 0x00 "CORE_IRQ_MASK,CORE SPECIFIC IRQ MASK REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641608++0x03
|
|
line.long 0x00 "CORE_IRQ_MASK_RS,CORE SPECIFIC IRQ MASK RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF064160C++0x03
|
|
line.long 0x00 "CORE_IRQ_MASK,CORE SPECIFIC IRQ MASK REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641610++0x03
|
|
line.long 0x00 "CORE_IRQ_MASK_RS,CORE SPECIFIC IRQ MASK RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641614++0x03
|
|
line.long 0x00 "CORE_IRQ_MASK,CORE SPECIFIC IRQ MASK REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641618++0x03
|
|
line.long 0x00 "CORE_IRQ_MASK_RS,CORE SPECIFIC IRQ MASK RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF064161C++0x03
|
|
line.long 0x00 "CORE_IRQ_MASK,CORE SPECIFIC IRQ MASK REGISTER"
|
|
hexmask.long.word 0x00 0.--15. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641800++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_RS,COMMON IRQ MASK RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641804++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_0,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641808++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_1,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF064180C++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_2,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641810++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_3,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641814++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_4,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641818++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_5,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF064181C++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_6,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641820++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_7,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641824++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_RS,COMMON IRQ MASK RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641828++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_0,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF064182C++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_1,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641830++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_2,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641834++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_3,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641838++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_4,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF064183C++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_5,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641840++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_6,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641844++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_7,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641848++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_RS,COMMON IRQ MASK RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF064184C++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_0,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641850++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_1,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641854++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_2,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641858++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_3,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF064185C++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_4,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641860++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_5,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641864++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_6,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641868++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_7,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF064186C++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_RS,COMMON IRQ MASK RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641870++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_0,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641874++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_1,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641878++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_2,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF064187C++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_3,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641880++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_4,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641884++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_5,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641888++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_6,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF064188C++0x03
|
|
line.long 0x00 "COM_IRQ_MASK_7,COMMON IRQ MASK REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MASK ,irq mask. 0: unmask 1: mask"
|
|
group ad:0xF0641A00++0x03
|
|
line.long 0x00 "IRQ_MON_RS,IRQ MONITOR REGISTER RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641A04++0x03
|
|
line.long 0x00 "CORE_IRQ_MON,CORE SPECIFIC IRQ MONITOR REGISER"
|
|
bitfld.long 0x00 15. " IRQ_STA_15 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,core irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641A08++0x03
|
|
line.long 0x00 "CORE_IRQ_MON,CORE SPECIFIC IRQ MONITOR REGISER"
|
|
bitfld.long 0x00 15. " IRQ_STA_15 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,core irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641A0C++0x03
|
|
line.long 0x00 "CORE_IRQ_MON,CORE SPECIFIC IRQ MONITOR REGISER"
|
|
bitfld.long 0x00 15. " IRQ_STA_15 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,core irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641A10++0x03
|
|
line.long 0x00 "CORE_IRQ_MON,CORE SPECIFIC IRQ MONITOR REGISER"
|
|
bitfld.long 0x00 15. " IRQ_STA_15 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,core irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,core irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,core irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641B00++0x03
|
|
line.long 0x00 "COM_IRQ_MON_0,COMMON IRQ MONITOR REGISTER"
|
|
bitfld.long 0x00 31. " IRQ_STA_31 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 30. " IRQ_STA_30 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 29. " IRQ_STA_29 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 28. " IRQ_STA_28 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "IRQ_STA_27 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 26. " IRQ_STA_26 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 25. " IRQ_STA_25 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 24. " IRQ_STA_24 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "IRQ_STA_23 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 22. " IRQ_STA_22 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 21. " IRQ_STA_21 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 20. " IRQ_STA_20 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "IRQ_STA_19 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 18. " IRQ_STA_18 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 17. " IRQ_STA_17 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 16. " IRQ_STA_16 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "IRQ_STA_15 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,common irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641B04++0x03
|
|
line.long 0x00 "COM_IRQ_MON_1,COMMON IRQ MONITOR REGISTER"
|
|
bitfld.long 0x00 31. " IRQ_STA_31 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 30. " IRQ_STA_30 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 29. " IRQ_STA_29 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 28. " IRQ_STA_28 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "IRQ_STA_27 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 26. " IRQ_STA_26 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 25. " IRQ_STA_25 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 24. " IRQ_STA_24 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "IRQ_STA_23 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 22. " IRQ_STA_22 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 21. " IRQ_STA_21 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 20. " IRQ_STA_20 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "IRQ_STA_19 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 18. " IRQ_STA_18 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 17. " IRQ_STA_17 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 16. " IRQ_STA_16 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "IRQ_STA_15 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,common irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641B08++0x03
|
|
line.long 0x00 "COM_IRQ_MON_2,COMMON IRQ MONITOR REGISTER"
|
|
bitfld.long 0x00 31. " IRQ_STA_31 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 30. " IRQ_STA_30 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 29. " IRQ_STA_29 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 28. " IRQ_STA_28 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "IRQ_STA_27 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 26. " IRQ_STA_26 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 25. " IRQ_STA_25 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 24. " IRQ_STA_24 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "IRQ_STA_23 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 22. " IRQ_STA_22 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 21. " IRQ_STA_21 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 20. " IRQ_STA_20 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "IRQ_STA_19 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 18. " IRQ_STA_18 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 17. " IRQ_STA_17 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 16. " IRQ_STA_16 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "IRQ_STA_15 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,common irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641B0C++0x03
|
|
line.long 0x00 "COM_IRQ_MON_3,COMMON IRQ MONITOR REGISTER"
|
|
bitfld.long 0x00 31. " IRQ_STA_31 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 30. " IRQ_STA_30 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 29. " IRQ_STA_29 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 28. " IRQ_STA_28 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "IRQ_STA_27 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 26. " IRQ_STA_26 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 25. " IRQ_STA_25 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 24. " IRQ_STA_24 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "IRQ_STA_23 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 22. " IRQ_STA_22 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 21. " IRQ_STA_21 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 20. " IRQ_STA_20 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "IRQ_STA_19 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 18. " IRQ_STA_18 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 17. " IRQ_STA_17 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 16. " IRQ_STA_16 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "IRQ_STA_15 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,common irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641B10++0x03
|
|
line.long 0x00 "COM_IRQ_MON_4,COMMON IRQ MONITOR REGISTER"
|
|
bitfld.long 0x00 31. " IRQ_STA_31 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 30. " IRQ_STA_30 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 29. " IRQ_STA_29 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 28. " IRQ_STA_28 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "IRQ_STA_27 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 26. " IRQ_STA_26 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 25. " IRQ_STA_25 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 24. " IRQ_STA_24 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "IRQ_STA_23 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 22. " IRQ_STA_22 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 21. " IRQ_STA_21 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 20. " IRQ_STA_20 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "IRQ_STA_19 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 18. " IRQ_STA_18 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 17. " IRQ_STA_17 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 16. " IRQ_STA_16 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "IRQ_STA_15 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,common irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641B14++0x03
|
|
line.long 0x00 "COM_IRQ_MON_5,COMMON IRQ MONITOR REGISTER"
|
|
bitfld.long 0x00 31. " IRQ_STA_31 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 30. " IRQ_STA_30 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 29. " IRQ_STA_29 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 28. " IRQ_STA_28 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "IRQ_STA_27 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 26. " IRQ_STA_26 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 25. " IRQ_STA_25 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 24. " IRQ_STA_24 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "IRQ_STA_23 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 22. " IRQ_STA_22 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 21. " IRQ_STA_21 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 20. " IRQ_STA_20 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "IRQ_STA_19 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 18. " IRQ_STA_18 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 17. " IRQ_STA_17 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 16. " IRQ_STA_16 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "IRQ_STA_15 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,common irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641B18++0x03
|
|
line.long 0x00 "COM_IRQ_MON_6,COMMON IRQ MONITOR REGISTER"
|
|
bitfld.long 0x00 31. " IRQ_STA_31 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 30. " IRQ_STA_30 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 29. " IRQ_STA_29 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 28. " IRQ_STA_28 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "IRQ_STA_27 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 26. " IRQ_STA_26 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 25. " IRQ_STA_25 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 24. " IRQ_STA_24 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "IRQ_STA_23 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 22. " IRQ_STA_22 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 21. " IRQ_STA_21 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 20. " IRQ_STA_20 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "IRQ_STA_19 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 18. " IRQ_STA_18 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 17. " IRQ_STA_17 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 16. " IRQ_STA_16 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "IRQ_STA_15 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,common irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641B1C++0x03
|
|
line.long 0x00 "COM_IRQ_MON_7,COMMON IRQ MONITOR REGISTER"
|
|
bitfld.long 0x00 31. " IRQ_STA_31 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 30. " IRQ_STA_30 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 29. " IRQ_STA_29 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 28. " IRQ_STA_28 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. "IRQ_STA_27 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 26. " IRQ_STA_26 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 25. " IRQ_STA_25 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 24. " IRQ_STA_24 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. "IRQ_STA_23 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 22. " IRQ_STA_22 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 21. " IRQ_STA_21 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 20. " IRQ_STA_20 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "IRQ_STA_19 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 18. " IRQ_STA_18 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 17. " IRQ_STA_17 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 16. " IRQ_STA_16 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. "IRQ_STA_15 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 14. " IRQ_STA_14 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 13. " IRQ_STA_13 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 12. " IRQ_STA_12 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IRQ_STA_11 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 10. " IRQ_STA_10 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 9. " IRQ_STA_9 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 8. " IRQ_STA_8 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "IRQ_STA_7 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 6. " IRQ_STA_6 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 5. " IRQ_STA_5 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 4. " IRQ_STA_4 ,common irq monitor, can be clear by software programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "IRQ_STA_3 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_STA_2 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_STA_1 ,common irq monitor, can be clear by software programming" "0,1"
|
|
bitfld.long 0x00 0. " IRQ_STA_0 ,common irq monitor, can be clear by software programming" "0,1"
|
|
group ad:0xF0641C00++0x03
|
|
line.long 0x00 "SMC_RES_RS,SMC RESERVE REGISTER RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641C04++0x03
|
|
line.long 0x00 "SMC_RES,SMC RESERVE REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " RES ,reserve register for future use"
|
|
group ad:0xF0641C08++0x03
|
|
line.long 0x00 "SMC_MISC_RS,SMC MISC REGISTER RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641C0C++0x03
|
|
line.long 0x00 "SMC_MISC,SMC MISC REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MISC ,bit[31:2]: reserved bit[1]: lpbk force check enable. loopback wdt DIv number check without req/ack active bit[0]: enable for permission error as apbslverr"
|
|
group ad:0xF0641C10++0x03
|
|
line.long 0x00 "SMC_SUP_DOM,SMC SUPER DOMAIN REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock the entire register" "0,1"
|
|
bitfld.long 0x00 5.--6. " PPROT ,pprot for super doman" "0,1,2,3"
|
|
bitfld.long 0x00 4. " SEC_EN ,check pprot enable" "0,1"
|
|
bitfld.long 0x00 0.--3. " DID ,super domain domain id bit3 reserved bit[2:0] DId used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0641C14++0x03
|
|
line.long 0x00 "SWM_MON,SWM STATUS MONITOR REGISTER"
|
|
bitfld.long 0x00 21.--25. " AP_INTER_SWM ,ap internal swm transition status 5'd1: RUN 5'd2: LP PROC 5'd4: RUN PROC 5'd8: LP 5'd16: RTC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " SAF_INTER_SWM ,saf internal swm transition status 5'd1: RUN 5'd2: LP PROC 5'd4: RUN PROC 5'd8: LP 5'd16: RTC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--11. " SOC_SWM ,soc swm status 4'd1: RUN 4'd2: SLP 4'd4: HIB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " AP_SWM ,ap swm status 4'd1: RUN 4'd2: SLP 4'd4: HIB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. "SAF_SWM ,saf swm status 4'd1: RUN 4'd2: SLP 4'd4: HIB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0641D00++0x03
|
|
line.long 0x00 "SMC_FUSA_RS,SMC FUSA RELATED REGISTER RULE SPACE REGISTER"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641D04++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 23. " PADDR_INT_CLR ,paddr uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 22. " PUSER_INT_CLR ,puser uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 21. " PCTRL1_INT_CLR ,pctrl1 uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 20. " PCTRL0_INT_CLR ,pctrl0 uncorrectable error interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. "PWDAT_C_INT_CLR ,pwdata correctable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " PWDAT_U_INT_CLR ,pwdata uncorrectable error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " PWDAT_F_INT_CLR ,pwdata fatal error interrupt clear" "0,1"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. "PUSER_INT_STA ,puser uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 11. " PWDAT_C_INT_STA ,pwdata correctable error interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status." "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. " PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF0641D08++0x03
|
|
line.long 0x00 "APB_LKSTEP_INT,APB LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 19. " SYNC_ERR_INT_CLR ,sync error interrupt clear" "0,1"
|
|
bitfld.long 0x00 18. " RESP_ERR_INT_CLR ,response parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 17. " REQ_ERR_INT_CLR ,request parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 16. " CMP_INT_CLR ,lockstep compare interrupt clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "SYNC_ERR_INT_STA ,sync error status" "0,1"
|
|
bitfld.long 0x00 10. " RESP_ERR_INT_STA ,response parity error status" "0,1"
|
|
bitfld.long 0x00 9. " REQ_ERR_INT_STA ,request parity error status" "0,1"
|
|
bitfld.long 0x00 8. " CMP_INT_STA ,lockstep compare error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SYNC_ERR_INT_EN ,apb sync error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. " RESP_ERR_INT_EN ,apb response parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " REQ_ERR_INT_EN ,apb request parity error interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. " CMP_INT_EN ,lockstep compare interrupt enable" "0,1"
|
|
group ad:0xF0641D0C++0x03
|
|
line.long 0x00 "SMC_FUSA_INT,SMC INTERNAL FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 21. " LKSTEP_CMP_ERR_CLR ,rstgen core lockstep compare error clear" "0,1"
|
|
bitfld.long 0x00 20. " SYNC_ERR_CLR ,internal sync check error clear" "0,1"
|
|
bitfld.long 0x00 19. " SOC_24M_ERR_CLR ,soc 24m error clear" "0,1"
|
|
bitfld.long 0x00 18. " SMC_CFG_ERR_CLR ,swm global config error clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. "TOUT_ERR_CLR ,timeout error clear" "0,1"
|
|
bitfld.long 0x00 16. " SWM_CHK_ERR_CLR ,swm check error clear check error include: 1. swm payload input is DIfferent from swm payload output 2. swm ack received when there is no swm req" "0,1"
|
|
bitfld.long 0x00 13. " LKSTEP_CMP_ERR_STA ,rstgen core lockstep compare error status" "0,1"
|
|
bitfld.long 0x00 12. " SYNC_ERR_STA ,internal sync check error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "SOC_24M_ERR_STA ,soc 24m error status" "0,1"
|
|
bitfld.long 0x00 10. " SMC_CFG_ERR_STA ,swm global config error status. include primary core and lp_mode" "0,1"
|
|
bitfld.long 0x00 9. " TOUT_ERR_STA ,timeout error status" "0,1"
|
|
bitfld.long 0x00 8. " SWM_CHK_ERR_STA ,swm check error status check error include: 1. swm payload input is DIfferent from swm payload output 2. swm ack received when there is no swm req" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "LKSTEP_CMP_ERR_EN ,rstgen core lockstep compare error enable" "0,1"
|
|
bitfld.long 0x00 4. " SYNC_ERR_EN ,internal sync check error enable" "0,1"
|
|
bitfld.long 0x00 3. " SOC_24M_ERR_EN ,soc 24m error enable" "0,1"
|
|
bitfld.long 0x00 2. " SMC_CFG_ERR_EN ,smc global config error enable include primary core and lp_mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "TOUT_ERR_EN ,timeout error enable" "0,1"
|
|
bitfld.long 0x00 0. " SWM_CHK_ERR_EN ,swm check error enable. check error include: 1. swm payload input is DIfferent from swm payload output 2. swm ack received when there is no swm req" "0,1"
|
|
group ad:0xF0641D10++0x03
|
|
line.long 0x00 "SMC_TOUT_STA,SMC TIMEOUT EVENT MONITOR STATUS REGISTER"
|
|
bitfld.long 0x00 15. " TOUT_15 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 14. " TOUT_14 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 13. " TOUT_13 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 12. " TOUT_12 ,smc timeout event status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "TOUT_11 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 10. " TOUT_10 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 9. " TOUT_9 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 8. " TOUT_8 ,smc timeout event status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "TOUT_7 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 6. " TOUT_6 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 5. " TOUT_5 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 4. " TOUT_4 ,smc timeout event status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "TOUT_3 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 2. " TOUT_2 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 1. " TOUT_1 ,smc timeout event status." "0,1"
|
|
bitfld.long 0x00 0. " TOUT_0 ,smc timeout event status." "0,1"
|
|
group ad:0xF0641D14++0x03
|
|
line.long 0x00 "SMC_ILL_TRANS_STA,SMC ILLEGAL TRANSFER EVENT MONITOR STATUS REGISTER"
|
|
bitfld.long 0x00 9. " ILL_TRANS_9 ,smc illegal transfer status." "0,1"
|
|
bitfld.long 0x00 8. " ILL_TRANS_8 ,smc illegal transfer status." "0,1"
|
|
bitfld.long 0x00 7. " ILL_TRANS_7 ,smc illegal transfer status." "0,1"
|
|
bitfld.long 0x00 6. " ILL_TRANS_6 ,smc illegal transfer status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ILL_TRANS_5 ,smc illegal transfer status." "0,1"
|
|
bitfld.long 0x00 4. " ILL_TRANS_4 ,smc illegal transfer status." "0,1"
|
|
bitfld.long 0x00 3. " ILL_TRANS_3 ,smc illegal transfer status." "0,1"
|
|
bitfld.long 0x00 2. " ILL_TRANS_2 ,smc illegal transfer status." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "ILL_TRANS_1 ,smc illegal transfer status." "0,1"
|
|
bitfld.long 0x00 0. " ILL_TRANS_0 ,smc illegal transfer status." "0,1"
|
|
group ad:0xF0641D18++0x03
|
|
line.long 0x00 "WDT_LKSTEP_INT,WDT LOCKSTEP INTERRUPT REGISTER"
|
|
bitfld.long 0x00 18. " CMP_ERR_CLR ,lkstep cmp error clear" "0,1"
|
|
bitfld.long 0x00 17. " SYNC_ERR_CLR ,sync check error clear" "0,1"
|
|
bitfld.long 0x00 16. " TOUT_CHK_ERR_CLR ,timeout value check error clear" "0,1"
|
|
bitfld.long 0x00 10. " CMP_ERR_STA ,cmp error status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "SYNC_ERR_STA ,sync check error status" "0,1"
|
|
bitfld.long 0x00 8. " TOUT_CHK_ERR_STA ,timeout value check error status" "0,1"
|
|
bitfld.long 0x00 2. " CMP_ERR_EN ,cmp error enable" "0,1"
|
|
bitfld.long 0x00 1. " SYNC_ERR_EN ,sync check error enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "TOUT_CHK_ERR_EN ,timeout value check error enable" "0,1"
|
|
group ad:0xF0641D1C++0x03
|
|
line.long 0x00 "SMC_INJ_EN,SMC ERROR INJECTION ENABLE"
|
|
hexmask.long.word 0x00 0.--15. 1. " INJ_EN ,error injection enable bit[0]: irq error injection enable. bit[1]: smc lkstep error injection enable. bit[2]: aapb lkstep error injection enable bit[3]: aapb req ded error injection enable. bit[4]: aapb output error .."
|
|
group ad:0xF0641D20++0x03
|
|
line.long 0x00 "SMC_INJ_BIT,SMC ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 29.--31. " IRQ_INJ ,irq inj: bit0: inj for unc_irq bit1: inj for cor_irq bit2: inj for smc_irq" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " ERR_INJ_BIT ,error injection bit bit[3:0]: aapb resp ded error injection bit. bit[17:8]: smc lkstep error injection bit. bit[27:20]: smc dout error injection bit."
|
|
group ad:0xF0641D24++0x03
|
|
line.long 0x00 "SMC_INJ_BIT_1,SMC ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_BIT ,error injection bit bit[7:0]: aapb lkstep injection bit. bit[11:8]: aapb req ded error injection bit. bit[15:12]: aapb output error injection bit."
|
|
group ad:0xF0641D28++0x03
|
|
line.long 0x00 "SMC_INJ_BIT_2,SMC ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ_BIT ,wdt error injection bit bit[4:0]: wdt output injection bit bit[11:5]: wdt timeout value loopback error injection bit[17:12]: wdt lkstep cmp error injection bit"
|
|
group ad:0xF0641D40++0x03
|
|
line.long 0x00 "SMC_FUNC_INT_RS,This register is used for assign rule space for rstgen function interrupt register"
|
|
bitfld.long 0x00 31. " LOCK ,lock this domain register" "0,1"
|
|
bitfld.long 0x00 1.--4. " RS ,rule space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " EN ,enable domain id assign. 0: DIsabled, share with all domain 1: enabled" "0,1"
|
|
group ad:0xF0641D44++0x03
|
|
line.long 0x00 "SMC_FUNC_INT,SMC FUNC INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " ACCESS_PER_ERR_CLR ,access permission check error clear" "0,1"
|
|
bitfld.long 0x00 8. " ACCESS_PER_ERR_STA ,access permission check error status" "0,1"
|
|
bitfld.long 0x00 0. " ACCESS_PER_ERR_EN ,access permission check error enable" "0,1"
|
|
group ad:0xF0641F00++0x03
|
|
line.long 0x00 "SMC_DBG_SEL,SMC DEBUG SELECT REGISTER"
|
|
bitfld.long 0x00 0.--2. " SEL ,debug mux sel: 3'd1: dbg_out = {12'b0,saf_rstgen_swm_ack,saf_rstgen_swm_i,saf_rstgen_swm_req,saf_rstgen_swm_o,saf_ckgen_swm_ack,saf_ckgen_swm_i,saf_ckgen_swm_req,saf_ckgen_swm_o}; 3'd2: dbg_out = {12'b0,.." "0,1,2,3,4,5,6,7"
|
|
group ad:0xF0641F04++0x03
|
|
line.long 0x00 "SMC_DBG_MON,SMC DEBUG MONITOR REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " MON ,debug out"
|
|
tree.end
|
|
config 16. 8.
|
|
tree "SEM"
|
|
tree "SEM1"
|
|
width 22.
|
|
group ad:0xF07C0000++0x03
|
|
line.long 0x00 "SEM_COMMON_SET,SEM common settings"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP_ENABLE ,compare output enable bits for int0-7"
|
|
bitfld.long 0x00 23. " SIG_MON_GLB_EN ,signal monitor global enable" "0,1"
|
|
bitfld.long 0x00 17. " EI_GLOBAL_EN_LOCK ,Error Injection Global Enable Lock bit" "0,1"
|
|
bitfld.long 0x00 16. " EI_GLOBAL_EN ,Error Injection Global Enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "ERROR_DIV ,error DIvider ratio for waveform A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " ERROR_WAVE_SEL ,waveform A/B selection for normal/recoverable error" "0,1"
|
|
bitfld.long 0x00 10. " FATAL_HIGH_LOW ,fatal error High or Low selection" "0,1"
|
|
bitfld.long 0x00 8.--9. " SEM_INT_DC4_SEL ,SEM_INT DC4 selection" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "SEM_INT_DC3_SEL ,SEM_INT DC3 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " SEM_INT_DC2_SEL ,SEM_INT DC2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " SEM_INT_DC1_SEL ,SEM_INT DC1 selection" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " SEM_INT_DC0_SEL ,SEM_INT DC0 selection" "0,1,2,3"
|
|
group ad:0xF07C0004++0x03
|
|
line.long 0x00 "INT_TRIG,int0-7 trigger"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INT_TRIG ,int0-int7 trigger"
|
|
group ad:0xF07C0008++0x03
|
|
line.long 0x00 "INT_ENABLE_OVRD,int0-7 enable override"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INT_ENABLE_OVRD_VAL ,int0-7 enable override value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INT_ENABLE_OVRD_EN ,int0-7 enable override enable"
|
|
group ad:0xF07C000C++0x03
|
|
line.long 0x00 "ERR_INJ_CTRL,error injection control"
|
|
bitfld.long 0x00 8. " LOCK ," "0,1"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR_INJ_EN ," "0,1"
|
|
group ad:0xF07C0010++0x03
|
|
line.long 0x00 "IO_WAVE_CTRL,output io wave control"
|
|
bitfld.long 0x00 31. " LOCK ," "0,1"
|
|
bitfld.long 0x00 2.--3. " LEVEL_CFG ,the level for the io when normal[2] and recoverable error [3] occurs" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " LEVEL_EN ,if enable this bit the output io for the normal and recoverable error will be set as level [0] normal [1] recover case" "0,1,2,3"
|
|
group ad:0xF07C0014++0x03
|
|
line.long 0x00 "SEM_INT_CTRL,sem int ctrl"
|
|
bitfld.long 0x00 31. " LOCK ,Lock will only affect the ERR injection bits" "0,1"
|
|
bitfld.long 0x00 26. " REG_PARITY_EJ_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1"
|
|
bitfld.long 0x00 25. " GLOBAL_EJ_EN_ERR_INJ_EN ,global error injection enable , need a bit to control the error injection enable of itself. 1: err injection enable 0 error injection DIsable" "0,1"
|
|
bitfld.long 0x00 24. " GLOBAL_EJ_EN_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. "HW_INT_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10. " PMU_INT_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1"
|
|
bitfld.long 0x00 9. " CPU_INT_ERR_INJ ,1: error injection eanble" "0,1"
|
|
bitfld.long 0x00 8. " PAD_INT_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CORERR_INT_STAT ," "0,1"
|
|
bitfld.long 0x00 4. " UNCERR_INT_STAT ," "0,1"
|
|
bitfld.long 0x00 3. " CORERR_INT_ERR_INJ ," "0,1"
|
|
bitfld.long 0x00 2. " UNCERR_INT_ERR_INJ ," "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CORERR_INT_CLR ," "0,1"
|
|
bitfld.long 0x00 0. " UNCERR_INT_CLR ," "0,1"
|
|
group ad:0xF07C0020++0x03
|
|
line.long 0x00 "SEM_INT_MON_STATUS,the unc/cor err interrupt and signal monitor status"
|
|
bitfld.long 0x00 2. " CORERR_INT_STATUS ,corerr interrupt status" "0,1"
|
|
bitfld.long 0x00 1. " UNCERR_INT_STATUS ,uncerr interrupt status" "0,1"
|
|
bitfld.long 0x00 0. " SIG_MON_STATUS ,signal monitor error status" "0,1"
|
|
group ad:0xF07C0080++0x03
|
|
line.long 0x00 "INT_STATUS0,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS0 ,Interrupt status"
|
|
group ad:0xF07C0084++0x03
|
|
line.long 0x00 "INT_STATUS1,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS1 ,Interrupt status"
|
|
group ad:0xF07C0088++0x03
|
|
line.long 0x00 "INT_STATUS2,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS2 ,Interrupt status"
|
|
group ad:0xF07C008C++0x03
|
|
line.long 0x00 "INT_STATUS3,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS3 ,Interrupt status"
|
|
group ad:0xF07C0090++0x03
|
|
line.long 0x00 "INT_STATUS4,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS4 ,Interrupt status"
|
|
group ad:0xF07C0094++0x03
|
|
line.long 0x00 "INT_STATUS5,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS5 ,Interrupt status"
|
|
group ad:0xF07C0098++0x03
|
|
line.long 0x00 "INT_STATUS6,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS6 ,Interrupt status"
|
|
group ad:0xF07C009C++0x03
|
|
line.long 0x00 "INT_STATUS7,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS7 ,Interrupt status"
|
|
group ad:0xF07C00A0++0x03
|
|
line.long 0x00 "INT_STATUS8,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS8 ,Interrupt status"
|
|
group ad:0xF07C00A4++0x03
|
|
line.long 0x00 "INT_STATUS9,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS9 ,Interrupt status"
|
|
group ad:0xF07C0100++0x03
|
|
line.long 0x00 "INT_ENABLE_00,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_00 ,interrupt enable for int0"
|
|
group ad:0xF07C0104++0x03
|
|
line.long 0x00 "INT_ENABLE_01,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_01 ,interrupt enable for int0"
|
|
group ad:0xF07C0108++0x03
|
|
line.long 0x00 "INT_ENABLE_02,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_02 ,interrupt enable for int0"
|
|
group ad:0xF07C010C++0x03
|
|
line.long 0x00 "INT_ENABLE_03,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_03 ,interrupt enable for int0"
|
|
group ad:0xF07C0110++0x03
|
|
line.long 0x00 "INT_ENABLE_04,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_04 ,interrupt enable for int0"
|
|
group ad:0xF07C0114++0x03
|
|
line.long 0x00 "INT_ENABLE_05,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_05 ,interrupt enable for int0"
|
|
group ad:0xF07C0118++0x03
|
|
line.long 0x00 "INT_ENABLE_06,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_06 ,interrupt enable for int0"
|
|
group ad:0xF07C011C++0x03
|
|
line.long 0x00 "INT_ENABLE_07,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_07 ,interrupt enable for int0"
|
|
group ad:0xF07C0120++0x03
|
|
line.long 0x00 "INT_ENABLE_08,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_08 ,interrupt enable for int0"
|
|
group ad:0xF07C0124++0x03
|
|
line.long 0x00 "INT_ENABLE_09,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_09 ,interrupt enable for int0"
|
|
group ad:0xF07C0180++0x03
|
|
line.long 0x00 "INT_ENABLE_10,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_10 ,interrupt enable for int1"
|
|
group ad:0xF07C0184++0x03
|
|
line.long 0x00 "INT_ENABLE_11,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_11 ,interrupt enable for int1"
|
|
group ad:0xF07C0188++0x03
|
|
line.long 0x00 "INT_ENABLE_12,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_12 ,interrupt enable for int1"
|
|
group ad:0xF07C018C++0x03
|
|
line.long 0x00 "INT_ENABLE_13,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_13 ,interrupt enable for int1"
|
|
group ad:0xF07C0190++0x03
|
|
line.long 0x00 "INT_ENABLE_14,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_14 ,interrupt enable for int1"
|
|
group ad:0xF07C0194++0x03
|
|
line.long 0x00 "INT_ENABLE_15,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_15 ,interrupt enable for int1"
|
|
group ad:0xF07C0198++0x03
|
|
line.long 0x00 "INT_ENABLE_16,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_16 ,interrupt enable for int1"
|
|
group ad:0xF07C019C++0x03
|
|
line.long 0x00 "INT_ENABLE_17,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_17 ,interrupt enable for int1"
|
|
group ad:0xF07C01A0++0x03
|
|
line.long 0x00 "INT_ENABLE_18,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_18 ,interrupt enable for int1"
|
|
group ad:0xF07C01A4++0x03
|
|
line.long 0x00 "INT_ENABLE_19,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_19 ,interrupt enable for int1"
|
|
group ad:0xF07C0200++0x03
|
|
line.long 0x00 "INT_ENABLE_20,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_20 ,interrupt enable for int2"
|
|
group ad:0xF07C0204++0x03
|
|
line.long 0x00 "INT_ENABLE_21,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_21 ,interrupt enable for int2"
|
|
group ad:0xF07C0208++0x03
|
|
line.long 0x00 "INT_ENABLE_22,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_22 ,interrupt enable for int2"
|
|
group ad:0xF07C020C++0x03
|
|
line.long 0x00 "INT_ENABLE_23,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_23 ,interrupt enable for int2"
|
|
group ad:0xF07C0210++0x03
|
|
line.long 0x00 "INT_ENABLE_24,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_24 ,interrupt enable for int2"
|
|
group ad:0xF07C0214++0x03
|
|
line.long 0x00 "INT_ENABLE_25,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_25 ,interrupt enable for int2"
|
|
group ad:0xF07C0218++0x03
|
|
line.long 0x00 "INT_ENABLE_26,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_26 ,interrupt enable for int2"
|
|
group ad:0xF07C021C++0x03
|
|
line.long 0x00 "INT_ENABLE_27,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_27 ,interrupt enable for int2"
|
|
group ad:0xF07C0220++0x03
|
|
line.long 0x00 "INT_ENABLE_28,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_28 ,interrupt enable for int2"
|
|
group ad:0xF07C0224++0x03
|
|
line.long 0x00 "INT_ENABLE_29,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_29 ,interrupt enable for int2"
|
|
group ad:0xF07C0280++0x03
|
|
line.long 0x00 "INT_ENABLE_30,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_30 ,interrupt enable for int3"
|
|
group ad:0xF07C0284++0x03
|
|
line.long 0x00 "INT_ENABLE_31,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_31 ,interrupt enable for int3"
|
|
group ad:0xF07C0288++0x03
|
|
line.long 0x00 "INT_ENABLE_32,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_32 ,interrupt enable for int3"
|
|
group ad:0xF07C028C++0x03
|
|
line.long 0x00 "INT_ENABLE_33,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_33 ,interrupt enable for int3"
|
|
group ad:0xF07C0290++0x03
|
|
line.long 0x00 "INT_ENABLE_34,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_34 ,interrupt enable for int3"
|
|
group ad:0xF07C0294++0x03
|
|
line.long 0x00 "INT_ENABLE_35,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_35 ,interrupt enable for int3"
|
|
group ad:0xF07C0298++0x03
|
|
line.long 0x00 "INT_ENABLE_36,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_36 ,interrupt enable for int3"
|
|
group ad:0xF07C029C++0x03
|
|
line.long 0x00 "INT_ENABLE_37,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_37 ,interrupt enable for int3"
|
|
group ad:0xF07C02A0++0x03
|
|
line.long 0x00 "INT_ENABLE_38,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_38 ,interrupt enable for int3"
|
|
group ad:0xF07C02A4++0x03
|
|
line.long 0x00 "INT_ENABLE_39,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_39 ,interrupt enable for int3"
|
|
group ad:0xF07C0300++0x03
|
|
line.long 0x00 "INT_ENABLE_40,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_40 ,interrupt enable for int4"
|
|
group ad:0xF07C0304++0x03
|
|
line.long 0x00 "INT_ENABLE_41,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_41 ,interrupt enable for int4"
|
|
group ad:0xF07C0308++0x03
|
|
line.long 0x00 "INT_ENABLE_42,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_42 ,interrupt enable for int4"
|
|
group ad:0xF07C030C++0x03
|
|
line.long 0x00 "INT_ENABLE_43,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_43 ,interrupt enable for int4"
|
|
group ad:0xF07C0310++0x03
|
|
line.long 0x00 "INT_ENABLE_44,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_44 ,interrupt enable for int4"
|
|
group ad:0xF07C0314++0x03
|
|
line.long 0x00 "INT_ENABLE_45,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_45 ,interrupt enable for int4"
|
|
group ad:0xF07C0318++0x03
|
|
line.long 0x00 "INT_ENABLE_46,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_46 ,interrupt enable for int4"
|
|
group ad:0xF07C031C++0x03
|
|
line.long 0x00 "INT_ENABLE_47,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_47 ,interrupt enable for int4"
|
|
group ad:0xF07C0320++0x03
|
|
line.long 0x00 "INT_ENABLE_48,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_48 ,interrupt enable for int4"
|
|
group ad:0xF07C0324++0x03
|
|
line.long 0x00 "INT_ENABLE_49,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_49 ,interrupt enable for int4"
|
|
group ad:0xF07C0380++0x03
|
|
line.long 0x00 "INT_ENABLE_50,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_50 ,interrupt enable for int5"
|
|
group ad:0xF07C0384++0x03
|
|
line.long 0x00 "INT_ENABLE_51,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_51 ,interrupt enable for int5"
|
|
group ad:0xF07C0388++0x03
|
|
line.long 0x00 "INT_ENABLE_52,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_52 ,interrupt enable for int5"
|
|
group ad:0xF07C038C++0x03
|
|
line.long 0x00 "INT_ENABLE_53,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_53 ,interrupt enable for int5"
|
|
group ad:0xF07C0390++0x03
|
|
line.long 0x00 "INT_ENABLE_54,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_54 ,interrupt enable for int5"
|
|
group ad:0xF07C0394++0x03
|
|
line.long 0x00 "INT_ENABLE_55,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_55 ,interrupt enable for int5"
|
|
group ad:0xF07C0398++0x03
|
|
line.long 0x00 "INT_ENABLE_56,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_56 ,interrupt enable for int5"
|
|
group ad:0xF07C039C++0x03
|
|
line.long 0x00 "INT_ENABLE_57,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_57 ,interrupt enable for int5"
|
|
group ad:0xF07C03A0++0x03
|
|
line.long 0x00 "INT_ENABLE_58,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_58 ,interrupt enable for int5"
|
|
group ad:0xF07C03A4++0x03
|
|
line.long 0x00 "INT_ENABLE_59,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_59 ,interrupt enable for int5"
|
|
group ad:0xF07C0400++0x03
|
|
line.long 0x00 "INT_ENABLE_60,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_60 ,interrupt enable for int6"
|
|
group ad:0xF07C0404++0x03
|
|
line.long 0x00 "INT_ENABLE_61,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_61 ,interrupt enable for int6"
|
|
group ad:0xF07C0408++0x03
|
|
line.long 0x00 "INT_ENABLE_62,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_62 ,interrupt enable for int6"
|
|
group ad:0xF07C040C++0x03
|
|
line.long 0x00 "INT_ENABLE_63,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_63 ,interrupt enable for int6"
|
|
group ad:0xF07C0410++0x03
|
|
line.long 0x00 "INT_ENABLE_64,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_64 ,interrupt enable for int6"
|
|
group ad:0xF07C0414++0x03
|
|
line.long 0x00 "INT_ENABLE_65,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_65 ,interrupt enable for int6"
|
|
group ad:0xF07C0418++0x03
|
|
line.long 0x00 "INT_ENABLE_66,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_66 ,interrupt enable for int6"
|
|
group ad:0xF07C041C++0x03
|
|
line.long 0x00 "INT_ENABLE_67,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_67 ,interrupt enable for int6"
|
|
group ad:0xF07C0420++0x03
|
|
line.long 0x00 "INT_ENABLE_68,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_68 ,interrupt enable for int6"
|
|
group ad:0xF07C0424++0x03
|
|
line.long 0x00 "INT_ENABLE_69,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_69 ,interrupt enable for int6"
|
|
group ad:0xF07C0480++0x03
|
|
line.long 0x00 "INT_ENABLE_70,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_70 ,interrupt enable for int7"
|
|
group ad:0xF07C0484++0x03
|
|
line.long 0x00 "INT_ENABLE_71,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_71 ,interrupt enable for int7"
|
|
group ad:0xF07C0488++0x03
|
|
line.long 0x00 "INT_ENABLE_72,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_72 ,interrupt enable for int7"
|
|
group ad:0xF07C048C++0x03
|
|
line.long 0x00 "INT_ENABLE_73,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_73 ,interrupt enable for int7"
|
|
group ad:0xF07C0490++0x03
|
|
line.long 0x00 "INT_ENABLE_74,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_74 ,interrupt enable for int7"
|
|
group ad:0xF07C0494++0x03
|
|
line.long 0x00 "INT_ENABLE_75,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_75 ,interrupt enable for int7"
|
|
group ad:0xF07C0498++0x03
|
|
line.long 0x00 "INT_ENABLE_76,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_76 ,interrupt enable for int7"
|
|
group ad:0xF07C049C++0x03
|
|
line.long 0x00 "INT_ENABLE_77,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_77 ,interrupt enable for int7"
|
|
group ad:0xF07C04A0++0x03
|
|
line.long 0x00 "INT_ENABLE_78,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_78 ,interrupt enable for int7"
|
|
group ad:0xF07C04A4++0x03
|
|
line.long 0x00 "INT_ENABLE_79,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_79 ,interrupt enable for int7"
|
|
group ad:0xF07C0500++0x03
|
|
line.long 0x00 "TGT_VALUE0,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE0 ,monitor target value"
|
|
group ad:0xF07C0504++0x03
|
|
line.long 0x00 "TGT_VALUE1,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE1 ,monitor target value"
|
|
group ad:0xF07C0508++0x03
|
|
line.long 0x00 "TGT_VALUE2,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE2 ,monitor target value"
|
|
group ad:0xF07C050C++0x03
|
|
line.long 0x00 "TGT_VALUE3,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE3 ,monitor target value"
|
|
group ad:0xF07C0510++0x03
|
|
line.long 0x00 "TGT_VALUE4,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE4 ,monitor target value"
|
|
group ad:0xF07C0514++0x03
|
|
line.long 0x00 "TGT_VALUE5,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE5 ,monitor target value"
|
|
group ad:0xF07C0580++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE0,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE0 ,monitor enable"
|
|
group ad:0xF07C0584++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE1,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE1 ,monitor enable"
|
|
group ad:0xF07C0588++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE2,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE2 ,monitor enable"
|
|
group ad:0xF07C058C++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE3,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE3 ,monitor enable"
|
|
group ad:0xF07C0590++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE4,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE4 ,monitor enable"
|
|
group ad:0xF07C0594++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE5,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE5 ,monitor enable"
|
|
group ad:0xF07C0600++0x03
|
|
line.long 0x00 "CORERR_INT_ENABLE_00,corerr interrupt enable int_0"
|
|
hexmask.long 0x00 0.--31. 1. " CORERR_INT_ENABLE_00 ,"
|
|
group ad:0xF07C0680++0x03
|
|
line.long 0x00 "CORERR_INT_ENABLE_10,corerr interrupt enable int_1"
|
|
hexmask.long 0x00 0.--31. 1. " CORERR_INT_ENABLE_10 ,"
|
|
group ad:0xF07C0700++0x03
|
|
line.long 0x00 "CORERR_INT_ENABLE_20,corerr interrupt enable int_2"
|
|
hexmask.long 0x00 0.--31. 1. " CORERR_INT_ENABLE_20 ,"
|
|
group ad:0xF07C0780++0x03
|
|
line.long 0x00 "CORERR_INT_STAT0,"
|
|
hexmask.long 0x00 0.--31. 1. " CORERR_INT_STAT0 ,CORERR Int status"
|
|
group ad:0xF07C0800++0x03
|
|
line.long 0x00 "SIG_MON_STATUS0,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS0 ,signal monitor error status"
|
|
group ad:0xF07C0804++0x03
|
|
line.long 0x00 "SIG_MON_STATUS1,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS1 ,signal monitor error status"
|
|
group ad:0xF07C0808++0x03
|
|
line.long 0x00 "SIG_MON_STATUS2,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS2 ,signal monitor error status"
|
|
group ad:0xF07C080C++0x03
|
|
line.long 0x00 "SIG_MON_STATUS3,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS3 ,signal monitor error status"
|
|
group ad:0xF07C0810++0x03
|
|
line.long 0x00 "SIG_MON_STATUS4,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS4 ,signal monitor error status"
|
|
group ad:0xF07C0814++0x03
|
|
line.long 0x00 "SIG_MON_STATUS5,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS5 ,signal monitor error status"
|
|
tree.end
|
|
tree "SEM2"
|
|
width 22.
|
|
group ad:0xF07D0000++0x03
|
|
line.long 0x00 "SEM_COMMON_SET,SEM common settings"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMP_ENABLE ,compare output enable bits for int0-7"
|
|
bitfld.long 0x00 23. " SIG_MON_GLB_EN ,signal monitor global enable" "0,1"
|
|
bitfld.long 0x00 17. " EI_GLOBAL_EN_LOCK ,Error Injection Global Enable Lock bit" "0,1"
|
|
bitfld.long 0x00 16. " EI_GLOBAL_EN ,Error Injection Global Enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "ERROR_DIV ,error DIvider ratio for waveform A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " ERROR_WAVE_SEL ,waveform A/B selection for normal/recoverable error" "0,1"
|
|
bitfld.long 0x00 10. " FATAL_HIGH_LOW ,fatal error High or Low selection" "0,1"
|
|
bitfld.long 0x00 8.--9. " SEM_INT_DC4_SEL ,SEM_INT DC4 selection" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. "SEM_INT_DC3_SEL ,SEM_INT DC3 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " SEM_INT_DC2_SEL ,SEM_INT DC2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " SEM_INT_DC1_SEL ,SEM_INT DC1 selection" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " SEM_INT_DC0_SEL ,SEM_INT DC0 selection" "0,1,2,3"
|
|
group ad:0xF07D0004++0x03
|
|
line.long 0x00 "INT_TRIG,int0-7 trigger"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INT_TRIG ,int0-int7 trigger"
|
|
group ad:0xF07D0008++0x03
|
|
line.long 0x00 "INT_ENABLE_OVRD,int0-7 enable override"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INT_ENABLE_OVRD_VAL ,int0-7 enable override value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INT_ENABLE_OVRD_EN ,int0-7 enable override enable"
|
|
group ad:0xF07D000C++0x03
|
|
line.long 0x00 "ERR_INJ_CTRL,error injection control"
|
|
bitfld.long 0x00 8. " LOCK ," "0,1"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR_INJ_EN ," "0,1"
|
|
group ad:0xF07D0010++0x03
|
|
line.long 0x00 "IO_WAVE_CTRL,output io wave control"
|
|
bitfld.long 0x00 31. " LOCK ," "0,1"
|
|
bitfld.long 0x00 2.--3. " LEVEL_CFG ,the level for the io when normal[2] and recoverable error [3] occurs" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " LEVEL_EN ,if enable this bit the output io for the normal and recoverable error will be set as level [0] normal [1] recover case" "0,1,2,3"
|
|
group ad:0xF07D0014++0x03
|
|
line.long 0x00 "SEM_INT_CTRL,sem int ctrl"
|
|
bitfld.long 0x00 31. " LOCK ,Lock will only affect the ERR injection bits" "0,1"
|
|
bitfld.long 0x00 26. " REG_PARITY_EJ_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1"
|
|
bitfld.long 0x00 25. " GLOBAL_EJ_EN_ERR_INJ_EN ,global error injection enable , need a bit to control the error injection enable of itself. 1: err injection enable 0 error injection DIsable" "0,1"
|
|
bitfld.long 0x00 24. " GLOBAL_EJ_EN_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. "HW_INT_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10. " PMU_INT_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1"
|
|
bitfld.long 0x00 9. " CPU_INT_ERR_INJ ,1: error injection eanble" "0,1"
|
|
bitfld.long 0x00 8. " PAD_INT_ERR_INJ ,1: err injection enable 0 error injection DIsable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "CORERR_INT_STAT ," "0,1"
|
|
bitfld.long 0x00 4. " UNCERR_INT_STAT ," "0,1"
|
|
bitfld.long 0x00 3. " CORERR_INT_ERR_INJ ," "0,1"
|
|
bitfld.long 0x00 2. " UNCERR_INT_ERR_INJ ," "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "CORERR_INT_CLR ," "0,1"
|
|
bitfld.long 0x00 0. " UNCERR_INT_CLR ," "0,1"
|
|
group ad:0xF07D0020++0x03
|
|
line.long 0x00 "SEM_INT_MON_STATUS,the unc/cor err interrupt and signal monitor status"
|
|
bitfld.long 0x00 2. " CORERR_INT_STATUS ,corerr interrupt status" "0,1"
|
|
bitfld.long 0x00 1. " UNCERR_INT_STATUS ,uncerr interrupt status" "0,1"
|
|
bitfld.long 0x00 0. " SIG_MON_STATUS ,signal monitor error status" "0,1"
|
|
group ad:0xF07D0080++0x03
|
|
line.long 0x00 "INT_STATUS0,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS0 ,Interrupt status"
|
|
group ad:0xF07D0084++0x03
|
|
line.long 0x00 "INT_STATUS1,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS1 ,Interrupt status"
|
|
group ad:0xF07D0088++0x03
|
|
line.long 0x00 "INT_STATUS2,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS2 ,Interrupt status"
|
|
group ad:0xF07D008C++0x03
|
|
line.long 0x00 "INT_STATUS3,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS3 ,Interrupt status"
|
|
group ad:0xF07D0090++0x03
|
|
line.long 0x00 "INT_STATUS4,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS4 ,Interrupt status"
|
|
group ad:0xF07D0094++0x03
|
|
line.long 0x00 "INT_STATUS5,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS5 ,Interrupt status"
|
|
group ad:0xF07D0098++0x03
|
|
line.long 0x00 "INT_STATUS6,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS6 ,Interrupt status"
|
|
group ad:0xF07D009C++0x03
|
|
line.long 0x00 "INT_STATUS7,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS7 ,Interrupt status"
|
|
group ad:0xF07D00A0++0x03
|
|
line.long 0x00 "INT_STATUS8,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS8 ,Interrupt status"
|
|
group ad:0xF07D00A4++0x03
|
|
line.long 0x00 "INT_STATUS9,interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " INT_STATUS9 ,Interrupt status"
|
|
group ad:0xF07D0100++0x03
|
|
line.long 0x00 "INT_ENABLE_00,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_00 ,interrupt enable for int0"
|
|
group ad:0xF07D0104++0x03
|
|
line.long 0x00 "INT_ENABLE_01,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_01 ,interrupt enable for int0"
|
|
group ad:0xF07D0108++0x03
|
|
line.long 0x00 "INT_ENABLE_02,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_02 ,interrupt enable for int0"
|
|
group ad:0xF07D010C++0x03
|
|
line.long 0x00 "INT_ENABLE_03,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_03 ,interrupt enable for int0"
|
|
group ad:0xF07D0110++0x03
|
|
line.long 0x00 "INT_ENABLE_04,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_04 ,interrupt enable for int0"
|
|
group ad:0xF07D0114++0x03
|
|
line.long 0x00 "INT_ENABLE_05,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_05 ,interrupt enable for int0"
|
|
group ad:0xF07D0118++0x03
|
|
line.long 0x00 "INT_ENABLE_06,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_06 ,interrupt enable for int0"
|
|
group ad:0xF07D011C++0x03
|
|
line.long 0x00 "INT_ENABLE_07,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_07 ,interrupt enable for int0"
|
|
group ad:0xF07D0120++0x03
|
|
line.long 0x00 "INT_ENABLE_08,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_08 ,interrupt enable for int0"
|
|
group ad:0xF07D0124++0x03
|
|
line.long 0x00 "INT_ENABLE_09,interrupt enable for int_0"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_09 ,interrupt enable for int0"
|
|
group ad:0xF07D0180++0x03
|
|
line.long 0x00 "INT_ENABLE_10,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_10 ,interrupt enable for int1"
|
|
group ad:0xF07D0184++0x03
|
|
line.long 0x00 "INT_ENABLE_11,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_11 ,interrupt enable for int1"
|
|
group ad:0xF07D0188++0x03
|
|
line.long 0x00 "INT_ENABLE_12,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_12 ,interrupt enable for int1"
|
|
group ad:0xF07D018C++0x03
|
|
line.long 0x00 "INT_ENABLE_13,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_13 ,interrupt enable for int1"
|
|
group ad:0xF07D0190++0x03
|
|
line.long 0x00 "INT_ENABLE_14,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_14 ,interrupt enable for int1"
|
|
group ad:0xF07D0194++0x03
|
|
line.long 0x00 "INT_ENABLE_15,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_15 ,interrupt enable for int1"
|
|
group ad:0xF07D0198++0x03
|
|
line.long 0x00 "INT_ENABLE_16,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_16 ,interrupt enable for int1"
|
|
group ad:0xF07D019C++0x03
|
|
line.long 0x00 "INT_ENABLE_17,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_17 ,interrupt enable for int1"
|
|
group ad:0xF07D01A0++0x03
|
|
line.long 0x00 "INT_ENABLE_18,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_18 ,interrupt enable for int1"
|
|
group ad:0xF07D01A4++0x03
|
|
line.long 0x00 "INT_ENABLE_19,interrupt enable for int_1"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_19 ,interrupt enable for int1"
|
|
group ad:0xF07D0200++0x03
|
|
line.long 0x00 "INT_ENABLE_20,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_20 ,interrupt enable for int2"
|
|
group ad:0xF07D0204++0x03
|
|
line.long 0x00 "INT_ENABLE_21,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_21 ,interrupt enable for int2"
|
|
group ad:0xF07D0208++0x03
|
|
line.long 0x00 "INT_ENABLE_22,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_22 ,interrupt enable for int2"
|
|
group ad:0xF07D020C++0x03
|
|
line.long 0x00 "INT_ENABLE_23,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_23 ,interrupt enable for int2"
|
|
group ad:0xF07D0210++0x03
|
|
line.long 0x00 "INT_ENABLE_24,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_24 ,interrupt enable for int2"
|
|
group ad:0xF07D0214++0x03
|
|
line.long 0x00 "INT_ENABLE_25,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_25 ,interrupt enable for int2"
|
|
group ad:0xF07D0218++0x03
|
|
line.long 0x00 "INT_ENABLE_26,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_26 ,interrupt enable for int2"
|
|
group ad:0xF07D021C++0x03
|
|
line.long 0x00 "INT_ENABLE_27,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_27 ,interrupt enable for int2"
|
|
group ad:0xF07D0220++0x03
|
|
line.long 0x00 "INT_ENABLE_28,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_28 ,interrupt enable for int2"
|
|
group ad:0xF07D0224++0x03
|
|
line.long 0x00 "INT_ENABLE_29,interrupt enable for int_2"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_29 ,interrupt enable for int2"
|
|
group ad:0xF07D0280++0x03
|
|
line.long 0x00 "INT_ENABLE_30,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_30 ,interrupt enable for int3"
|
|
group ad:0xF07D0284++0x03
|
|
line.long 0x00 "INT_ENABLE_31,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_31 ,interrupt enable for int3"
|
|
group ad:0xF07D0288++0x03
|
|
line.long 0x00 "INT_ENABLE_32,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_32 ,interrupt enable for int3"
|
|
group ad:0xF07D028C++0x03
|
|
line.long 0x00 "INT_ENABLE_33,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_33 ,interrupt enable for int3"
|
|
group ad:0xF07D0290++0x03
|
|
line.long 0x00 "INT_ENABLE_34,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_34 ,interrupt enable for int3"
|
|
group ad:0xF07D0294++0x03
|
|
line.long 0x00 "INT_ENABLE_35,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_35 ,interrupt enable for int3"
|
|
group ad:0xF07D0298++0x03
|
|
line.long 0x00 "INT_ENABLE_36,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_36 ,interrupt enable for int3"
|
|
group ad:0xF07D029C++0x03
|
|
line.long 0x00 "INT_ENABLE_37,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_37 ,interrupt enable for int3"
|
|
group ad:0xF07D02A0++0x03
|
|
line.long 0x00 "INT_ENABLE_38,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_38 ,interrupt enable for int3"
|
|
group ad:0xF07D02A4++0x03
|
|
line.long 0x00 "INT_ENABLE_39,interrupt enable for int_3"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_39 ,interrupt enable for int3"
|
|
group ad:0xF07D0300++0x03
|
|
line.long 0x00 "INT_ENABLE_40,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_40 ,interrupt enable for int4"
|
|
group ad:0xF07D0304++0x03
|
|
line.long 0x00 "INT_ENABLE_41,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_41 ,interrupt enable for int4"
|
|
group ad:0xF07D0308++0x03
|
|
line.long 0x00 "INT_ENABLE_42,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_42 ,interrupt enable for int4"
|
|
group ad:0xF07D030C++0x03
|
|
line.long 0x00 "INT_ENABLE_43,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_43 ,interrupt enable for int4"
|
|
group ad:0xF07D0310++0x03
|
|
line.long 0x00 "INT_ENABLE_44,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_44 ,interrupt enable for int4"
|
|
group ad:0xF07D0314++0x03
|
|
line.long 0x00 "INT_ENABLE_45,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_45 ,interrupt enable for int4"
|
|
group ad:0xF07D0318++0x03
|
|
line.long 0x00 "INT_ENABLE_46,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_46 ,interrupt enable for int4"
|
|
group ad:0xF07D031C++0x03
|
|
line.long 0x00 "INT_ENABLE_47,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_47 ,interrupt enable for int4"
|
|
group ad:0xF07D0320++0x03
|
|
line.long 0x00 "INT_ENABLE_48,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_48 ,interrupt enable for int4"
|
|
group ad:0xF07D0324++0x03
|
|
line.long 0x00 "INT_ENABLE_49,interrupt enable for int_4"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_49 ,interrupt enable for int4"
|
|
group ad:0xF07D0380++0x03
|
|
line.long 0x00 "INT_ENABLE_50,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_50 ,interrupt enable for int5"
|
|
group ad:0xF07D0384++0x03
|
|
line.long 0x00 "INT_ENABLE_51,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_51 ,interrupt enable for int5"
|
|
group ad:0xF07D0388++0x03
|
|
line.long 0x00 "INT_ENABLE_52,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_52 ,interrupt enable for int5"
|
|
group ad:0xF07D038C++0x03
|
|
line.long 0x00 "INT_ENABLE_53,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_53 ,interrupt enable for int5"
|
|
group ad:0xF07D0390++0x03
|
|
line.long 0x00 "INT_ENABLE_54,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_54 ,interrupt enable for int5"
|
|
group ad:0xF07D0394++0x03
|
|
line.long 0x00 "INT_ENABLE_55,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_55 ,interrupt enable for int5"
|
|
group ad:0xF07D0398++0x03
|
|
line.long 0x00 "INT_ENABLE_56,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_56 ,interrupt enable for int5"
|
|
group ad:0xF07D039C++0x03
|
|
line.long 0x00 "INT_ENABLE_57,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_57 ,interrupt enable for int5"
|
|
group ad:0xF07D03A0++0x03
|
|
line.long 0x00 "INT_ENABLE_58,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_58 ,interrupt enable for int5"
|
|
group ad:0xF07D03A4++0x03
|
|
line.long 0x00 "INT_ENABLE_59,interrupt enable for int_5"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_59 ,interrupt enable for int5"
|
|
group ad:0xF07D0400++0x03
|
|
line.long 0x00 "INT_ENABLE_60,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_60 ,interrupt enable for int6"
|
|
group ad:0xF07D0404++0x03
|
|
line.long 0x00 "INT_ENABLE_61,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_61 ,interrupt enable for int6"
|
|
group ad:0xF07D0408++0x03
|
|
line.long 0x00 "INT_ENABLE_62,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_62 ,interrupt enable for int6"
|
|
group ad:0xF07D040C++0x03
|
|
line.long 0x00 "INT_ENABLE_63,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_63 ,interrupt enable for int6"
|
|
group ad:0xF07D0410++0x03
|
|
line.long 0x00 "INT_ENABLE_64,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_64 ,interrupt enable for int6"
|
|
group ad:0xF07D0414++0x03
|
|
line.long 0x00 "INT_ENABLE_65,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_65 ,interrupt enable for int6"
|
|
group ad:0xF07D0418++0x03
|
|
line.long 0x00 "INT_ENABLE_66,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_66 ,interrupt enable for int6"
|
|
group ad:0xF07D041C++0x03
|
|
line.long 0x00 "INT_ENABLE_67,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_67 ,interrupt enable for int6"
|
|
group ad:0xF07D0420++0x03
|
|
line.long 0x00 "INT_ENABLE_68,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_68 ,interrupt enable for int6"
|
|
group ad:0xF07D0424++0x03
|
|
line.long 0x00 "INT_ENABLE_69,interrupt enable for int_6"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_69 ,interrupt enable for int6"
|
|
group ad:0xF07D0480++0x03
|
|
line.long 0x00 "INT_ENABLE_70,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_70 ,interrupt enable for int7"
|
|
group ad:0xF07D0484++0x03
|
|
line.long 0x00 "INT_ENABLE_71,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_71 ,interrupt enable for int7"
|
|
group ad:0xF07D0488++0x03
|
|
line.long 0x00 "INT_ENABLE_72,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_72 ,interrupt enable for int7"
|
|
group ad:0xF07D048C++0x03
|
|
line.long 0x00 "INT_ENABLE_73,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_73 ,interrupt enable for int7"
|
|
group ad:0xF07D0490++0x03
|
|
line.long 0x00 "INT_ENABLE_74,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_74 ,interrupt enable for int7"
|
|
group ad:0xF07D0494++0x03
|
|
line.long 0x00 "INT_ENABLE_75,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_75 ,interrupt enable for int7"
|
|
group ad:0xF07D0498++0x03
|
|
line.long 0x00 "INT_ENABLE_76,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_76 ,interrupt enable for int7"
|
|
group ad:0xF07D049C++0x03
|
|
line.long 0x00 "INT_ENABLE_77,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_77 ,interrupt enable for int7"
|
|
group ad:0xF07D04A0++0x03
|
|
line.long 0x00 "INT_ENABLE_78,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_78 ,interrupt enable for int7"
|
|
group ad:0xF07D04A4++0x03
|
|
line.long 0x00 "INT_ENABLE_79,interrupt enable for int_7"
|
|
hexmask.long 0x00 0.--31. 1. " INT_ENABLE_79 ,interrupt enable for int7"
|
|
group ad:0xF07D0500++0x03
|
|
line.long 0x00 "TGT_VALUE0,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE0 ,monitor target value"
|
|
group ad:0xF07D0504++0x03
|
|
line.long 0x00 "TGT_VALUE1,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE1 ,monitor target value"
|
|
group ad:0xF07D0508++0x03
|
|
line.long 0x00 "TGT_VALUE2,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE2 ,monitor target value"
|
|
group ad:0xF07D050C++0x03
|
|
line.long 0x00 "TGT_VALUE3,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE3 ,monitor target value"
|
|
group ad:0xF07D0510++0x03
|
|
line.long 0x00 "TGT_VALUE4,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE4 ,monitor target value"
|
|
group ad:0xF07D0514++0x03
|
|
line.long 0x00 "TGT_VALUE5,target value"
|
|
hexmask.long 0x00 0.--31. 1. " TGT_VALUE5 ,monitor target value"
|
|
group ad:0xF07D0580++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE0,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE0 ,monitor enable"
|
|
group ad:0xF07D0584++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE1,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE1 ,monitor enable"
|
|
group ad:0xF07D0588++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE2,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE2 ,monitor enable"
|
|
group ad:0xF07D058C++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE3,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE3 ,monitor enable"
|
|
group ad:0xF07D0590++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE4,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE4 ,monitor enable"
|
|
group ad:0xF07D0594++0x03
|
|
line.long 0x00 "SIG_MON_ENABLE5,signal monitor enable"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_ENABLE5 ,monitor enable"
|
|
group ad:0xF07D0600++0x03
|
|
line.long 0x00 "CORERR_INT_ENABLE_00,corerr interrupt enable int_0"
|
|
hexmask.long 0x00 0.--31. 1. " CORERR_INT_ENABLE_00 ,"
|
|
group ad:0xF07D0680++0x03
|
|
line.long 0x00 "CORERR_INT_ENABLE_10,corerr interrupt enable int_1"
|
|
hexmask.long 0x00 0.--31. 1. " CORERR_INT_ENABLE_10 ,"
|
|
group ad:0xF07D0700++0x03
|
|
line.long 0x00 "CORERR_INT_ENABLE_20,corerr interrupt enable int_2"
|
|
hexmask.long 0x00 0.--31. 1. " CORERR_INT_ENABLE_20 ,"
|
|
group ad:0xF07D0780++0x03
|
|
line.long 0x00 "CORERR_INT_STAT0,"
|
|
hexmask.long 0x00 0.--31. 1. " CORERR_INT_STAT0 ,CORERR Int status"
|
|
group ad:0xF07D0800++0x03
|
|
line.long 0x00 "SIG_MON_STATUS0,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS0 ,signal monitor error status"
|
|
group ad:0xF07D0804++0x03
|
|
line.long 0x00 "SIG_MON_STATUS1,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS1 ,signal monitor error status"
|
|
group ad:0xF07D0808++0x03
|
|
line.long 0x00 "SIG_MON_STATUS2,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS2 ,signal monitor error status"
|
|
group ad:0xF07D080C++0x03
|
|
line.long 0x00 "SIG_MON_STATUS3,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS3 ,signal monitor error status"
|
|
group ad:0xF07D0810++0x03
|
|
line.long 0x00 "SIG_MON_STATUS4,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS4 ,signal monitor error status"
|
|
group ad:0xF07D0814++0x03
|
|
line.long 0x00 "SIG_MON_STATUS5,signal monitor error status"
|
|
hexmask.long 0x00 0.--31. 1. " SIG_MON_STATUS5 ,signal monitor error status"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "SPI"
|
|
tree "SPI1"
|
|
width 27.
|
|
group ad:0xF09F0000++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI contrl register."
|
|
bitfld.long 0x00 31. " SW_RST ,SPI software reset. high active, softare clear." "0,1"
|
|
bitfld.long 0x00 25.--29. " IDLE ,SPI IDLE count value.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " SAMPLE_POINT ,Data sample point. It's useful in Mast mode. 1'b0: input data sampled on SCK edge. 1'b1: input data is sampled on delayed half sck cycle edge." "0,1"
|
|
bitfld.long 0x00 16.--20. " TIMEOUT ,Timeout value for the Data Wait state.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. "NSS_POL ,NSS polarity for 4 seperated NSS Pins. Each NSS_POL bit position corresponds to a NSS pin. 1'b0: NSS is active low. 1'b1: NSS is active high." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " SSP_CLK_MODE ,SSP clock mode select: 0: First dummy clock masked . 1: First dummy clock enable." "0,1"
|
|
bitfld.long 0x00 5. " RX_DMA_EN ,RX DMA enable." "0,1"
|
|
bitfld.long 0x00 4. " TX_DMA_EN ,Tx dma enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SLV_MODE ,SPI master slave mode select: 1'b0: Master mode 1'b1: slave mode." "0,1"
|
|
bitfld.long 0x00 2. " HALF_MODE ,SPI half-duplex mode. 1'b0: full-duplex mode. 1'b1: half-duplex mode." "0,1"
|
|
bitfld.long 0x00 1. " SLV_UNS_SIZE_EN ,The unspecified frame size enable in SPI Slave mode. 1'b0: the frame size = SPI_CMD.FRAM_SIZE in SPI slave mode. 1'b1: the fram size is unspecified in SPI slave mode." "0,1"
|
|
bitfld.long 0x00 0. " MODE ,SPI mode: 1'b0: SPI mode; 1'b1: TI SSP mode;" "0,1"
|
|
group ad:0xF09F0004++0x03
|
|
line.long 0x00 "SPI_TIM_CTRL,SPI Timing control."
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRM_DLY ,Frame delay Defines delay between 2 transition. unit: SCK period. the delay = FRM_DLY + 1;"
|
|
hexmask.long.byte 0x00 8.--15. 1. " END_DLY ,End delay defines from last sck edge to NSS edge delay. the unit is sck period. It's only used in Master mode. the delay = END_DLY+ 1;"
|
|
hexmask.long.byte 0x00 0.--7. 1. " START_DLY ,Start delay defines from NSS edge to first sck edge delay. the units is sck period. It's only used in Master mode. the delay = START_DLY + 1;"
|
|
group ad:0xF09F0008++0x03
|
|
line.long 0x00 "SPI_EN,SPI enable register"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI Enable: 1'b0: DIsable 1'b1: enable." "0,1"
|
|
group ad:0xF09F0010++0x03
|
|
line.long 0x00 "SPI_CMD_CTRL,SPI command control register."
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESSCALE ,CLK Prescaler value : 8'h00: DIvide by 1 8'h01: DIvide by 2 .... 8'hff: DIvide by 256"
|
|
bitfld.long 0x00 23. " TX_MASK ,TX data mask. When set this bit. TX data is maked. In mater mode, this bite will initiate a new transfer. This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: data not mask. 1'b1: Mask TX .." "0,1"
|
|
bitfld.long 0x00 22. " RX_MASK ,RX data mask. When set, the rx data will not be stored in RX FIFO.This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: Not mask. 1'b1: RX data mask." "0,1"
|
|
hexmask.long.word 0x00 12.--21. 1. " FRAM_SIZE ,Frame Size, Unit : Word Size. 10'h0: 1 10'h1: 2 10'h2: 3 10'h3: 4 10'h4: 5 .... 10'h3ff: 1024"
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. "WORD_SIZE ,SPI word size: if BYTE=0: 5'h0-2: Reserved. 5'h3: 4 bit 5'h4: 5 bit .... 5'h1f: 32 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. " SPI_CPHA ,Clock phase: 1'b0: the first clock transition is first data capture edge. 1'b1: the second clock transition is the first data capture edge." "0,1"
|
|
bitfld.long 0x00 5. " SPI_CPOL ,Clock polarity: 1'b0: SCK to 0 when inactive. 1'b1: sck to 1 when inactive." "0,1"
|
|
bitfld.long 0x00 4. " LAST ,This bit inDIcate whether the following data word is last. 1'b0: Not last 1'b1: last." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SWAP ,Tx data byte swap." "0,1"
|
|
bitfld.long 0x00 2. " LSB ,0: TX/RX data is MSB fist. 1: TX/RX data is LSB first." "0,1"
|
|
bitfld.long 0x00 0.--1. " NSS ,SPI slave select config." "0,1,2,3"
|
|
group ad:0xF09F0020++0x03
|
|
line.long 0x00 "SPI_IRQ_MASK,SPI interrupt mask register."
|
|
bitfld.long 0x00 14. " MST_FRM_END ,SPI Master Frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
bitfld.long 0x00 11. " IDLE ,SPI trans IDLE." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "TIMEOUT ,SPI trnas timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag." "0,1"
|
|
bitfld.long 0x00 7. " RX_FIFO_PRE_FULL ,Rx fifo dpt > thrd interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "TX_FIFO_PRE_EMPTY ,Tx fifo dpt < thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
bitfld.long 0x00 3. " RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF09F0024++0x03
|
|
line.long 0x00 "SPI_IRQ_STAT,SPI interrupt status."
|
|
bitfld.long 0x00 28.--31. " SPI_FSM_ST ,SPI FSM state." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " MST_FRM_END ,Master frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IDLE ,SPI Trans IDLE." "0,1"
|
|
bitfld.long 0x00 10. " TIMEOUT ,SPI trans timeout." "0,1"
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|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done. In master mode , when SPI returns to IDLE state with TX FIFO empty, this bit will be set." "0,1"
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|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag. It will be set at the end of each frame transfer" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RX_FIFO_PRE_FULL ,Rx fifo dpt > =thrd interrupt status" "0,1"
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|
bitfld.long 0x00 6. " TX_FIFO_PRE_EMPTY ,Tx fifo dpt =< thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
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|
bitfld.long 0x00 2. " TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
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|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
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|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
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|
group ad:0xF09F0030++0x03
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|
line.long 0x00 "SPI_FIFO_STAT,SPI FIFO status register."
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|
bitfld.long 0x00 25. " RX_FULL ,RX FIFO full." "0,1"
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|
bitfld.long 0x00 24. " RX_EMPTY ,RX FIFO empty." "0,1"
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|
bitfld.long 0x00 16.--20. " RX_FIFO_DPTR ,RX fifo dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 9. " TX_FULL ,TX FIFO FULL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "TX_EMPTY ,TX FIFO empty" "0,1"
|
|
bitfld.long 0x00 0.--4. " TX_FIFO_DPTR ,Tx FIFO dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group ad:0xF09F0034++0x03
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|
line.long 0x00 "SPI_TX_FIFO_CTRL,SPI TX FIFO control register."
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|
bitfld.long 0x00 0.--3. " THRD ,TX FIFO threshold. When FIFO dptr <= thrd, will generate a n TX fifo almost empty interrpt. It also is used to generate tx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group ad:0xF09F0038++0x03
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|
line.long 0x00 "SPI_RX_FIFO_CTRL,SPI RX FIFO control register."
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|
bitfld.long 0x00 0.--3. " THRD ,RX FIFO threshold. When FIFO dptr > thrd , will generate a n RX fifo almost empty interrpt. It also is used to generate rx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group ad:0xF09F0040++0x03
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|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status."
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|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF09F0044++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt mask"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF09F0048++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
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|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,Err_inj_en Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,registrer parity_err_inj Error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF09F004C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_MASK,Function safety uncorrectable error interrupt mask register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete erro" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,ERR_INJ_EN Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,REG_PARITY_ERR_INJ_EN ERROR mask" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF09F0050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
|
|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF09F0054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_MASK,Function safety correctable error interrupt status mask register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
|
|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF09F0058++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF09F005C++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF09F0060++0x03
|
|
line.long 0x00 "PRDATAINJ,inject error to the parity of apb_rdata[31:0]"
|
|
bitfld.long 0x00 0. " DATA_INJ ,inject error to the parity of apb_rdata[31:0]" "0,1"
|
|
group ad:0xF09F0064++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 2. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
|
bitfld.long 0x00 1. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
|
bitfld.long 0x00 0. " FUN_IRQ ,SPI function irq Error injection." "0,1"
|
|
group ad:0xF09F0068++0x03
|
|
line.long 0x00 "DMA_INJ,Error injection on DMA ."
|
|
bitfld.long 0x00 28.--31. " rx_fw_data_inj ,o_dma_rx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " rx_fw_code_inj ,o_dma_rx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " rx_bw_data_inj ,o_dma_rx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " rx_bw_code_inj ,o_dma_rx_bw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "tx_fw_data_inj ,o_dma_tx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " tx_fw_code_inj ,o_dma_tx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " tx_bw_data_inj ,o_dma_tx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " tx_bw_code_inj ,o_dma_tx_bw_code_inj." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF09F0080++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Selftest_mode enable."
|
|
bitfld.long 0x00 0. " en ,Selftest_mode enable." "0,1"
|
|
group ad:0xF09F1000++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CMD,SPI CMD data wirte port."
|
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group ad:0xF09F2000++0x03
|
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line.long 0x00 "SPI_TX_FIFO_DATA,SPI TX Data register.SPI transmitter FIFO data port. The address range from 0x1000-0x1fff(4KB). When writing to this register, you must right-justify the data."
|
|
group ad:0xF09F3000++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_DATA,SPI RX data register.SPI RX FIFO data port. The address range from 0x2000-0x2fff(4KB)."
|
|
tree.end
|
|
tree "SPI2"
|
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width 27.
|
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group ad:0xF0D90000++0x03
|
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line.long 0x00 "SPI_CTRL,SPI contrl register."
|
|
bitfld.long 0x00 31. " SW_RST ,SPI software reset. high active, softare clear." "0,1"
|
|
bitfld.long 0x00 25.--29. " IDLE ,SPI IDLE count value.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " SAMPLE_POINT ,Data sample point. It's useful in Mast mode. 1'b0: input data sampled on SCK edge. 1'b1: input data is sampled on delayed half sck cycle edge." "0,1"
|
|
bitfld.long 0x00 16.--20. " TIMEOUT ,Timeout value for the Data Wait state.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. "NSS_POL ,NSS polarity for 4 seperated NSS Pins. Each NSS_POL bit position corresponds to a NSS pin. 1'b0: NSS is active low. 1'b1: NSS is active high." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " SSP_CLK_MODE ,SSP clock mode select: 0: First dummy clock masked . 1: First dummy clock enable." "0,1"
|
|
bitfld.long 0x00 5. " RX_DMA_EN ,RX DMA enable." "0,1"
|
|
bitfld.long 0x00 4. " TX_DMA_EN ,Tx dma enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SLV_MODE ,SPI master slave mode select: 1'b0: Master mode 1'b1: slave mode." "0,1"
|
|
bitfld.long 0x00 2. " HALF_MODE ,SPI half-duplex mode. 1'b0: full-duplex mode. 1'b1: half-duplex mode." "0,1"
|
|
bitfld.long 0x00 1. " SLV_UNS_SIZE_EN ,The unspecified frame size enable in SPI Slave mode. 1'b0: the frame size = SPI_CMD.FRAM_SIZE in SPI slave mode. 1'b1: the fram size is unspecified in SPI slave mode." "0,1"
|
|
bitfld.long 0x00 0. " MODE ,SPI mode: 1'b0: SPI mode; 1'b1: TI SSP mode;" "0,1"
|
|
group ad:0xF0D90004++0x03
|
|
line.long 0x00 "SPI_TIM_CTRL,SPI Timing control."
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRM_DLY ,Frame delay Defines delay between 2 transition. unit: SCK period. the delay = FRM_DLY + 1;"
|
|
hexmask.long.byte 0x00 8.--15. 1. " END_DLY ,End delay defines from last sck edge to NSS edge delay. the unit is sck period. It's only used in Master mode. the delay = END_DLY+ 1;"
|
|
hexmask.long.byte 0x00 0.--7. 1. " START_DLY ,Start delay defines from NSS edge to first sck edge delay. the units is sck period. It's only used in Master mode. the delay = START_DLY + 1;"
|
|
group ad:0xF0D90008++0x03
|
|
line.long 0x00 "SPI_EN,SPI enable register"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI Enable: 1'b0: DIsable 1'b1: enable." "0,1"
|
|
group ad:0xF0D90010++0x03
|
|
line.long 0x00 "SPI_CMD_CTRL,SPI command control register."
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESSCALE ,CLK Prescaler value : 8'h00: DIvide by 1 8'h01: DIvide by 2 .... 8'hff: DIvide by 256"
|
|
bitfld.long 0x00 23. " TX_MASK ,TX data mask. When set this bit. TX data is maked. In mater mode, this bite will initiate a new transfer. This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: data not mask. 1'b1: Mask TX .." "0,1"
|
|
bitfld.long 0x00 22. " RX_MASK ,RX data mask. When set, the rx data will not be stored in RX FIFO.This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: Not mask. 1'b1: RX data mask." "0,1"
|
|
hexmask.long.word 0x00 12.--21. 1. " FRAM_SIZE ,Frame Size, Unit : Word Size. 10'h0: 1 10'h1: 2 10'h2: 3 10'h3: 4 10'h4: 5 .... 10'h3ff: 1024"
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. "WORD_SIZE ,SPI word size: if BYTE=0: 5'h0-2: Reserved. 5'h3: 4 bit 5'h4: 5 bit .... 5'h1f: 32 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. " SPI_CPHA ,Clock phase: 1'b0: the first clock transition is first data capture edge. 1'b1: the second clock transition is the first data capture edge." "0,1"
|
|
bitfld.long 0x00 5. " SPI_CPOL ,Clock polarity: 1'b0: SCK to 0 when inactive. 1'b1: sck to 1 when inactive." "0,1"
|
|
bitfld.long 0x00 4. " LAST ,This bit inDIcate whether the following data word is last. 1'b0: Not last 1'b1: last." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SWAP ,Tx data byte swap." "0,1"
|
|
bitfld.long 0x00 2. " LSB ,0: TX/RX data is MSB fist. 1: TX/RX data is LSB first." "0,1"
|
|
bitfld.long 0x00 0.--1. " NSS ,SPI slave select config." "0,1,2,3"
|
|
group ad:0xF0D90020++0x03
|
|
line.long 0x00 "SPI_IRQ_MASK,SPI interrupt mask register."
|
|
bitfld.long 0x00 14. " MST_FRM_END ,SPI Master Frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
bitfld.long 0x00 11. " IDLE ,SPI trans IDLE." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "TIMEOUT ,SPI trnas timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag." "0,1"
|
|
bitfld.long 0x00 7. " RX_FIFO_PRE_FULL ,Rx fifo dpt > thrd interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "TX_FIFO_PRE_EMPTY ,Tx fifo dpt < thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
bitfld.long 0x00 3. " RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0D90024++0x03
|
|
line.long 0x00 "SPI_IRQ_STAT,SPI interrupt status."
|
|
bitfld.long 0x00 28.--31. " SPI_FSM_ST ,SPI FSM state." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " MST_FRM_END ,Master frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IDLE ,SPI Trans IDLE." "0,1"
|
|
bitfld.long 0x00 10. " TIMEOUT ,SPI trans timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done. In master mode , when SPI returns to IDLE state with TX FIFO empty, this bit will be set." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag. It will be set at the end of each frame transfer" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RX_FIFO_PRE_FULL ,Rx fifo dpt > =thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 6. " TX_FIFO_PRE_EMPTY ,Tx fifo dpt =< thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 2. " TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0D90030++0x03
|
|
line.long 0x00 "SPI_FIFO_STAT,SPI FIFO status register."
|
|
bitfld.long 0x00 25. " RX_FULL ,RX FIFO full." "0,1"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 16.--20. " RX_FIFO_DPTR ,RX fifo dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 9. " TX_FULL ,TX FIFO FULL" "0,1"
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|
textline " "
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|
bitfld.long 0x00 8. "TX_EMPTY ,TX FIFO empty" "0,1"
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|
bitfld.long 0x00 0.--4. " TX_FIFO_DPTR ,Tx FIFO dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group ad:0xF0D90034++0x03
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line.long 0x00 "SPI_TX_FIFO_CTRL,SPI TX FIFO control register."
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|
bitfld.long 0x00 0.--3. " THRD ,TX FIFO threshold. When FIFO dptr <= thrd, will generate a n TX fifo almost empty interrpt. It also is used to generate tx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0D90038++0x03
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line.long 0x00 "SPI_RX_FIFO_CTRL,SPI RX FIFO control register."
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bitfld.long 0x00 0.--3. " THRD ,RX FIFO threshold. When FIFO dptr > thrd , will generate a n RX fifo almost empty interrpt. It also is used to generate rx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0D90040++0x03
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line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status."
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bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
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group ad:0xF0D90044++0x03
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line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt mask"
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|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
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|
group ad:0xF0D90048++0x03
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line.long 0x00 "FUSA_UNC_ERR_IRQ_STAT,Function safety uncorrectable error interrupt status register"
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bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
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bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete error" "0,1"
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bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
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bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
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textline " "
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bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
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bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
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bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
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bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
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textline " "
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bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,Err_inj_en Error." "0,1"
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bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,registrer parity_err_inj Error." "0,1"
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|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable parity error" "0,1"
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|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
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|
textline " "
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|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
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|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
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|
group ad:0xF0D9004C++0x03
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line.long 0x00 "FUSA_UNC_ERR_IRQ_MASK,Function safety uncorrectable error interrupt mask register"
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bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
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|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete erro" "0,1"
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|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
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bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
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|
textline " "
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bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
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|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
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|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
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|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
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|
textline " "
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bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,ERR_INJ_EN Error." "0,1"
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bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,REG_PARITY_ERR_INJ_EN ERROR mask" "0,1"
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|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
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|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
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|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
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|
group ad:0xF0D90050++0x03
|
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line.long 0x00 "FUSA_COR_ERR_IRQ_STAT,Function safety correctable error interrupt status register"
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|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
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|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
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|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
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|
group ad:0xF0D90054++0x03
|
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line.long 0x00 "FUSA_COR_ERR_IRQ_MASK,Function safety correctable error interrupt status mask register"
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bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
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bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
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|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
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|
group ad:0xF0D90058++0x03
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|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
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hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
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group ad:0xF0D9005C++0x03
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line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
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|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
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group ad:0xF0D90060++0x03
|
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line.long 0x00 "PRDATAINJ,inject error to the parity of apb_rdata[31:0]"
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bitfld.long 0x00 0. " DATA_INJ ,inject error to the parity of apb_rdata[31:0]" "0,1"
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group ad:0xF0D90064++0x03
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line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
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bitfld.long 0x00 2. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
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bitfld.long 0x00 1. " COR_ERR ,Correctable error interrupt error injection." "0,1"
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|
bitfld.long 0x00 0. " FUN_IRQ ,SPI function irq Error injection." "0,1"
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group ad:0xF0D90068++0x03
|
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line.long 0x00 "DMA_INJ,Error injection on DMA ."
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bitfld.long 0x00 28.--31. " rx_fw_data_inj ,o_dma_rx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 24.--27. " rx_fw_code_inj ,o_dma_rx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. " rx_bw_data_inj ,o_dma_rx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. " rx_bw_code_inj ,o_dma_rx_bw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "tx_fw_data_inj ,o_dma_tx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " tx_fw_code_inj ,o_dma_tx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " tx_bw_data_inj ,o_dma_tx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " tx_bw_code_inj ,o_dma_tx_bw_code_inj." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0D90080++0x03
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line.long 0x00 "SELFTEST_MODE,Selftest_mode enable."
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bitfld.long 0x00 0. " en ,Selftest_mode enable." "0,1"
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group ad:0xF0D91000++0x03
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line.long 0x00 "SPI_TX_FIFO_CMD,SPI CMD data wirte port."
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group ad:0xF0D92000++0x03
|
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line.long 0x00 "SPI_TX_FIFO_DATA,SPI TX Data register.SPI transmitter FIFO data port. The address range from 0x1000-0x1fff(4KB). When writing to this register, you must right-justify the data."
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group ad:0xF0D93000++0x03
|
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line.long 0x00 "SPI_RX_FIFO_DATA,SPI RX data register.SPI RX FIFO data port. The address range from 0x2000-0x2fff(4KB)."
|
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tree.end
|
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tree "SPI3"
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width 27.
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group ad:0xF0A00000++0x03
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line.long 0x00 "SPI_CTRL,SPI contrl register."
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bitfld.long 0x00 31. " SW_RST ,SPI software reset. high active, softare clear." "0,1"
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bitfld.long 0x00 25.--29. " IDLE ,SPI IDLE count value.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. " SAMPLE_POINT ,Data sample point. It's useful in Mast mode. 1'b0: input data sampled on SCK edge. 1'b1: input data is sampled on delayed half sck cycle edge." "0,1"
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bitfld.long 0x00 16.--20. " TIMEOUT ,Timeout value for the Data Wait state.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. "NSS_POL ,NSS polarity for 4 seperated NSS Pins. Each NSS_POL bit position corresponds to a NSS pin. 1'b0: NSS is active low. 1'b1: NSS is active high." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6. " SSP_CLK_MODE ,SSP clock mode select: 0: First dummy clock masked . 1: First dummy clock enable." "0,1"
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bitfld.long 0x00 5. " RX_DMA_EN ,RX DMA enable." "0,1"
|
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bitfld.long 0x00 4. " TX_DMA_EN ,Tx dma enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SLV_MODE ,SPI master slave mode select: 1'b0: Master mode 1'b1: slave mode." "0,1"
|
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bitfld.long 0x00 2. " HALF_MODE ,SPI half-duplex mode. 1'b0: full-duplex mode. 1'b1: half-duplex mode." "0,1"
|
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bitfld.long 0x00 1. " SLV_UNS_SIZE_EN ,The unspecified frame size enable in SPI Slave mode. 1'b0: the frame size = SPI_CMD.FRAM_SIZE in SPI slave mode. 1'b1: the fram size is unspecified in SPI slave mode." "0,1"
|
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bitfld.long 0x00 0. " MODE ,SPI mode: 1'b0: SPI mode; 1'b1: TI SSP mode;" "0,1"
|
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group ad:0xF0A00004++0x03
|
|
line.long 0x00 "SPI_TIM_CTRL,SPI Timing control."
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRM_DLY ,Frame delay Defines delay between 2 transition. unit: SCK period. the delay = FRM_DLY + 1;"
|
|
hexmask.long.byte 0x00 8.--15. 1. " END_DLY ,End delay defines from last sck edge to NSS edge delay. the unit is sck period. It's only used in Master mode. the delay = END_DLY+ 1;"
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hexmask.long.byte 0x00 0.--7. 1. " START_DLY ,Start delay defines from NSS edge to first sck edge delay. the units is sck period. It's only used in Master mode. the delay = START_DLY + 1;"
|
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group ad:0xF0A00008++0x03
|
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line.long 0x00 "SPI_EN,SPI enable register"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI Enable: 1'b0: DIsable 1'b1: enable." "0,1"
|
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group ad:0xF0A00010++0x03
|
|
line.long 0x00 "SPI_CMD_CTRL,SPI command control register."
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESSCALE ,CLK Prescaler value : 8'h00: DIvide by 1 8'h01: DIvide by 2 .... 8'hff: DIvide by 256"
|
|
bitfld.long 0x00 23. " TX_MASK ,TX data mask. When set this bit. TX data is maked. In mater mode, this bite will initiate a new transfer. This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: data not mask. 1'b1: Mask TX .." "0,1"
|
|
bitfld.long 0x00 22. " RX_MASK ,RX data mask. When set, the rx data will not be stored in RX FIFO.This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: Not mask. 1'b1: RX data mask." "0,1"
|
|
hexmask.long.word 0x00 12.--21. 1. " FRAM_SIZE ,Frame Size, Unit : Word Size. 10'h0: 1 10'h1: 2 10'h2: 3 10'h3: 4 10'h4: 5 .... 10'h3ff: 1024"
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. "WORD_SIZE ,SPI word size: if BYTE=0: 5'h0-2: Reserved. 5'h3: 4 bit 5'h4: 5 bit .... 5'h1f: 32 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. " SPI_CPHA ,Clock phase: 1'b0: the first clock transition is first data capture edge. 1'b1: the second clock transition is the first data capture edge." "0,1"
|
|
bitfld.long 0x00 5. " SPI_CPOL ,Clock polarity: 1'b0: SCK to 0 when inactive. 1'b1: sck to 1 when inactive." "0,1"
|
|
bitfld.long 0x00 4. " LAST ,This bit inDIcate whether the following data word is last. 1'b0: Not last 1'b1: last." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SWAP ,Tx data byte swap." "0,1"
|
|
bitfld.long 0x00 2. " LSB ,0: TX/RX data is MSB fist. 1: TX/RX data is LSB first." "0,1"
|
|
bitfld.long 0x00 0.--1. " NSS ,SPI slave select config." "0,1,2,3"
|
|
group ad:0xF0A00020++0x03
|
|
line.long 0x00 "SPI_IRQ_MASK,SPI interrupt mask register."
|
|
bitfld.long 0x00 14. " MST_FRM_END ,SPI Master Frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
bitfld.long 0x00 11. " IDLE ,SPI trans IDLE." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "TIMEOUT ,SPI trnas timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag." "0,1"
|
|
bitfld.long 0x00 7. " RX_FIFO_PRE_FULL ,Rx fifo dpt > thrd interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "TX_FIFO_PRE_EMPTY ,Tx fifo dpt < thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
bitfld.long 0x00 3. " RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0A00024++0x03
|
|
line.long 0x00 "SPI_IRQ_STAT,SPI interrupt status."
|
|
bitfld.long 0x00 28.--31. " SPI_FSM_ST ,SPI FSM state." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " MST_FRM_END ,Master frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IDLE ,SPI Trans IDLE." "0,1"
|
|
bitfld.long 0x00 10. " TIMEOUT ,SPI trans timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done. In master mode , when SPI returns to IDLE state with TX FIFO empty, this bit will be set." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag. It will be set at the end of each frame transfer" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RX_FIFO_PRE_FULL ,Rx fifo dpt > =thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 6. " TX_FIFO_PRE_EMPTY ,Tx fifo dpt =< thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 2. " TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0A00030++0x03
|
|
line.long 0x00 "SPI_FIFO_STAT,SPI FIFO status register."
|
|
bitfld.long 0x00 25. " RX_FULL ,RX FIFO full." "0,1"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 16.--20. " RX_FIFO_DPTR ,RX fifo dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " TX_FULL ,TX FIFO FULL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "TX_EMPTY ,TX FIFO empty" "0,1"
|
|
bitfld.long 0x00 0.--4. " TX_FIFO_DPTR ,Tx FIFO dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0A00034++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CTRL,SPI TX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,TX FIFO threshold. When FIFO dptr <= thrd, will generate a n TX fifo almost empty interrpt. It also is used to generate tx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0A00038++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_CTRL,SPI RX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,RX FIFO threshold. When FIFO dptr > thrd , will generate a n RX fifo almost empty interrpt. It also is used to generate rx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0A00040++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status."
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|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
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|
group ad:0xF0A00044++0x03
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|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt mask"
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|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
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|
group ad:0xF0A00048++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_STAT,Function safety uncorrectable error interrupt status register"
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|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
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|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete error" "0,1"
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|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
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|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
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|
textline " "
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|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
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|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
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|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
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|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
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|
textline " "
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|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,Err_inj_en Error." "0,1"
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|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,registrer parity_err_inj Error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable parity error" "0,1"
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|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
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|
textline " "
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|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
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|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
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|
group ad:0xF0A0004C++0x03
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|
line.long 0x00 "FUSA_UNC_ERR_IRQ_MASK,Function safety uncorrectable error interrupt mask register"
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|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
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|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete erro" "0,1"
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|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
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|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
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|
textline " "
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bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
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|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
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|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
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|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
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|
textline " "
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bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,ERR_INJ_EN Error." "0,1"
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|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,REG_PARITY_ERR_INJ_EN ERROR mask" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
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|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
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|
textline " "
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|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
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|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
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|
group ad:0xF0A00050++0x03
|
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line.long 0x00 "FUSA_COR_ERR_IRQ_STAT,Function safety correctable error interrupt status register"
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|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
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|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
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|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
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|
group ad:0xF0A00054++0x03
|
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line.long 0x00 "FUSA_COR_ERR_IRQ_MASK,Function safety correctable error interrupt status mask register"
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bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
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bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
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|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
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|
group ad:0xF0A00058++0x03
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|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
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|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
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|
group ad:0xF0A0005C++0x03
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line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
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|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
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|
group ad:0xF0A00060++0x03
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line.long 0x00 "PRDATAINJ,inject error to the parity of apb_rdata[31:0]"
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|
bitfld.long 0x00 0. " DATA_INJ ,inject error to the parity of apb_rdata[31:0]" "0,1"
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|
group ad:0xF0A00064++0x03
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line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
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bitfld.long 0x00 2. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
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bitfld.long 0x00 1. " COR_ERR ,Correctable error interrupt error injection." "0,1"
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|
bitfld.long 0x00 0. " FUN_IRQ ,SPI function irq Error injection." "0,1"
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group ad:0xF0A00068++0x03
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line.long 0x00 "DMA_INJ,Error injection on DMA ."
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|
bitfld.long 0x00 28.--31. " rx_fw_data_inj ,o_dma_rx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 24.--27. " rx_fw_code_inj ,o_dma_rx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. " rx_bw_data_inj ,o_dma_rx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. " rx_bw_code_inj ,o_dma_rx_bw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "tx_fw_data_inj ,o_dma_tx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. " tx_fw_code_inj ,o_dma_tx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. " tx_bw_data_inj ,o_dma_tx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " tx_bw_code_inj ,o_dma_tx_bw_code_inj." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group ad:0xF0A00080++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Selftest_mode enable."
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bitfld.long 0x00 0. " en ,Selftest_mode enable." "0,1"
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|
group ad:0xF0A01000++0x03
|
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line.long 0x00 "SPI_TX_FIFO_CMD,SPI CMD data wirte port."
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group ad:0xF0A02000++0x03
|
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line.long 0x00 "SPI_TX_FIFO_DATA,SPI TX Data register.SPI transmitter FIFO data port. The address range from 0x1000-0x1fff(4KB). When writing to this register, you must right-justify the data."
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group ad:0xF0A03000++0x03
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|
line.long 0x00 "SPI_RX_FIFO_DATA,SPI RX data register.SPI RX FIFO data port. The address range from 0x2000-0x2fff(4KB)."
|
|
tree.end
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|
tree "SPI4"
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width 27.
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group ad:0xF0DA0000++0x03
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line.long 0x00 "SPI_CTRL,SPI contrl register."
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bitfld.long 0x00 31. " SW_RST ,SPI software reset. high active, softare clear." "0,1"
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bitfld.long 0x00 25.--29. " IDLE ,SPI IDLE count value.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. " SAMPLE_POINT ,Data sample point. It's useful in Mast mode. 1'b0: input data sampled on SCK edge. 1'b1: input data is sampled on delayed half sck cycle edge." "0,1"
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bitfld.long 0x00 16.--20. " TIMEOUT ,Timeout value for the Data Wait state.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
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bitfld.long 0x00 8.--11. "NSS_POL ,NSS polarity for 4 seperated NSS Pins. Each NSS_POL bit position corresponds to a NSS pin. 1'b0: NSS is active low. 1'b1: NSS is active high." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6. " SSP_CLK_MODE ,SSP clock mode select: 0: First dummy clock masked . 1: First dummy clock enable." "0,1"
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bitfld.long 0x00 5. " RX_DMA_EN ,RX DMA enable." "0,1"
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bitfld.long 0x00 4. " TX_DMA_EN ,Tx dma enable." "0,1"
|
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textline " "
|
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bitfld.long 0x00 3. "SLV_MODE ,SPI master slave mode select: 1'b0: Master mode 1'b1: slave mode." "0,1"
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bitfld.long 0x00 2. " HALF_MODE ,SPI half-duplex mode. 1'b0: full-duplex mode. 1'b1: half-duplex mode." "0,1"
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bitfld.long 0x00 1. " SLV_UNS_SIZE_EN ,The unspecified frame size enable in SPI Slave mode. 1'b0: the frame size = SPI_CMD.FRAM_SIZE in SPI slave mode. 1'b1: the fram size is unspecified in SPI slave mode." "0,1"
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bitfld.long 0x00 0. " MODE ,SPI mode: 1'b0: SPI mode; 1'b1: TI SSP mode;" "0,1"
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group ad:0xF0DA0004++0x03
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line.long 0x00 "SPI_TIM_CTRL,SPI Timing control."
|
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hexmask.long.byte 0x00 16.--23. 1. " FRM_DLY ,Frame delay Defines delay between 2 transition. unit: SCK period. the delay = FRM_DLY + 1;"
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hexmask.long.byte 0x00 8.--15. 1. " END_DLY ,End delay defines from last sck edge to NSS edge delay. the unit is sck period. It's only used in Master mode. the delay = END_DLY+ 1;"
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hexmask.long.byte 0x00 0.--7. 1. " START_DLY ,Start delay defines from NSS edge to first sck edge delay. the units is sck period. It's only used in Master mode. the delay = START_DLY + 1;"
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group ad:0xF0DA0008++0x03
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line.long 0x00 "SPI_EN,SPI enable register"
|
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bitfld.long 0x00 0. " ENABLE ,SPI Enable: 1'b0: DIsable 1'b1: enable." "0,1"
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group ad:0xF0DA0010++0x03
|
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line.long 0x00 "SPI_CMD_CTRL,SPI command control register."
|
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hexmask.long.byte 0x00 24.--31. 1. " PRESSCALE ,CLK Prescaler value : 8'h00: DIvide by 1 8'h01: DIvide by 2 .... 8'hff: DIvide by 256"
|
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bitfld.long 0x00 23. " TX_MASK ,TX data mask. When set this bit. TX data is maked. In mater mode, this bite will initiate a new transfer. This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: data not mask. 1'b1: Mask TX .." "0,1"
|
|
bitfld.long 0x00 22. " RX_MASK ,RX data mask. When set, the rx data will not be stored in RX FIFO.This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: Not mask. 1'b1: RX data mask." "0,1"
|
|
hexmask.long.word 0x00 12.--21. 1. " FRAM_SIZE ,Frame Size, Unit : Word Size. 10'h0: 1 10'h1: 2 10'h2: 3 10'h3: 4 10'h4: 5 .... 10'h3ff: 1024"
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. "WORD_SIZE ,SPI word size: if BYTE=0: 5'h0-2: Reserved. 5'h3: 4 bit 5'h4: 5 bit .... 5'h1f: 32 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. " SPI_CPHA ,Clock phase: 1'b0: the first clock transition is first data capture edge. 1'b1: the second clock transition is the first data capture edge." "0,1"
|
|
bitfld.long 0x00 5. " SPI_CPOL ,Clock polarity: 1'b0: SCK to 0 when inactive. 1'b1: sck to 1 when inactive." "0,1"
|
|
bitfld.long 0x00 4. " LAST ,This bit inDIcate whether the following data word is last. 1'b0: Not last 1'b1: last." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SWAP ,Tx data byte swap." "0,1"
|
|
bitfld.long 0x00 2. " LSB ,0: TX/RX data is MSB fist. 1: TX/RX data is LSB first." "0,1"
|
|
bitfld.long 0x00 0.--1. " NSS ,SPI slave select config." "0,1,2,3"
|
|
group ad:0xF0DA0020++0x03
|
|
line.long 0x00 "SPI_IRQ_MASK,SPI interrupt mask register."
|
|
bitfld.long 0x00 14. " MST_FRM_END ,SPI Master Frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
bitfld.long 0x00 11. " IDLE ,SPI trans IDLE." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "TIMEOUT ,SPI trnas timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag." "0,1"
|
|
bitfld.long 0x00 7. " RX_FIFO_PRE_FULL ,Rx fifo dpt > thrd interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "TX_FIFO_PRE_EMPTY ,Tx fifo dpt < thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
bitfld.long 0x00 3. " RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0DA0024++0x03
|
|
line.long 0x00 "SPI_IRQ_STAT,SPI interrupt status."
|
|
bitfld.long 0x00 28.--31. " SPI_FSM_ST ,SPI FSM state." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " MST_FRM_END ,Master frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IDLE ,SPI Trans IDLE." "0,1"
|
|
bitfld.long 0x00 10. " TIMEOUT ,SPI trans timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done. In master mode , when SPI returns to IDLE state with TX FIFO empty, this bit will be set." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag. It will be set at the end of each frame transfer" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RX_FIFO_PRE_FULL ,Rx fifo dpt > =thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 6. " TX_FIFO_PRE_EMPTY ,Tx fifo dpt =< thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 2. " TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0DA0030++0x03
|
|
line.long 0x00 "SPI_FIFO_STAT,SPI FIFO status register."
|
|
bitfld.long 0x00 25. " RX_FULL ,RX FIFO full." "0,1"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 16.--20. " RX_FIFO_DPTR ,RX fifo dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " TX_FULL ,TX FIFO FULL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "TX_EMPTY ,TX FIFO empty" "0,1"
|
|
bitfld.long 0x00 0.--4. " TX_FIFO_DPTR ,Tx FIFO dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0DA0034++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CTRL,SPI TX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,TX FIFO threshold. When FIFO dptr <= thrd, will generate a n TX fifo almost empty interrpt. It also is used to generate tx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0DA0038++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_CTRL,SPI RX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,RX FIFO threshold. When FIFO dptr > thrd , will generate a n RX fifo almost empty interrpt. It also is used to generate rx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0DA0040++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0DA0044++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt mask"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF0DA0048++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,Err_inj_en Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,registrer parity_err_inj Error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0DA004C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_MASK,Function safety uncorrectable error interrupt mask register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete erro" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,ERR_INJ_EN Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,REG_PARITY_ERR_INJ_EN ERROR mask" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0DA0050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
|
|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0DA0054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_MASK,Function safety correctable error interrupt status mask register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
|
|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0DA0058++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF0DA005C++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF0DA0060++0x03
|
|
line.long 0x00 "PRDATAINJ,inject error to the parity of apb_rdata[31:0]"
|
|
bitfld.long 0x00 0. " DATA_INJ ,inject error to the parity of apb_rdata[31:0]" "0,1"
|
|
group ad:0xF0DA0064++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 2. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
|
bitfld.long 0x00 1. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
|
bitfld.long 0x00 0. " FUN_IRQ ,SPI function irq Error injection." "0,1"
|
|
group ad:0xF0DA0068++0x03
|
|
line.long 0x00 "DMA_INJ,Error injection on DMA ."
|
|
bitfld.long 0x00 28.--31. " rx_fw_data_inj ,o_dma_rx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " rx_fw_code_inj ,o_dma_rx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " rx_bw_data_inj ,o_dma_rx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " rx_bw_code_inj ,o_dma_rx_bw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "tx_fw_data_inj ,o_dma_tx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " tx_fw_code_inj ,o_dma_tx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " tx_bw_data_inj ,o_dma_tx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " tx_bw_code_inj ,o_dma_tx_bw_code_inj." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0DA0080++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Selftest_mode enable."
|
|
bitfld.long 0x00 0. " en ,Selftest_mode enable." "0,1"
|
|
group ad:0xF0DA1000++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CMD,SPI CMD data wirte port."
|
|
group ad:0xF0DA2000++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_DATA,SPI TX Data register.SPI transmitter FIFO data port. The address range from 0x1000-0x1fff(4KB). When writing to this register, you must right-justify the data."
|
|
group ad:0xF0DA3000++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_DATA,SPI RX data register.SPI RX FIFO data port. The address range from 0x2000-0x2fff(4KB)."
|
|
tree.end
|
|
tree "SPI5"
|
|
width 27.
|
|
group ad:0xF0A10000++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI contrl register."
|
|
bitfld.long 0x00 31. " SW_RST ,SPI software reset. high active, softare clear." "0,1"
|
|
bitfld.long 0x00 25.--29. " IDLE ,SPI IDLE count value.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " SAMPLE_POINT ,Data sample point. It's useful in Mast mode. 1'b0: input data sampled on SCK edge. 1'b1: input data is sampled on delayed half sck cycle edge." "0,1"
|
|
bitfld.long 0x00 16.--20. " TIMEOUT ,Timeout value for the Data Wait state.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. "NSS_POL ,NSS polarity for 4 seperated NSS Pins. Each NSS_POL bit position corresponds to a NSS pin. 1'b0: NSS is active low. 1'b1: NSS is active high." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " SSP_CLK_MODE ,SSP clock mode select: 0: First dummy clock masked . 1: First dummy clock enable." "0,1"
|
|
bitfld.long 0x00 5. " RX_DMA_EN ,RX DMA enable." "0,1"
|
|
bitfld.long 0x00 4. " TX_DMA_EN ,Tx dma enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SLV_MODE ,SPI master slave mode select: 1'b0: Master mode 1'b1: slave mode." "0,1"
|
|
bitfld.long 0x00 2. " HALF_MODE ,SPI half-duplex mode. 1'b0: full-duplex mode. 1'b1: half-duplex mode." "0,1"
|
|
bitfld.long 0x00 1. " SLV_UNS_SIZE_EN ,The unspecified frame size enable in SPI Slave mode. 1'b0: the frame size = SPI_CMD.FRAM_SIZE in SPI slave mode. 1'b1: the fram size is unspecified in SPI slave mode." "0,1"
|
|
bitfld.long 0x00 0. " MODE ,SPI mode: 1'b0: SPI mode; 1'b1: TI SSP mode;" "0,1"
|
|
group ad:0xF0A10004++0x03
|
|
line.long 0x00 "SPI_TIM_CTRL,SPI Timing control."
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRM_DLY ,Frame delay Defines delay between 2 transition. unit: SCK period. the delay = FRM_DLY + 1;"
|
|
hexmask.long.byte 0x00 8.--15. 1. " END_DLY ,End delay defines from last sck edge to NSS edge delay. the unit is sck period. It's only used in Master mode. the delay = END_DLY+ 1;"
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hexmask.long.byte 0x00 0.--7. 1. " START_DLY ,Start delay defines from NSS edge to first sck edge delay. the units is sck period. It's only used in Master mode. the delay = START_DLY + 1;"
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|
group ad:0xF0A10008++0x03
|
|
line.long 0x00 "SPI_EN,SPI enable register"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI Enable: 1'b0: DIsable 1'b1: enable." "0,1"
|
|
group ad:0xF0A10010++0x03
|
|
line.long 0x00 "SPI_CMD_CTRL,SPI command control register."
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESSCALE ,CLK Prescaler value : 8'h00: DIvide by 1 8'h01: DIvide by 2 .... 8'hff: DIvide by 256"
|
|
bitfld.long 0x00 23. " TX_MASK ,TX data mask. When set this bit. TX data is maked. In mater mode, this bite will initiate a new transfer. This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: data not mask. 1'b1: Mask TX .." "0,1"
|
|
bitfld.long 0x00 22. " RX_MASK ,RX data mask. When set, the rx data will not be stored in RX FIFO.This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: Not mask. 1'b1: RX data mask." "0,1"
|
|
hexmask.long.word 0x00 12.--21. 1. " FRAM_SIZE ,Frame Size, Unit : Word Size. 10'h0: 1 10'h1: 2 10'h2: 3 10'h3: 4 10'h4: 5 .... 10'h3ff: 1024"
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. "WORD_SIZE ,SPI word size: if BYTE=0: 5'h0-2: Reserved. 5'h3: 4 bit 5'h4: 5 bit .... 5'h1f: 32 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. " SPI_CPHA ,Clock phase: 1'b0: the first clock transition is first data capture edge. 1'b1: the second clock transition is the first data capture edge." "0,1"
|
|
bitfld.long 0x00 5. " SPI_CPOL ,Clock polarity: 1'b0: SCK to 0 when inactive. 1'b1: sck to 1 when inactive." "0,1"
|
|
bitfld.long 0x00 4. " LAST ,This bit inDIcate whether the following data word is last. 1'b0: Not last 1'b1: last." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SWAP ,Tx data byte swap." "0,1"
|
|
bitfld.long 0x00 2. " LSB ,0: TX/RX data is MSB fist. 1: TX/RX data is LSB first." "0,1"
|
|
bitfld.long 0x00 0.--1. " NSS ,SPI slave select config." "0,1,2,3"
|
|
group ad:0xF0A10020++0x03
|
|
line.long 0x00 "SPI_IRQ_MASK,SPI interrupt mask register."
|
|
bitfld.long 0x00 14. " MST_FRM_END ,SPI Master Frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
bitfld.long 0x00 11. " IDLE ,SPI trans IDLE." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "TIMEOUT ,SPI trnas timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag." "0,1"
|
|
bitfld.long 0x00 7. " RX_FIFO_PRE_FULL ,Rx fifo dpt > thrd interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "TX_FIFO_PRE_EMPTY ,Tx fifo dpt < thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
bitfld.long 0x00 3. " RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0A10024++0x03
|
|
line.long 0x00 "SPI_IRQ_STAT,SPI interrupt status."
|
|
bitfld.long 0x00 28.--31. " SPI_FSM_ST ,SPI FSM state." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " MST_FRM_END ,Master frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IDLE ,SPI Trans IDLE." "0,1"
|
|
bitfld.long 0x00 10. " TIMEOUT ,SPI trans timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done. In master mode , when SPI returns to IDLE state with TX FIFO empty, this bit will be set." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag. It will be set at the end of each frame transfer" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RX_FIFO_PRE_FULL ,Rx fifo dpt > =thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 6. " TX_FIFO_PRE_EMPTY ,Tx fifo dpt =< thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 2. " TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0A10030++0x03
|
|
line.long 0x00 "SPI_FIFO_STAT,SPI FIFO status register."
|
|
bitfld.long 0x00 25. " RX_FULL ,RX FIFO full." "0,1"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 16.--20. " RX_FIFO_DPTR ,RX fifo dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " TX_FULL ,TX FIFO FULL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "TX_EMPTY ,TX FIFO empty" "0,1"
|
|
bitfld.long 0x00 0.--4. " TX_FIFO_DPTR ,Tx FIFO dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0A10034++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CTRL,SPI TX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,TX FIFO threshold. When FIFO dptr <= thrd, will generate a n TX fifo almost empty interrpt. It also is used to generate tx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0A10038++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_CTRL,SPI RX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,RX FIFO threshold. When FIFO dptr > thrd , will generate a n RX fifo almost empty interrpt. It also is used to generate rx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0A10040++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0A10044++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt mask"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF0A10048++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,Err_inj_en Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,registrer parity_err_inj Error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0A1004C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_MASK,Function safety uncorrectable error interrupt mask register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete erro" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,ERR_INJ_EN Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,REG_PARITY_ERR_INJ_EN ERROR mask" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0A10050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
|
|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
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|
group ad:0xF0A10054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_MASK,Function safety correctable error interrupt status mask register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
|
|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
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|
group ad:0xF0A10058++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
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|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF0A1005C++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF0A10060++0x03
|
|
line.long 0x00 "PRDATAINJ,inject error to the parity of apb_rdata[31:0]"
|
|
bitfld.long 0x00 0. " DATA_INJ ,inject error to the parity of apb_rdata[31:0]" "0,1"
|
|
group ad:0xF0A10064++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 2. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
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|
bitfld.long 0x00 1. " COR_ERR ,Correctable error interrupt error injection." "0,1"
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|
bitfld.long 0x00 0. " FUN_IRQ ,SPI function irq Error injection." "0,1"
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|
group ad:0xF0A10068++0x03
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|
line.long 0x00 "DMA_INJ,Error injection on DMA ."
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|
bitfld.long 0x00 28.--31. " rx_fw_data_inj ,o_dma_rx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 24.--27. " rx_fw_code_inj ,o_dma_rx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 20.--23. " rx_bw_data_inj ,o_dma_rx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. " rx_bw_code_inj ,o_dma_rx_bw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "tx_fw_data_inj ,o_dma_tx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. " tx_fw_code_inj ,o_dma_tx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. " tx_bw_data_inj ,o_dma_tx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " tx_bw_code_inj ,o_dma_tx_bw_code_inj." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group ad:0xF0A10080++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Selftest_mode enable."
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|
bitfld.long 0x00 0. " en ,Selftest_mode enable." "0,1"
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|
group ad:0xF0A11000++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CMD,SPI CMD data wirte port."
|
|
group ad:0xF0A12000++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_DATA,SPI TX Data register.SPI transmitter FIFO data port. The address range from 0x1000-0x1fff(4KB). When writing to this register, you must right-justify the data."
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|
group ad:0xF0A13000++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_DATA,SPI RX data register.SPI RX FIFO data port. The address range from 0x2000-0x2fff(4KB)."
|
|
tree.end
|
|
tree "SPI6"
|
|
width 27.
|
|
group ad:0xF0DB0000++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI contrl register."
|
|
bitfld.long 0x00 31. " SW_RST ,SPI software reset. high active, softare clear." "0,1"
|
|
bitfld.long 0x00 25.--29. " IDLE ,SPI IDLE count value.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 24. " SAMPLE_POINT ,Data sample point. It's useful in Mast mode. 1'b0: input data sampled on SCK edge. 1'b1: input data is sampled on delayed half sck cycle edge." "0,1"
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|
bitfld.long 0x00 16.--20. " TIMEOUT ,Timeout value for the Data Wait state.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. "NSS_POL ,NSS polarity for 4 seperated NSS Pins. Each NSS_POL bit position corresponds to a NSS pin. 1'b0: NSS is active low. 1'b1: NSS is active high." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 6. " SSP_CLK_MODE ,SSP clock mode select: 0: First dummy clock masked . 1: First dummy clock enable." "0,1"
|
|
bitfld.long 0x00 5. " RX_DMA_EN ,RX DMA enable." "0,1"
|
|
bitfld.long 0x00 4. " TX_DMA_EN ,Tx dma enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SLV_MODE ,SPI master slave mode select: 1'b0: Master mode 1'b1: slave mode." "0,1"
|
|
bitfld.long 0x00 2. " HALF_MODE ,SPI half-duplex mode. 1'b0: full-duplex mode. 1'b1: half-duplex mode." "0,1"
|
|
bitfld.long 0x00 1. " SLV_UNS_SIZE_EN ,The unspecified frame size enable in SPI Slave mode. 1'b0: the frame size = SPI_CMD.FRAM_SIZE in SPI slave mode. 1'b1: the fram size is unspecified in SPI slave mode." "0,1"
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|
bitfld.long 0x00 0. " MODE ,SPI mode: 1'b0: SPI mode; 1'b1: TI SSP mode;" "0,1"
|
|
group ad:0xF0DB0004++0x03
|
|
line.long 0x00 "SPI_TIM_CTRL,SPI Timing control."
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRM_DLY ,Frame delay Defines delay between 2 transition. unit: SCK period. the delay = FRM_DLY + 1;"
|
|
hexmask.long.byte 0x00 8.--15. 1. " END_DLY ,End delay defines from last sck edge to NSS edge delay. the unit is sck period. It's only used in Master mode. the delay = END_DLY+ 1;"
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|
hexmask.long.byte 0x00 0.--7. 1. " START_DLY ,Start delay defines from NSS edge to first sck edge delay. the units is sck period. It's only used in Master mode. the delay = START_DLY + 1;"
|
|
group ad:0xF0DB0008++0x03
|
|
line.long 0x00 "SPI_EN,SPI enable register"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI Enable: 1'b0: DIsable 1'b1: enable." "0,1"
|
|
group ad:0xF0DB0010++0x03
|
|
line.long 0x00 "SPI_CMD_CTRL,SPI command control register."
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESSCALE ,CLK Prescaler value : 8'h00: DIvide by 1 8'h01: DIvide by 2 .... 8'hff: DIvide by 256"
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|
bitfld.long 0x00 23. " TX_MASK ,TX data mask. When set this bit. TX data is maked. In mater mode, this bite will initiate a new transfer. This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: data not mask. 1'b1: Mask TX .." "0,1"
|
|
bitfld.long 0x00 22. " RX_MASK ,RX data mask. When set, the rx data will not be stored in RX FIFO.This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: Not mask. 1'b1: RX data mask." "0,1"
|
|
hexmask.long.word 0x00 12.--21. 1. " FRAM_SIZE ,Frame Size, Unit : Word Size. 10'h0: 1 10'h1: 2 10'h2: 3 10'h3: 4 10'h4: 5 .... 10'h3ff: 1024"
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. "WORD_SIZE ,SPI word size: if BYTE=0: 5'h0-2: Reserved. 5'h3: 4 bit 5'h4: 5 bit .... 5'h1f: 32 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 6. " SPI_CPHA ,Clock phase: 1'b0: the first clock transition is first data capture edge. 1'b1: the second clock transition is the first data capture edge." "0,1"
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|
bitfld.long 0x00 5. " SPI_CPOL ,Clock polarity: 1'b0: SCK to 0 when inactive. 1'b1: sck to 1 when inactive." "0,1"
|
|
bitfld.long 0x00 4. " LAST ,This bit inDIcate whether the following data word is last. 1'b0: Not last 1'b1: last." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SWAP ,Tx data byte swap." "0,1"
|
|
bitfld.long 0x00 2. " LSB ,0: TX/RX data is MSB fist. 1: TX/RX data is LSB first." "0,1"
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|
bitfld.long 0x00 0.--1. " NSS ,SPI slave select config." "0,1,2,3"
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|
group ad:0xF0DB0020++0x03
|
|
line.long 0x00 "SPI_IRQ_MASK,SPI interrupt mask register."
|
|
bitfld.long 0x00 14. " MST_FRM_END ,SPI Master Frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
bitfld.long 0x00 11. " IDLE ,SPI trans IDLE." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "TIMEOUT ,SPI trnas timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag." "0,1"
|
|
bitfld.long 0x00 7. " RX_FIFO_PRE_FULL ,Rx fifo dpt > thrd interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "TX_FIFO_PRE_EMPTY ,Tx fifo dpt < thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
bitfld.long 0x00 3. " RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0DB0024++0x03
|
|
line.long 0x00 "SPI_IRQ_STAT,SPI interrupt status."
|
|
bitfld.long 0x00 28.--31. " SPI_FSM_ST ,SPI FSM state." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " MST_FRM_END ,Master frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IDLE ,SPI Trans IDLE." "0,1"
|
|
bitfld.long 0x00 10. " TIMEOUT ,SPI trans timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done. In master mode , when SPI returns to IDLE state with TX FIFO empty, this bit will be set." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag. It will be set at the end of each frame transfer" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RX_FIFO_PRE_FULL ,Rx fifo dpt > =thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 6. " TX_FIFO_PRE_EMPTY ,Tx fifo dpt =< thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 2. " TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0DB0030++0x03
|
|
line.long 0x00 "SPI_FIFO_STAT,SPI FIFO status register."
|
|
bitfld.long 0x00 25. " RX_FULL ,RX FIFO full." "0,1"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 16.--20. " RX_FIFO_DPTR ,RX fifo dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " TX_FULL ,TX FIFO FULL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "TX_EMPTY ,TX FIFO empty" "0,1"
|
|
bitfld.long 0x00 0.--4. " TX_FIFO_DPTR ,Tx FIFO dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0DB0034++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CTRL,SPI TX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,TX FIFO threshold. When FIFO dptr <= thrd, will generate a n TX fifo almost empty interrpt. It also is used to generate tx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0DB0038++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_CTRL,SPI RX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,RX FIFO threshold. When FIFO dptr > thrd , will generate a n RX fifo almost empty interrpt. It also is used to generate rx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0DB0040++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0DB0044++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt mask"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF0DB0048++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,Err_inj_en Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,registrer parity_err_inj Error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0DB004C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_MASK,Function safety uncorrectable error interrupt mask register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete erro" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,ERR_INJ_EN Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,REG_PARITY_ERR_INJ_EN ERROR mask" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0DB0050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
|
|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0DB0054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_MASK,Function safety correctable error interrupt status mask register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
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|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
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|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
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|
group ad:0xF0DB0058++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
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|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF0DB005C++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF0DB0060++0x03
|
|
line.long 0x00 "PRDATAINJ,inject error to the parity of apb_rdata[31:0]"
|
|
bitfld.long 0x00 0. " DATA_INJ ,inject error to the parity of apb_rdata[31:0]" "0,1"
|
|
group ad:0xF0DB0064++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 2. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
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|
bitfld.long 0x00 1. " COR_ERR ,Correctable error interrupt error injection." "0,1"
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|
bitfld.long 0x00 0. " FUN_IRQ ,SPI function irq Error injection." "0,1"
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|
group ad:0xF0DB0068++0x03
|
|
line.long 0x00 "DMA_INJ,Error injection on DMA ."
|
|
bitfld.long 0x00 28.--31. " rx_fw_data_inj ,o_dma_rx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 24.--27. " rx_fw_code_inj ,o_dma_rx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 20.--23. " rx_bw_data_inj ,o_dma_rx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. " rx_bw_code_inj ,o_dma_rx_bw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. "tx_fw_data_inj ,o_dma_tx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. " tx_fw_code_inj ,o_dma_tx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. " tx_bw_data_inj ,o_dma_tx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " tx_bw_code_inj ,o_dma_tx_bw_code_inj." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group ad:0xF0DB0080++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Selftest_mode enable."
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|
bitfld.long 0x00 0. " en ,Selftest_mode enable." "0,1"
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|
group ad:0xF0DB1000++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CMD,SPI CMD data wirte port."
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|
group ad:0xF0DB2000++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_DATA,SPI TX Data register.SPI transmitter FIFO data port. The address range from 0x1000-0x1fff(4KB). When writing to this register, you must right-justify the data."
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|
group ad:0xF0DB3000++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_DATA,SPI RX data register.SPI RX FIFO data port. The address range from 0x2000-0x2fff(4KB)."
|
|
tree.end
|
|
tree "SPI7"
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|
width 27.
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|
group ad:0xF0A20000++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI contrl register."
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|
bitfld.long 0x00 31. " SW_RST ,SPI software reset. high active, softare clear." "0,1"
|
|
bitfld.long 0x00 25.--29. " IDLE ,SPI IDLE count value.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 24. " SAMPLE_POINT ,Data sample point. It's useful in Mast mode. 1'b0: input data sampled on SCK edge. 1'b1: input data is sampled on delayed half sck cycle edge." "0,1"
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|
bitfld.long 0x00 16.--20. " TIMEOUT ,Timeout value for the Data Wait state.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. "NSS_POL ,NSS polarity for 4 seperated NSS Pins. Each NSS_POL bit position corresponds to a NSS pin. 1'b0: NSS is active low. 1'b1: NSS is active high." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 6. " SSP_CLK_MODE ,SSP clock mode select: 0: First dummy clock masked . 1: First dummy clock enable." "0,1"
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|
bitfld.long 0x00 5. " RX_DMA_EN ,RX DMA enable." "0,1"
|
|
bitfld.long 0x00 4. " TX_DMA_EN ,Tx dma enable." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "SLV_MODE ,SPI master slave mode select: 1'b0: Master mode 1'b1: slave mode." "0,1"
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|
bitfld.long 0x00 2. " HALF_MODE ,SPI half-duplex mode. 1'b0: full-duplex mode. 1'b1: half-duplex mode." "0,1"
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|
bitfld.long 0x00 1. " SLV_UNS_SIZE_EN ,The unspecified frame size enable in SPI Slave mode. 1'b0: the frame size = SPI_CMD.FRAM_SIZE in SPI slave mode. 1'b1: the fram size is unspecified in SPI slave mode." "0,1"
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|
bitfld.long 0x00 0. " MODE ,SPI mode: 1'b0: SPI mode; 1'b1: TI SSP mode;" "0,1"
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|
group ad:0xF0A20004++0x03
|
|
line.long 0x00 "SPI_TIM_CTRL,SPI Timing control."
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRM_DLY ,Frame delay Defines delay between 2 transition. unit: SCK period. the delay = FRM_DLY + 1;"
|
|
hexmask.long.byte 0x00 8.--15. 1. " END_DLY ,End delay defines from last sck edge to NSS edge delay. the unit is sck period. It's only used in Master mode. the delay = END_DLY+ 1;"
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hexmask.long.byte 0x00 0.--7. 1. " START_DLY ,Start delay defines from NSS edge to first sck edge delay. the units is sck period. It's only used in Master mode. the delay = START_DLY + 1;"
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|
group ad:0xF0A20008++0x03
|
|
line.long 0x00 "SPI_EN,SPI enable register"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI Enable: 1'b0: DIsable 1'b1: enable." "0,1"
|
|
group ad:0xF0A20010++0x03
|
|
line.long 0x00 "SPI_CMD_CTRL,SPI command control register."
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESSCALE ,CLK Prescaler value : 8'h00: DIvide by 1 8'h01: DIvide by 2 .... 8'hff: DIvide by 256"
|
|
bitfld.long 0x00 23. " TX_MASK ,TX data mask. When set this bit. TX data is maked. In mater mode, this bite will initiate a new transfer. This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: data not mask. 1'b1: Mask TX .." "0,1"
|
|
bitfld.long 0x00 22. " RX_MASK ,RX data mask. When set, the rx data will not be stored in RX FIFO.This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: Not mask. 1'b1: RX data mask." "0,1"
|
|
hexmask.long.word 0x00 12.--21. 1. " FRAM_SIZE ,Frame Size, Unit : Word Size. 10'h0: 1 10'h1: 2 10'h2: 3 10'h3: 4 10'h4: 5 .... 10'h3ff: 1024"
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. "WORD_SIZE ,SPI word size: if BYTE=0: 5'h0-2: Reserved. 5'h3: 4 bit 5'h4: 5 bit .... 5'h1f: 32 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 6. " SPI_CPHA ,Clock phase: 1'b0: the first clock transition is first data capture edge. 1'b1: the second clock transition is the first data capture edge." "0,1"
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|
bitfld.long 0x00 5. " SPI_CPOL ,Clock polarity: 1'b0: SCK to 0 when inactive. 1'b1: sck to 1 when inactive." "0,1"
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|
bitfld.long 0x00 4. " LAST ,This bit inDIcate whether the following data word is last. 1'b0: Not last 1'b1: last." "0,1"
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|
textline " "
|
|
bitfld.long 0x00 3. "SWAP ,Tx data byte swap." "0,1"
|
|
bitfld.long 0x00 2. " LSB ,0: TX/RX data is MSB fist. 1: TX/RX data is LSB first." "0,1"
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|
bitfld.long 0x00 0.--1. " NSS ,SPI slave select config." "0,1,2,3"
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|
group ad:0xF0A20020++0x03
|
|
line.long 0x00 "SPI_IRQ_MASK,SPI interrupt mask register."
|
|
bitfld.long 0x00 14. " MST_FRM_END ,SPI Master Frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
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|
bitfld.long 0x00 11. " IDLE ,SPI trans IDLE." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. "TIMEOUT ,SPI trnas timeout." "0,1"
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|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done." "0,1"
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|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag." "0,1"
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|
bitfld.long 0x00 7. " RX_FIFO_PRE_FULL ,Rx fifo dpt > thrd interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "TX_FIFO_PRE_EMPTY ,Tx fifo dpt < thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
bitfld.long 0x00 3. " RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0A20024++0x03
|
|
line.long 0x00 "SPI_IRQ_STAT,SPI interrupt status."
|
|
bitfld.long 0x00 28.--31. " SPI_FSM_ST ,SPI FSM state." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " MST_FRM_END ,Master frame end." "0,1"
|
|
bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
|
|
bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "IDLE ,SPI Trans IDLE." "0,1"
|
|
bitfld.long 0x00 10. " TIMEOUT ,SPI trans timeout." "0,1"
|
|
bitfld.long 0x00 9. " TRANS_DONE ,Transfer done. In master mode , when SPI returns to IDLE state with TX FIFO empty, this bit will be set." "0,1"
|
|
bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag. It will be set at the end of each frame transfer" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "RX_FIFO_PRE_FULL ,Rx fifo dpt > =thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 6. " TX_FIFO_PRE_EMPTY ,Tx fifo dpt =< thrd interrupt status" "0,1"
|
|
bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
|
|
bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. "RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 2. " TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
|
|
bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
|
|
bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
|
|
group ad:0xF0A20030++0x03
|
|
line.long 0x00 "SPI_FIFO_STAT,SPI FIFO status register."
|
|
bitfld.long 0x00 25. " RX_FULL ,RX FIFO full." "0,1"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,RX FIFO empty." "0,1"
|
|
bitfld.long 0x00 16.--20. " RX_FIFO_DPTR ,RX fifo dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " TX_FULL ,TX FIFO FULL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. "TX_EMPTY ,TX FIFO empty" "0,1"
|
|
bitfld.long 0x00 0.--4. " TX_FIFO_DPTR ,Tx FIFO dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group ad:0xF0A20034++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CTRL,SPI TX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,TX FIFO threshold. When FIFO dptr <= thrd, will generate a n TX fifo almost empty interrpt. It also is used to generate tx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0A20038++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_CTRL,SPI RX FIFO control register."
|
|
bitfld.long 0x00 0.--3. " THRD ,RX FIFO threshold. When FIFO dptr > thrd , will generate a n RX fifo almost empty interrpt. It also is used to generate rx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0A20040++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status."
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
|
|
group ad:0xF0A20044++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt mask"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
group ad:0xF0A20048++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_STAT,Function safety uncorrectable error interrupt status register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,Err_inj_en Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,registrer parity_err_inj Error." "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0A2004C++0x03
|
|
line.long 0x00 "FUSA_UNC_ERR_IRQ_MASK,Function safety uncorrectable error interrupt mask register"
|
|
bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete erro" "0,1"
|
|
bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
|
|
bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
|
|
bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
|
|
bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
|
|
bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,ERR_INJ_EN Error." "0,1"
|
|
bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,REG_PARITY_ERR_INJ_EN ERROR mask" "0,1"
|
|
bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
|
|
bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
|
|
group ad:0xF0A20050++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_STAT,Function safety correctable error interrupt status register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
|
|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0A20054++0x03
|
|
line.long 0x00 "FUSA_COR_ERR_IRQ_MASK,Function safety correctable error interrupt status mask register"
|
|
bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
|
|
bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
|
|
bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
|
|
group ad:0xF0A20058++0x03
|
|
line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
|
|
hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
|
group ad:0xF0A2005C++0x03
|
|
line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
|
group ad:0xF0A20060++0x03
|
|
line.long 0x00 "PRDATAINJ,inject error to the parity of apb_rdata[31:0]"
|
|
bitfld.long 0x00 0. " DATA_INJ ,inject error to the parity of apb_rdata[31:0]" "0,1"
|
|
group ad:0xF0A20064++0x03
|
|
line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 2. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
|
|
bitfld.long 0x00 1. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
|
bitfld.long 0x00 0. " FUN_IRQ ,SPI function irq Error injection." "0,1"
|
|
group ad:0xF0A20068++0x03
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line.long 0x00 "DMA_INJ,Error injection on DMA ."
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bitfld.long 0x00 28.--31. " rx_fw_data_inj ,o_dma_rx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. " rx_fw_code_inj ,o_dma_rx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. " rx_bw_data_inj ,o_dma_rx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " rx_bw_code_inj ,o_dma_rx_bw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 12.--15. "tx_fw_data_inj ,o_dma_tx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " tx_fw_code_inj ,o_dma_tx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " tx_bw_data_inj ,o_dma_tx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " tx_bw_code_inj ,o_dma_tx_bw_code_inj." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0A20080++0x03
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line.long 0x00 "SELFTEST_MODE,Selftest_mode enable."
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bitfld.long 0x00 0. " en ,Selftest_mode enable." "0,1"
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group ad:0xF0A21000++0x03
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line.long 0x00 "SPI_TX_FIFO_CMD,SPI CMD data wirte port."
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group ad:0xF0A22000++0x03
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line.long 0x00 "SPI_TX_FIFO_DATA,SPI TX Data register.SPI transmitter FIFO data port. The address range from 0x1000-0x1fff(4KB). When writing to this register, you must right-justify the data."
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group ad:0xF0A23000++0x03
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line.long 0x00 "SPI_RX_FIFO_DATA,SPI RX data register.SPI RX FIFO data port. The address range from 0x2000-0x2fff(4KB)."
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tree.end
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tree "SPI8"
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width 27.
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group ad:0xF0DC0000++0x03
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line.long 0x00 "SPI_CTRL,SPI contrl register."
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bitfld.long 0x00 31. " SW_RST ,SPI software reset. high active, softare clear." "0,1"
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bitfld.long 0x00 25.--29. " IDLE ,SPI IDLE count value.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. " SAMPLE_POINT ,Data sample point. It's useful in Mast mode. 1'b0: input data sampled on SCK edge. 1'b1: input data is sampled on delayed half sck cycle edge." "0,1"
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bitfld.long 0x00 16.--20. " TIMEOUT ,Timeout value for the Data Wait state.(unit: SCK/2 peroid) 5'h0-5'h5: 2^5 = 32 5'h6: 2^6 = 64 5'h7: 2^7 = 128 5'h8: 2^8 = 256 .... 5'h1f: 2^32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 8.--11. "NSS_POL ,NSS polarity for 4 seperated NSS Pins. Each NSS_POL bit position corresponds to a NSS pin. 1'b0: NSS is active low. 1'b1: NSS is active high." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6. " SSP_CLK_MODE ,SSP clock mode select: 0: First dummy clock masked . 1: First dummy clock enable." "0,1"
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bitfld.long 0x00 5. " RX_DMA_EN ,RX DMA enable." "0,1"
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bitfld.long 0x00 4. " TX_DMA_EN ,Tx dma enable." "0,1"
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textline " "
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bitfld.long 0x00 3. "SLV_MODE ,SPI master slave mode select: 1'b0: Master mode 1'b1: slave mode." "0,1"
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bitfld.long 0x00 2. " HALF_MODE ,SPI half-duplex mode. 1'b0: full-duplex mode. 1'b1: half-duplex mode." "0,1"
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bitfld.long 0x00 1. " SLV_UNS_SIZE_EN ,The unspecified frame size enable in SPI Slave mode. 1'b0: the frame size = SPI_CMD.FRAM_SIZE in SPI slave mode. 1'b1: the fram size is unspecified in SPI slave mode." "0,1"
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bitfld.long 0x00 0. " MODE ,SPI mode: 1'b0: SPI mode; 1'b1: TI SSP mode;" "0,1"
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group ad:0xF0DC0004++0x03
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line.long 0x00 "SPI_TIM_CTRL,SPI Timing control."
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hexmask.long.byte 0x00 16.--23. 1. " FRM_DLY ,Frame delay Defines delay between 2 transition. unit: SCK period. the delay = FRM_DLY + 1;"
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hexmask.long.byte 0x00 8.--15. 1. " END_DLY ,End delay defines from last sck edge to NSS edge delay. the unit is sck period. It's only used in Master mode. the delay = END_DLY+ 1;"
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hexmask.long.byte 0x00 0.--7. 1. " START_DLY ,Start delay defines from NSS edge to first sck edge delay. the units is sck period. It's only used in Master mode. the delay = START_DLY + 1;"
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group ad:0xF0DC0008++0x03
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line.long 0x00 "SPI_EN,SPI enable register"
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bitfld.long 0x00 0. " ENABLE ,SPI Enable: 1'b0: DIsable 1'b1: enable." "0,1"
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group ad:0xF0DC0010++0x03
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line.long 0x00 "SPI_CMD_CTRL,SPI command control register."
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hexmask.long.byte 0x00 24.--31. 1. " PRESSCALE ,CLK Prescaler value : 8'h00: DIvide by 1 8'h01: DIvide by 2 .... 8'hff: DIvide by 256"
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bitfld.long 0x00 23. " TX_MASK ,TX data mask. When set this bit. TX data is maked. In mater mode, this bite will initiate a new transfer. This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: data not mask. 1'b1: Mask TX .." "0,1"
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bitfld.long 0x00 22. " RX_MASK ,RX data mask. When set, the rx data will not be stored in RX FIFO.This bit will be cleared by HW at the end of the TX end and last bit valid. 1'b0: Not mask. 1'b1: RX data mask." "0,1"
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hexmask.long.word 0x00 12.--21. 1. " FRAM_SIZE ,Frame Size, Unit : Word Size. 10'h0: 1 10'h1: 2 10'h2: 3 10'h3: 4 10'h4: 5 .... 10'h3ff: 1024"
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textline " "
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bitfld.long 0x00 7.--11. "WORD_SIZE ,SPI word size: if BYTE=0: 5'h0-2: Reserved. 5'h3: 4 bit 5'h4: 5 bit .... 5'h1f: 32 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6. " SPI_CPHA ,Clock phase: 1'b0: the first clock transition is first data capture edge. 1'b1: the second clock transition is the first data capture edge." "0,1"
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bitfld.long 0x00 5. " SPI_CPOL ,Clock polarity: 1'b0: SCK to 0 when inactive. 1'b1: sck to 1 when inactive." "0,1"
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bitfld.long 0x00 4. " LAST ,This bit inDIcate whether the following data word is last. 1'b0: Not last 1'b1: last." "0,1"
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textline " "
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bitfld.long 0x00 3. "SWAP ,Tx data byte swap." "0,1"
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bitfld.long 0x00 2. " LSB ,0: TX/RX data is MSB fist. 1: TX/RX data is LSB first." "0,1"
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bitfld.long 0x00 0.--1. " NSS ,SPI slave select config." "0,1,2,3"
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group ad:0xF0DC0020++0x03
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line.long 0x00 "SPI_IRQ_MASK,SPI interrupt mask register."
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bitfld.long 0x00 14. " MST_FRM_END ,SPI Master Frame end." "0,1"
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bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
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bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
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bitfld.long 0x00 11. " IDLE ,SPI trans IDLE." "0,1"
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textline " "
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bitfld.long 0x00 10. "TIMEOUT ,SPI trnas timeout." "0,1"
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bitfld.long 0x00 9. " TRANS_DONE ,Transfer done." "0,1"
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bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag." "0,1"
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bitfld.long 0x00 7. " RX_FIFO_PRE_FULL ,Rx fifo dpt > thrd interrupt status" "0,1"
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textline " "
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bitfld.long 0x00 6. "TX_FIFO_PRE_EMPTY ,Tx fifo dpt < thrd interrupt status" "0,1"
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bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
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bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
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bitfld.long 0x00 3. " RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
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textline " "
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bitfld.long 0x00 2. "TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
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bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
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bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
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group ad:0xF0DC0024++0x03
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line.long 0x00 "SPI_IRQ_STAT,SPI interrupt status."
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bitfld.long 0x00 28.--31. " SPI_FSM_ST ,SPI FSM state." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 14. " MST_FRM_END ,Master frame end." "0,1"
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bitfld.long 0x00 13. " SLV_NSS_INVLD ,SPI NSS input invalid in Slave mode. It will be set on NSS invalid edge." "0,1"
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bitfld.long 0x00 12. " SLV_NSS_VLD ,SPI NSS input valid in Slave mode. It will be set on NSS valid edge." "0,1"
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textline " "
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bitfld.long 0x00 11. "IDLE ,SPI Trans IDLE." "0,1"
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bitfld.long 0x00 10. " TIMEOUT ,SPI trans timeout." "0,1"
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bitfld.long 0x00 9. " TRANS_DONE ,Transfer done. In master mode , when SPI returns to IDLE state with TX FIFO empty, this bit will be set." "0,1"
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bitfld.long 0x00 8. " FRM_DONE ,The frame complete done flag. It will be set at the end of each frame transfer" "0,1"
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textline " "
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bitfld.long 0x00 7. "RX_FIFO_PRE_FULL ,Rx fifo dpt > =thrd interrupt status" "0,1"
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bitfld.long 0x00 6. " TX_FIFO_PRE_EMPTY ,Tx fifo dpt =< thrd interrupt status" "0,1"
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bitfld.long 0x00 5. " RX_FIFO_OVR ,RX FIFO overrun." "0,1"
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bitfld.long 0x00 4. " RX_FIFO_FULL ,RX FIFO full" "0,1"
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textline " "
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bitfld.long 0x00 3. "RX_FIFO_EMPTY ,RX FIFO empty." "0,1"
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bitfld.long 0x00 2. " TX_FIFO_UDR ,Tx FIFO underrun." "0,1"
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bitfld.long 0x00 1. " TX_FIFO_FULL ,tx fifo full." "0,1"
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bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Tx FIFO empty." "0,1"
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group ad:0xF0DC0030++0x03
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line.long 0x00 "SPI_FIFO_STAT,SPI FIFO status register."
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bitfld.long 0x00 25. " RX_FULL ,RX FIFO full." "0,1"
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bitfld.long 0x00 24. " RX_EMPTY ,RX FIFO empty." "0,1"
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bitfld.long 0x00 16.--20. " RX_FIFO_DPTR ,RX fifo dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 9. " TX_FULL ,TX FIFO FULL" "0,1"
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textline " "
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bitfld.long 0x00 8. "TX_EMPTY ,TX FIFO empty" "0,1"
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bitfld.long 0x00 0.--4. " TX_FIFO_DPTR ,Tx FIFO dptr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group ad:0xF0DC0034++0x03
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line.long 0x00 "SPI_TX_FIFO_CTRL,SPI TX FIFO control register."
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bitfld.long 0x00 0.--3. " THRD ,TX FIFO threshold. When FIFO dptr <= thrd, will generate a n TX fifo almost empty interrpt. It also is used to generate tx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0DC0038++0x03
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line.long 0x00 "SPI_RX_FIFO_CTRL,SPI RX FIFO control register."
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bitfld.long 0x00 0.--3. " THRD ,RX FIFO threshold. When FIFO dptr > thrd , will generate a n RX fifo almost empty interrpt. It also is used to generate rx dma request." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group ad:0xF0DC0040++0x03
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line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status."
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bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt status." "0,1"
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group ad:0xF0DC0044++0x03
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line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt mask"
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bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
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group ad:0xF0DC0048++0x03
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line.long 0x00 "FUSA_UNC_ERR_IRQ_STAT,Function safety uncorrectable error interrupt status register"
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bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
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bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete error" "0,1"
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bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
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bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
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textline " "
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bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
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bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
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bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
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bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
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textline " "
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bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,Err_inj_en Error." "0,1"
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bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,registrer parity_err_inj Error." "0,1"
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bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable parity error" "0,1"
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bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
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textline " "
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
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bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
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group ad:0xF0DC004C++0x03
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line.long 0x00 "FUSA_UNC_ERR_IRQ_MASK,Function safety uncorrectable error interrupt mask register"
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bitfld.long 0x00 13. " RX_DMA_EOBA_POL_ERR ,DMA RX EOB for ack error" "0,1"
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bitfld.long 0x00 12. " RX_DMA_EOBC_POL_ERR ,DMA RX EOB for Complete erro" "0,1"
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bitfld.long 0x00 11. " RX_DMA_BW_FATAL_ERR ,DMA RX backward fatal error" "0,1"
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bitfld.long 0x00 10. " RX_DMA_BW_UNC_ERR ,DMA RX backward uncorrectable error" "0,1"
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textline " "
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bitfld.long 0x00 9. "TX_DMA_EOBA_POL_ERR ,DMA TX EOB for ack error" "0,1"
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bitfld.long 0x00 8. " TX_DMA_EOBC_POL_ERR ,DMA TX EOB for Complete error" "0,1"
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bitfld.long 0x00 7. " TX_DMA_BW_FATAL_ERR ,DMA TX backward fatal error" "0,1"
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bitfld.long 0x00 6. " TX_DMA_BW_UNC_ERR ,DMA TX backward uncorrectable error" "0,1"
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textline " "
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bitfld.long 0x00 5. "ERR_INJ_EN_ERR ,ERR_INJ_EN Error." "0,1"
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bitfld.long 0x00 4. " REG_PARITY_ERR_INJ_EN_ERR ,REG_PARITY_ERR_INJ_EN ERROR mask" "0,1"
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bitfld.long 0x00 3. " PCTL_UNC_ERR ,Apb control siganls(pwrite, psel and penable) parity error" "0,1"
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bitfld.long 0x00 2. " PADDR_UNC_ERR ,Paddr parity error" "0,1"
|
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textline " "
|
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bitfld.long 0x00 1. "PWDATA_FATAL_ERR ,Pwdata fatal error." "0,1"
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bitfld.long 0x00 0. " PWDATA_UNC_ERR ,Pwdata uncorrectable error." "0,1"
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group ad:0xF0DC0050++0x03
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line.long 0x00 "FUSA_COR_ERR_IRQ_STAT,Function safety correctable error interrupt status register"
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bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
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bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
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bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
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group ad:0xF0DC0054++0x03
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line.long 0x00 "FUSA_COR_ERR_IRQ_MASK,Function safety correctable error interrupt status mask register"
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bitfld.long 0x00 2. " RX_DMA_BW_COR_ERR ,DMA RX backward correctable error" "0,1"
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bitfld.long 0x00 1. " TX_DMA_BW_COR_ERR ,DMA TX backward correctable error" "0,1"
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bitfld.long 0x00 0. " PWDATA_COR_ERR ,Pwdata correctable error." "0,1"
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group ad:0xF0DC0058++0x03
|
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line.long 0x00 "PWDATA_INJ,Error injection on apb write data"
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hexmask.long 0x00 0.--31. 1. " DATA_INJ ,Error injection on axi write data and apb write data"
|
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group ad:0xF0DC005C++0x03
|
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line.long 0x00 "PWECC_INJ,Error injection on apb write data ecc code"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ECC_INJ ,Error injection on ecc code for axi write data and apb write data"
|
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group ad:0xF0DC0060++0x03
|
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line.long 0x00 "PRDATAINJ,inject error to the parity of apb_rdata[31:0]"
|
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bitfld.long 0x00 0. " DATA_INJ ,inject error to the parity of apb_rdata[31:0]" "0,1"
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group ad:0xF0DC0064++0x03
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line.long 0x00 "INT_ERR_INJ,Interrupt error injection."
|
|
bitfld.long 0x00 2. " UNC_ERR ,Uncorrectable error interrupt interrupt error injection." "0,1"
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bitfld.long 0x00 1. " COR_ERR ,Correctable error interrupt error injection." "0,1"
|
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bitfld.long 0x00 0. " FUN_IRQ ,SPI function irq Error injection." "0,1"
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group ad:0xF0DC0068++0x03
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line.long 0x00 "DMA_INJ,Error injection on DMA ."
|
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bitfld.long 0x00 28.--31. " rx_fw_data_inj ,o_dma_rx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. " rx_fw_code_inj ,o_dma_rx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. " rx_bw_data_inj ,o_dma_rx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " rx_bw_code_inj ,o_dma_rx_bw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
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bitfld.long 0x00 12.--15. "tx_fw_data_inj ,o_dma_tx_fw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " tx_fw_code_inj ,o_dma_tx_fw_code_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " tx_bw_data_inj ,o_dma_tx_bw_data_inj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " tx_bw_code_inj ,o_dma_tx_bw_code_inj." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF0DC0080++0x03
|
|
line.long 0x00 "SELFTEST_MODE,Selftest_mode enable."
|
|
bitfld.long 0x00 0. " en ,Selftest_mode enable." "0,1"
|
|
group ad:0xF0DC1000++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_CMD,SPI CMD data wirte port."
|
|
group ad:0xF0DC2000++0x03
|
|
line.long 0x00 "SPI_TX_FIFO_DATA,SPI TX Data register.SPI transmitter FIFO data port. The address range from 0x1000-0x1fff(4KB). When writing to this register, you must right-justify the data."
|
|
group ad:0xF0DC3000++0x03
|
|
line.long 0x00 "SPI_RX_FIFO_DATA,SPI RX data register.SPI RX FIFO data port. The address range from 0x2000-0x2fff(4KB)."
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "VIC"
|
|
tree "VIC1"
|
|
width 17.
|
|
group ad:0xF1C00000++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00004++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00008++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C0000C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00010++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00014++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00018++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C0001C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00020++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00024++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00028++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C0002C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00030++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00034++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00038++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C0003C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C00040++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00044++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00048++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C0004C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00050++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00054++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00058++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C0005C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00060++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00064++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00068++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C0006C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00070++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00074++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00078++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C0007C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C00080++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C00084++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C00088++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C0008C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C00090++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C00094++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C00098++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C0009C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C000A0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C000A4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C000A8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C000AC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C000B0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C000B4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C000B8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C000BC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C000C0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000C4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000C8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000CC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000D0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000D4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000D8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000DC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000E0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000E4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000E8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000EC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000F0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000F4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000F8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C000FC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C00100++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00104++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00108++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C0010C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00110++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00114++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00118++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C0011C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00120++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00124++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00128++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C0012C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00130++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00134++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00138++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C0013C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C00140++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00144++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00148++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C0014C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00150++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00154++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00158++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C0015C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00160++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00164++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00168++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C0016C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00170++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00174++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00178++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C0017C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C00180++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C00184++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C00188++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C0018C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C00190++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C00194++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C00198++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C0019C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C001A0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C001A4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C001A8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C001AC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C001B0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C001B4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C001B8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C001BC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C001C0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001C4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001C8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001CC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001D0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001D4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001D8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001DC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001E0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001E4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001E8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001EC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001F0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001F4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001F8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C001FC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C00200++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00204++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00208++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C0020C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00210++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00214++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00218++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C0021C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00220++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00224++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00228++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C0022C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00230++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00234++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00238++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C0023C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C00380++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C00384++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C00388++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C0038C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C00390++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C00394++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C00398++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C0039C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C003A0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C003A4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C003A8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C003AC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C003B0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C003B4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C003B8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C003BC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C003C0++0x03
|
|
line.long 0x00 "WDT_TH,timeout settings"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: timeout function enable bit25~bit16: reference clock DIvider bit7~bit0: timeout threshold(configure threshold to 0 is not allowed)"
|
|
group ad:0xF1C003C4++0x03
|
|
line.long 0x00 "AHB_PRTENB,ahb prot enable, privileged access only"
|
|
bitfld.long 0x00 0. " VAL ,ahb prot enable, privileged access only" "0,1"
|
|
group ad:0xF1C003C8++0x03
|
|
line.long 0x00 "ERRINT_MASK,error mask only for apss"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C003CC++0x03
|
|
line.long 0x00 "ERRINT_CLR,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,write 1 to clear"
|
|
group ad:0xF1C003D0++0x03
|
|
line.long 0x00 "ERRINT_RAW,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C003D4++0x03
|
|
line.long 0x00 "ERRINT_ST,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C00400++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00404++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00408++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0040C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00410++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00414++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00418++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0041C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00420++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00424++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00428++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0042C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00430++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00434++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00438++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0043C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00440++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00444++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00448++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0044C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00450++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00454++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00458++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0045C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00460++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00464++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00468++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0046C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00470++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00474++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00478++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0047C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00480++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00484++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00488++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0048C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00490++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00494++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00498++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0049C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C004FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00500++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00504++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00508++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0050C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00510++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00514++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00518++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0051C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00520++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00524++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00528++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0052C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00530++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00534++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00538++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0053C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00540++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00544++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00548++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0054C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00550++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00554++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00558++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0055C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00560++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00564++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00568++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0056C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00570++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00574++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00578++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0057C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00580++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00584++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00588++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0058C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00590++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00594++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00598++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0059C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C005FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00600++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00604++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00608++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0060C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00610++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00614++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00618++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0061C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00620++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00624++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00628++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0062C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00630++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00634++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00638++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0063C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00640++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00644++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00648++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0064C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00650++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00654++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00658++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0065C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00660++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00664++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00668++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0066C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00670++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00674++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00678++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0067C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00680++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00684++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00688++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0068C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00690++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00694++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00698++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0069C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C006FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00700++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00704++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00708++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0070C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00710++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00714++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00718++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0071C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00720++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00724++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00728++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0072C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00730++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00734++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00738++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0073C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00740++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00744++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00748++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0074C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00750++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00754++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00758++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0075C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00760++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00764++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00768++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0076C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00770++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00774++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00778++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0077C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00780++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00784++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00788++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0078C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00790++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00794++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00798++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0079C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C007FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00800++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00804++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00808++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0080C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00810++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00814++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00818++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0081C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00820++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00824++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00828++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0082C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00830++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00834++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00838++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0083C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00840++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00844++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00848++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0084C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00850++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00854++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00858++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0085C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00860++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00864++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00868++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0086C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00870++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00874++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00878++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0087C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00880++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00884++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00888++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0088C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00890++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00894++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00898++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0089C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C008FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00900++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00904++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00908++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0090C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00910++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00914++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00918++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0091C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00920++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00924++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00928++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0092C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00930++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00934++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00938++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0093C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00940++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00944++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00948++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0094C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00950++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00954++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00958++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0095C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00960++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00964++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00968++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0096C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00970++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00974++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00978++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0097C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00980++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00984++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00988++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0098C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00990++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00994++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00998++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C0099C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C009FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00A9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00ABC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00ACC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00ADC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00AFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00B9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BBC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BCC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BDC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00BFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C00F00++0x03
|
|
line.long 0x00 "VICADDRESS,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C01000++0x03
|
|
line.long 0x00 "AHB_INJ_EN,ahb e2e error injection enable. (only for VIC_SFSS and VIC_SPSS)"
|
|
bitfld.long 0x00 0. " VAL ,error injection enable" "0,1"
|
|
group ad:0xF1C01004++0x03
|
|
line.long 0x00 "AHB_HWDATA_INJ,ahb hwdata error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,hwdata error injection"
|
|
group ad:0xF1C01008++0x03
|
|
line.long 0x00 "AHB_HWECC_INJ,ahb hwecc error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,hwecc error injection"
|
|
group ad:0xF1C0100C++0x03
|
|
line.long 0x00 "SFERR_INJ_EN,safe error injection enable (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: corerr irq injection bit bit30: uncerr irq injection bit bit29: lp_mode fail injection bit bit28: intsrc check error injection bit bit27: reserved bit26: reserved bit25: selftest mode check fail injection bit bit24:is_lockstep_fail(.."
|
|
group ad:0xF1C01010++0x03
|
|
line.long 0x00 "WDT_PNCHK_INJ,vic wdt reduntant check error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--5. 1. " VAL ,bit5: irq_b timeout pn parity injection bit bit4: fiq_b timeout pn parity injection bit bit3: fiq_b pn parity injection bit bit2: irq_b pn parity injection bit bit1: wdt enable cfg pn parity injection bit bit0: wdt reduntant check injection .."
|
|
group ad:0xF1C0101C++0x03
|
|
line.long 0x00 "CMP_INJ_EN,lockstep compare error injection enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SEL ,injection selection"
|
|
bitfld.long 0x00 0. " ENABLE ,injection enable" "0,1"
|
|
group ad:0xF1C01020++0x03
|
|
line.long 0x00 "CMP_INJ_BIT0,compare injection data bit31~bit0"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,64bit injection data internal signal selected: to use bit9~bit0 memory ecc selected: to use bit17~bit0 memory selected: to use bit42~bit0 cpu ack selected: to use bit34~bit0 irq selected: to use bit3~bit0 apb selected: to use bit41~bit0.."
|
|
group ad:0xF1C01024++0x03
|
|
line.long 0x00 "CMP_INJ_BIT1,compare injection data bit63~bit32"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C01F00++0x03
|
|
line.long 0x00 "SFINT_MASK,safe irq mask (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF1C01F04++0x03
|
|
line.long 0x00 "SFINT_CLR,safe irq clear (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr(correctable) bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check .."
|
|
group ad:0xF1C01F08++0x03
|
|
line.long 0x00 "SFINT_RAW,safe irq raw (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF1C01F0C++0x03
|
|
line.long 0x00 "SFINT_ST,safe irq status (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF1C02000++0x03
|
|
line.long 0x00 "VIC_MNT0,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C02004++0x03
|
|
line.long 0x00 "VIC_MNT1,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C02008++0x03
|
|
line.long 0x00 "VIC_MNT2,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C0200C++0x03
|
|
line.long 0x00 "VIC_MNT3,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C02010++0x03
|
|
line.long 0x00 "VIC_MNT4,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C0F000++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F004++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F008++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F00C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F010++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F014++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F018++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F01C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F020++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F024++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F028++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F02C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F030++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F034++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F038++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F03C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F040++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F044++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F048++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F04C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F050++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F054++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F058++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F05C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F060++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F064++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F068++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F06C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F070++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F074++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F078++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F07C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F080++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F084++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F088++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F08C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F090++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F094++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F098++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F09C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F0FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F100++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F104++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F108++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F10C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F110++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F114++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F118++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F11C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F120++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F124++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F128++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F12C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F130++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F134++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F138++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F13C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F140++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F144++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F148++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F14C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F150++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F154++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F158++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F15C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F160++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F164++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F168++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F16C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F170++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F174++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F178++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F17C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F180++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F184++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F188++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F18C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F190++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F194++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F198++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F19C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F1FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F200++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F204++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F208++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F20C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F210++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F214++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F218++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F21C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F220++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F224++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F228++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F22C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F230++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F234++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F238++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F23C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F240++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F244++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F248++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F24C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F250++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F254++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F258++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F25C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F260++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F264++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F268++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F26C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F270++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F274++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F278++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F27C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F280++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F284++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F288++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F28C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F290++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F294++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F298++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F29C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F2FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F300++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F304++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F308++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F30C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F310++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F314++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F318++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F31C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F320++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F324++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F328++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F32C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F330++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F334++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F338++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F33C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F340++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F344++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F348++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F34C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F350++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F354++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F358++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F35C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F360++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F364++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F368++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F36C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F370++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F374++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F378++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F37C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F380++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F384++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F388++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F38C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F390++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F394++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F398++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F39C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F3FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F400++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F404++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F408++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F40C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F410++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F414++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F418++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F41C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F420++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F424++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F428++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F42C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F430++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F434++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F438++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F43C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F440++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F444++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F448++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F44C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F450++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F454++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F458++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F45C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F460++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F464++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F468++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F46C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F470++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F474++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F478++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F47C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F480++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F484++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F488++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F48C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F490++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F494++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F498++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F49C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F4FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F500++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F504++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F508++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F50C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F510++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F514++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F518++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F51C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F520++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F524++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F528++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F52C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F530++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F534++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F538++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F53C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F540++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F544++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F548++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F54C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F550++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F554++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F558++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F55C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F560++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F564++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F568++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F56C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F570++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F574++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F578++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F57C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F580++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F584++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F588++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F58C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F590++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F594++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F598++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F59C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F5FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F600++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F604++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F608++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F60C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F610++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F614++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F618++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F61C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F620++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F624++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F628++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F62C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F630++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F634++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F638++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F63C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F640++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F644++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F648++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F64C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F650++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F654++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F658++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F65C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F660++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F664++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F668++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F66C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F670++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F674++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F678++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F67C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F680++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F684++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F688++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F68C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F690++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F694++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F698++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F69C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F6FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F700++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F704++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F708++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F70C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F710++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F714++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F718++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F71C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F720++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F724++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F728++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F72C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F730++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F734++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F738++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F73C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F740++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F744++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F748++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F74C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F750++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F754++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F758++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F75C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F760++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F764++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F768++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F76C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F770++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F774++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F778++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F77C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F780++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F784++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F788++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F78C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F790++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F794++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F798++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F79C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C0F7FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
tree.end
|
|
tree "VIC3PortA"
|
|
width 17.
|
|
group ad:0xF1C20000++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20004++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20008++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C2000C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20010++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20014++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20018++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C2001C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20020++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20024++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20028++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C2002C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20030++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20034++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20038++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C2003C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C20040++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20044++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20048++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C2004C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20050++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20054++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20058++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C2005C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20060++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20064++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20068++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C2006C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20070++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20074++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20078++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C2007C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C20080++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C20084++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C20088++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C2008C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C20090++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C20094++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C20098++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C2009C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C200A0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C200A4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C200A8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C200AC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C200B0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C200B4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C200B8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C200BC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C200C0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200C4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200C8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200CC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200D0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200D4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200D8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200DC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200E0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200E4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200E8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200EC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200F0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200F4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200F8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C200FC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C20100++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20104++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20108++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C2010C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20110++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20114++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20118++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C2011C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20120++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20124++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20128++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C2012C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20130++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20134++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20138++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C2013C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C20140++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20144++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20148++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C2014C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20150++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20154++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20158++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C2015C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20160++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20164++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20168++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C2016C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20170++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20174++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20178++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C2017C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C20180++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C20184++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C20188++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C2018C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C20190++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C20194++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C20198++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C2019C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C201A0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C201A4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C201A8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C201AC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C201B0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C201B4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C201B8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C201BC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C201C0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201C4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201C8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201CC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201D0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201D4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201D8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201DC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201E0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201E4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201E8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201EC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201F0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201F4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201F8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C201FC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C20200++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20204++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20208++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C2020C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20210++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20214++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20218++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C2021C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20220++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20224++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20228++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C2022C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20230++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20234++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20238++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C2023C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C20380++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C20384++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C20388++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C2038C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C20390++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C20394++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C20398++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C2039C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C203A0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C203A4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C203A8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C203AC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C203B0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C203B4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C203B8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C203BC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C203C0++0x03
|
|
line.long 0x00 "WDT_TH,timeout settings"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: timeout function enable bit25~bit16: reference clock DIvider bit7~bit0: timeout threshold(configure threshold to 0 is not allowed)"
|
|
group ad:0xF1C203C4++0x03
|
|
line.long 0x00 "AHB_PRTENB,ahb prot enable, privileged access only"
|
|
bitfld.long 0x00 0. " VAL ,ahb prot enable, privileged access only" "0,1"
|
|
group ad:0xF1C203C8++0x03
|
|
line.long 0x00 "ERRINT_MASK,error mask only for apss"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C203CC++0x03
|
|
line.long 0x00 "ERRINT_CLR,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,write 1 to clear"
|
|
group ad:0xF1C203D0++0x03
|
|
line.long 0x00 "ERRINT_RAW,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C203D4++0x03
|
|
line.long 0x00 "ERRINT_ST,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C20400++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20404++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20408++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2040C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20410++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20414++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20418++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2041C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20420++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20424++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20428++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2042C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20430++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20434++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20438++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2043C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20440++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20444++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20448++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2044C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20450++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20454++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20458++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2045C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20460++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20464++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20468++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2046C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20470++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20474++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20478++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2047C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20480++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20484++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20488++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2048C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20490++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20494++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20498++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2049C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C204FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20500++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20504++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20508++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2050C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20510++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20514++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20518++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2051C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20520++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20524++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20528++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2052C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20530++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20534++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20538++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2053C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20540++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20544++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20548++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2054C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20550++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20554++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20558++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2055C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20560++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20564++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20568++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2056C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20570++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20574++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20578++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2057C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20580++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20584++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20588++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2058C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20590++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20594++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20598++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2059C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C205FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20600++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20604++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20608++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2060C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20610++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20614++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20618++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2061C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20620++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20624++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20628++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2062C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20630++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20634++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20638++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2063C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20640++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20644++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20648++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2064C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20650++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20654++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20658++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2065C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20660++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20664++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20668++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2066C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20670++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20674++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20678++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2067C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20680++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20684++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20688++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2068C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20690++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20694++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20698++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2069C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C206FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20700++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20704++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20708++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2070C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20710++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20714++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20718++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2071C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20720++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20724++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20728++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2072C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20730++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20734++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20738++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2073C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20740++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20744++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20748++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2074C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20750++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20754++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20758++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2075C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20760++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20764++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20768++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2076C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20770++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20774++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20778++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2077C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20780++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20784++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20788++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2078C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20790++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20794++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20798++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2079C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C207FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20800++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20804++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20808++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2080C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20810++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20814++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20818++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2081C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20820++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20824++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20828++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2082C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20830++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20834++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20838++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2083C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20840++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20844++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20848++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2084C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20850++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20854++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20858++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2085C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20860++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20864++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20868++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2086C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20870++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20874++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20878++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2087C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20880++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20884++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20888++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2088C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20890++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20894++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20898++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2089C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C208FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20900++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20904++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20908++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2090C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20910++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20914++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20918++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2091C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20920++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20924++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20928++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2092C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20930++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20934++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20938++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2093C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20940++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20944++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20948++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2094C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20950++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20954++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20958++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2095C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20960++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20964++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20968++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2096C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20970++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20974++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20978++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2097C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20980++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20984++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20988++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2098C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20990++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20994++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20998++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C2099C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C209FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20A9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20ABC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20ACC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20ADC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20AFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20B9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BBC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BCC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BDC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20BFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C20F00++0x03
|
|
line.long 0x00 "VICADDRESS,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C21000++0x03
|
|
line.long 0x00 "AHB_INJ_EN,ahb e2e error injection enable. (only for VIC_SFSS and VIC_SPSS)"
|
|
bitfld.long 0x00 0. " VAL ,error injection enable" "0,1"
|
|
group ad:0xF1C21004++0x03
|
|
line.long 0x00 "AHB_HWDATA_INJ,ahb hwdata error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,hwdata error injection"
|
|
group ad:0xF1C21008++0x03
|
|
line.long 0x00 "AHB_HWECC_INJ,ahb hwecc error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,hwecc error injection"
|
|
group ad:0xF1C2100C++0x03
|
|
line.long 0x00 "SFERR_INJ_EN,safe error injection enable (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: corerr irq injection bit bit30: uncerr irq injection bit bit29: lp_mode fail injection bit bit28: intsrc check error injection bit bit27: reserved bit26: reserved bit25: selftest mode check fail injection bit bit24:is_lockstep_fail(.."
|
|
group ad:0xF1C21010++0x03
|
|
line.long 0x00 "WDT_PNCHK_INJ,vic wdt reduntant check error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--5. 1. " VAL ,bit5: irq_b timeout pn parity injection bit bit4: fiq_b timeout pn parity injection bit bit3: fiq_b pn parity injection bit bit2: irq_b pn parity injection bit bit1: wdt enable cfg pn parity injection bit bit0: wdt reduntant check injection .."
|
|
group ad:0xF1C2101C++0x03
|
|
line.long 0x00 "CMP_INJ_EN,lockstep compare error injection enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SEL ,injection selection"
|
|
bitfld.long 0x00 0. " ENABLE ,injection enable" "0,1"
|
|
group ad:0xF1C21020++0x03
|
|
line.long 0x00 "CMP_INJ_BIT0,compare injection data bit31~bit0"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,64bit injection data internal signal selected: to use bit9~bit0 memory ecc selected: to use bit17~bit0 memory selected: to use bit42~bit0 cpu ack selected: to use bit34~bit0 irq selected: to use bit3~bit0 apb selected: to use bit41~bit0.."
|
|
group ad:0xF1C21024++0x03
|
|
line.long 0x00 "CMP_INJ_BIT1,compare injection data bit63~bit32"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C21F00++0x03
|
|
line.long 0x00 "SFINT_MASK,safe irq mask (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF1C21F04++0x03
|
|
line.long 0x00 "SFINT_CLR,safe irq clear (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr(correctable) bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check .."
|
|
group ad:0xF1C21F08++0x03
|
|
line.long 0x00 "SFINT_RAW,safe irq raw (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF1C21F0C++0x03
|
|
line.long 0x00 "SFINT_ST,safe irq status (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF1C22000++0x03
|
|
line.long 0x00 "VIC_MNT0,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C22004++0x03
|
|
line.long 0x00 "VIC_MNT1,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C22008++0x03
|
|
line.long 0x00 "VIC_MNT2,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C2200C++0x03
|
|
line.long 0x00 "VIC_MNT3,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C22010++0x03
|
|
line.long 0x00 "VIC_MNT4,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C2F000++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F004++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F008++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F00C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F010++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F014++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F018++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F01C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F020++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F024++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F028++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F02C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F030++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F034++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F038++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F03C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F040++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F044++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F048++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F04C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F050++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F054++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F058++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F05C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F060++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F064++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F068++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F06C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F070++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F074++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F078++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F07C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F080++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F084++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F088++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F08C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F090++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F094++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F098++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F09C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F0FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F100++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F104++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F108++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F10C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F110++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F114++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F118++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F11C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F120++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F124++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F128++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F12C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F130++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F134++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F138++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F13C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F140++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F144++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F148++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F14C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F150++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F154++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F158++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F15C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F160++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F164++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F168++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F16C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F170++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F174++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F178++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F17C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F180++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F184++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F188++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F18C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F190++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F194++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F198++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F19C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F1FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F200++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F204++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F208++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F20C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F210++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F214++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F218++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F21C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F220++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F224++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F228++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F22C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F230++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F234++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F238++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F23C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F240++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F244++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F248++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F24C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F250++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F254++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F258++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F25C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F260++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F264++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F268++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F26C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F270++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F274++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F278++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F27C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F280++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F284++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F288++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F28C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F290++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F294++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F298++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F29C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F2FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F300++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F304++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F308++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F30C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F310++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F314++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F318++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F31C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F320++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F324++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F328++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F32C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F330++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F334++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F338++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F33C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F340++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F344++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F348++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F34C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F350++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F354++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F358++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F35C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F360++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F364++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F368++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F36C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F370++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F374++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F378++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F37C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F380++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F384++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F388++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F38C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F390++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F394++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F398++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F39C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F3FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F400++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F404++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F408++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F40C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F410++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F414++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F418++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F41C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F420++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F424++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F428++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F42C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F430++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F434++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F438++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F43C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F440++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F444++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F448++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F44C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F450++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F454++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F458++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F45C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F460++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F464++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F468++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F46C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F470++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F474++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F478++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F47C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F480++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F484++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F488++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F48C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F490++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F494++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F498++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F49C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F4FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F500++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F504++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F508++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F50C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F510++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F514++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F518++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F51C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F520++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F524++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F528++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F52C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F530++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F534++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F538++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F53C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F540++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F544++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F548++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F54C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F550++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F554++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F558++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F55C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F560++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F564++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F568++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F56C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F570++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F574++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F578++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F57C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F580++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F584++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F588++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F58C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F590++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F594++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F598++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F59C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F5FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F600++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F604++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F608++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F60C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F610++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F614++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F618++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F61C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F620++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F624++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F628++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F62C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F630++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F634++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F638++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F63C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F640++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F644++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F648++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F64C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F650++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F654++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F658++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F65C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F660++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F664++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F668++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F66C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F670++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F674++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F678++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F67C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F680++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F684++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F688++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F68C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F690++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F694++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F698++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F69C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F6FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F700++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F704++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F708++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F70C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F710++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F714++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F718++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F71C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F720++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F724++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F728++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F72C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F730++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F734++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F738++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F73C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F740++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F744++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F748++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F74C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F750++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F754++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F758++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F75C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F760++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F764++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F768++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F76C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F770++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F774++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F778++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F77C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F780++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F784++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F788++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F78C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F790++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F794++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F798++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F79C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C2F7FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
tree.end
|
|
tree "VIC3PortB"
|
|
width 17.
|
|
group ad:0xF1C30000++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30004++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30008++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C3000C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30010++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30014++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30018++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C3001C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30020++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30024++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30028++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C3002C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30030++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30034++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30038++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C3003C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF1C30040++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30044++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30048++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C3004C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30050++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30054++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30058++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C3005C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30060++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30064++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30068++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C3006C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30070++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30074++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30078++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C3007C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF1C30080++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C30084++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C30088++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C3008C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C30090++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C30094++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C30098++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C3009C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C300A0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C300A4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C300A8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C300AC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C300B0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C300B4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C300B8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C300BC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF1C300C0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300C4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300C8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300CC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300D0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300D4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300D8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300DC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300E0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300E4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300E8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300EC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300F0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300F4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300F8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C300FC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF1C30100++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30104++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30108++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C3010C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30110++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30114++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30118++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C3011C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30120++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30124++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30128++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C3012C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30130++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30134++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30138++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C3013C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF1C30140++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30144++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30148++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C3014C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30150++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30154++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30158++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C3015C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30160++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30164++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30168++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C3016C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30170++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30174++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30178++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C3017C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF1C30180++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C30184++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C30188++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C3018C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C30190++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C30194++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C30198++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C3019C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C301A0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C301A4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C301A8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C301AC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C301B0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C301B4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C301B8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C301BC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF1C301C0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301C4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301C8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301CC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301D0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301D4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301D8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301DC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301E0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301E4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301E8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301EC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301F0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301F4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301F8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C301FC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF1C30200++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30204++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30208++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C3020C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30210++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30214++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30218++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C3021C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30220++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30224++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30228++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C3022C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30230++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30234++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30238++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C3023C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF1C30380++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C30384++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C30388++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C3038C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C30390++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C30394++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C30398++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C3039C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C303A0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C303A4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C303A8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C303AC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C303B0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C303B4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C303B8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C303BC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF1C303C0++0x03
|
|
line.long 0x00 "WDT_TH,timeout settings"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: timeout function enable bit25~bit16: reference clock DIvider bit7~bit0: timeout threshold(configure threshold to 0 is not allowed)"
|
|
group ad:0xF1C303C4++0x03
|
|
line.long 0x00 "AHB_PRTENB,ahb prot enable, privileged access only"
|
|
bitfld.long 0x00 0. " VAL ,ahb prot enable, privileged access only" "0,1"
|
|
group ad:0xF1C303C8++0x03
|
|
line.long 0x00 "ERRINT_MASK,error mask only for apss"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C303CC++0x03
|
|
line.long 0x00 "ERRINT_CLR,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,write 1 to clear"
|
|
group ad:0xF1C303D0++0x03
|
|
line.long 0x00 "ERRINT_RAW,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C303D4++0x03
|
|
line.long 0x00 "ERRINT_ST,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C30400++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30404++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30408++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3040C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30410++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30414++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30418++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3041C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30420++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30424++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30428++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3042C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30430++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30434++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30438++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3043C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30440++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30444++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30448++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3044C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30450++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30454++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30458++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3045C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30460++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30464++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30468++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3046C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30470++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30474++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30478++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3047C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30480++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30484++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30488++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3048C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30490++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30494++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30498++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3049C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C304FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30500++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30504++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30508++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3050C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30510++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30514++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30518++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3051C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30520++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30524++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30528++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3052C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30530++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30534++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30538++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3053C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30540++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30544++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30548++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3054C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30550++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30554++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30558++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3055C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30560++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30564++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30568++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3056C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30570++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30574++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30578++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3057C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30580++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30584++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30588++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3058C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30590++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30594++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30598++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3059C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C305FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30600++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30604++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30608++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3060C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30610++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30614++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30618++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3061C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30620++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30624++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30628++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3062C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30630++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30634++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30638++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3063C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30640++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30644++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30648++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3064C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30650++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30654++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30658++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3065C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30660++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30664++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30668++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3066C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30670++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30674++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30678++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3067C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30680++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30684++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30688++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3068C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30690++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30694++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30698++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3069C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C306FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30700++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30704++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30708++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3070C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30710++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30714++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30718++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3071C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30720++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30724++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30728++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3072C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30730++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30734++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30738++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3073C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30740++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30744++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30748++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3074C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30750++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30754++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30758++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3075C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30760++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30764++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30768++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3076C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30770++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30774++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30778++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3077C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30780++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30784++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30788++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3078C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30790++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30794++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30798++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3079C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C307FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30800++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30804++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30808++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3080C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30810++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30814++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30818++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3081C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30820++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30824++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30828++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3082C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30830++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30834++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30838++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3083C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30840++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30844++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30848++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3084C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30850++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30854++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30858++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3085C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30860++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30864++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30868++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3086C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30870++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30874++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30878++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3087C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30880++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30884++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30888++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3088C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30890++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30894++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30898++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3089C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C308FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30900++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30904++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30908++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3090C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30910++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30914++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30918++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3091C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30920++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30924++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30928++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3092C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30930++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30934++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30938++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3093C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30940++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30944++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30948++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3094C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30950++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30954++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30958++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3095C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30960++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30964++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30968++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3096C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30970++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30974++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30978++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3097C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30980++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30984++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30988++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3098C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30990++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30994++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30998++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C3099C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C309FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30A9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30ABC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30ACC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30ADC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30AFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30B9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BBC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BCC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BDC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30BFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF1C30F00++0x03
|
|
line.long 0x00 "VICADDRESS,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C31000++0x03
|
|
line.long 0x00 "AHB_INJ_EN,ahb e2e error injection enable. (only for VIC_SFSS and VIC_SPSS)"
|
|
bitfld.long 0x00 0. " VAL ,error injection enable" "0,1"
|
|
group ad:0xF1C31004++0x03
|
|
line.long 0x00 "AHB_HWDATA_INJ,ahb hwdata error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,hwdata error injection"
|
|
group ad:0xF1C31008++0x03
|
|
line.long 0x00 "AHB_HWECC_INJ,ahb hwecc error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,hwecc error injection"
|
|
group ad:0xF1C3100C++0x03
|
|
line.long 0x00 "SFERR_INJ_EN,safe error injection enable (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: corerr irq injection bit bit30: uncerr irq injection bit bit29: lp_mode fail injection bit bit28: intsrc check error injection bit bit27: reserved bit26: reserved bit25: selftest mode check fail injection bit bit24:is_lockstep_fail(.."
|
|
group ad:0xF1C31010++0x03
|
|
line.long 0x00 "WDT_PNCHK_INJ,vic wdt reduntant check error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--5. 1. " VAL ,bit5: irq_b timeout pn parity injection bit bit4: fiq_b timeout pn parity injection bit bit3: fiq_b pn parity injection bit bit2: irq_b pn parity injection bit bit1: wdt enable cfg pn parity injection bit bit0: wdt reduntant check injection .."
|
|
group ad:0xF1C3101C++0x03
|
|
line.long 0x00 "CMP_INJ_EN,lockstep compare error injection enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SEL ,injection selection"
|
|
bitfld.long 0x00 0. " ENABLE ,injection enable" "0,1"
|
|
group ad:0xF1C31020++0x03
|
|
line.long 0x00 "CMP_INJ_BIT0,compare injection data bit31~bit0"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,64bit injection data internal signal selected: to use bit9~bit0 memory ecc selected: to use bit17~bit0 memory selected: to use bit42~bit0 cpu ack selected: to use bit34~bit0 irq selected: to use bit3~bit0 apb selected: to use bit41~bit0.."
|
|
group ad:0xF1C31024++0x03
|
|
line.long 0x00 "CMP_INJ_BIT1,compare injection data bit63~bit32"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF1C31F00++0x03
|
|
line.long 0x00 "SFINT_MASK,safe irq mask (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF1C31F04++0x03
|
|
line.long 0x00 "SFINT_CLR,safe irq clear (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr(correctable) bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check .."
|
|
group ad:0xF1C31F08++0x03
|
|
line.long 0x00 "SFINT_RAW,safe irq raw (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF1C31F0C++0x03
|
|
line.long 0x00 "SFINT_ST,safe irq status (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF1C32000++0x03
|
|
line.long 0x00 "VIC_MNT0,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C32004++0x03
|
|
line.long 0x00 "VIC_MNT1,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C32008++0x03
|
|
line.long 0x00 "VIC_MNT2,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C3200C++0x03
|
|
line.long 0x00 "VIC_MNT3,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C32010++0x03
|
|
line.long 0x00 "VIC_MNT4,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF1C3F000++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F004++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F008++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F00C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F010++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F014++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F018++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F01C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F020++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F024++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F028++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F02C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F030++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F034++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F038++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F03C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F040++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F044++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F048++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F04C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F050++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F054++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F058++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F05C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F060++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F064++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F068++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F06C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F070++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F074++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F078++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F07C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F080++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F084++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F088++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F08C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F090++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F094++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F098++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F09C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F0FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F100++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F104++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F108++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F10C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F110++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F114++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F118++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F11C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F120++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F124++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F128++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F12C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F130++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F134++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F138++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F13C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F140++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F144++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F148++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F14C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F150++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F154++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F158++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F15C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F160++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F164++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F168++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F16C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F170++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F174++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F178++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F17C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F180++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F184++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F188++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F18C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F190++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F194++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F198++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F19C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F1FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F200++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F204++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F208++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F20C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F210++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F214++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F218++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F21C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F220++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F224++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F228++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F22C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F230++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F234++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F238++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F23C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F240++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F244++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F248++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F24C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F250++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F254++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F258++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F25C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F260++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F264++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F268++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F26C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F270++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F274++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F278++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F27C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F280++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F284++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F288++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F28C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F290++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F294++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F298++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F29C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F2FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F300++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F304++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F308++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F30C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F310++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F314++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F318++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F31C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F320++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F324++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F328++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F32C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F330++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F334++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F338++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F33C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F340++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F344++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F348++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F34C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F350++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F354++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F358++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F35C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F360++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F364++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F368++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F36C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F370++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F374++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F378++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F37C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F380++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F384++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F388++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F38C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F390++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F394++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F398++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F39C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F3FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F400++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F404++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F408++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F40C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F410++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F414++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F418++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F41C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F420++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F424++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F428++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F42C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F430++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F434++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F438++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F43C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F440++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F444++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F448++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F44C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F450++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F454++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F458++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F45C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F460++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F464++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F468++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F46C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F470++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F474++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F478++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F47C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F480++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F484++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F488++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F48C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F490++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F494++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F498++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F49C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F4FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F500++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F504++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F508++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F50C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F510++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F514++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F518++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F51C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F520++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F524++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F528++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F52C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F530++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F534++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F538++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F53C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F540++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F544++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F548++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F54C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F550++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F554++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F558++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F55C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F560++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F564++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F568++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F56C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F570++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F574++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F578++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F57C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F580++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F584++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F588++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F58C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F590++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F594++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F598++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F59C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F5FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F600++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F604++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F608++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F60C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F610++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F614++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F618++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F61C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F620++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F624++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F628++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F62C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F630++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F634++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F638++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F63C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F640++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F644++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F648++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F64C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F650++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F654++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F658++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F65C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F660++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F664++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F668++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F66C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F670++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F674++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F678++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F67C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F680++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F684++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F688++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F68C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F690++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F694++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F698++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F69C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F6FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F700++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F704++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F708++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F70C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F710++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F714++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F718++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F71C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F720++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F724++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F728++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F72C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F730++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F734++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F738++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F73C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F740++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F744++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F748++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F74C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F750++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F754++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F758++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F75C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F760++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F764++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F768++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F76C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F770++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F774++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F778++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F77C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F780++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F784++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F788++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F78C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F790++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F794++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F798++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F79C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF1C3F7FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
tree.end
|
|
tree "VIC2PortA"
|
|
width 17.
|
|
group ad:0xF2C00000++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00004++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00008++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C0000C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00010++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00014++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00018++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C0001C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00020++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00024++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00028++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C0002C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00030++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00034++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00038++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C0003C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C00040++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00044++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00048++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C0004C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00050++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00054++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00058++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C0005C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00060++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00064++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00068++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C0006C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00070++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00074++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00078++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C0007C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C00080++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C00084++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C00088++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C0008C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C00090++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C00094++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C00098++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C0009C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C000A0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C000A4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C000A8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C000AC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C000B0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C000B4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C000B8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C000BC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C000C0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000C4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000C8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000CC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000D0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000D4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000D8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000DC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000E0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000E4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000E8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000EC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000F0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000F4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000F8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C000FC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C00100++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00104++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00108++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C0010C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00110++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00114++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00118++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C0011C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00120++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00124++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00128++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C0012C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00130++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00134++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00138++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C0013C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C00140++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00144++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00148++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C0014C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00150++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00154++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00158++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C0015C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00160++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00164++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00168++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C0016C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00170++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00174++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00178++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C0017C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C00180++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C00184++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C00188++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C0018C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C00190++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C00194++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C00198++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C0019C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C001A0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C001A4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C001A8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C001AC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C001B0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C001B4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C001B8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C001BC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C001C0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001C4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001C8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001CC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001D0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001D4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001D8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001DC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001E0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001E4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001E8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001EC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001F0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001F4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001F8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C001FC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C00200++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00204++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00208++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C0020C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00210++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00214++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00218++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C0021C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00220++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00224++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00228++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C0022C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00230++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00234++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00238++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C0023C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C00380++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C00384++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C00388++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C0038C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C00390++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C00394++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C00398++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C0039C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C003A0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C003A4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C003A8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C003AC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C003B0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C003B4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C003B8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C003BC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C003C0++0x03
|
|
line.long 0x00 "WDT_TH,timeout settings"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: timeout function enable bit25~bit16: reference clock DIvider bit7~bit0: timeout threshold(configure threshold to 0 is not allowed)"
|
|
group ad:0xF2C003C4++0x03
|
|
line.long 0x00 "AHB_PRTENB,ahb prot enable, privileged access only"
|
|
bitfld.long 0x00 0. " VAL ,ahb prot enable, privileged access only" "0,1"
|
|
group ad:0xF2C003C8++0x03
|
|
line.long 0x00 "ERRINT_MASK,error mask only for apss"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF2C003CC++0x03
|
|
line.long 0x00 "ERRINT_CLR,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,write 1 to clear"
|
|
group ad:0xF2C003D0++0x03
|
|
line.long 0x00 "ERRINT_RAW,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF2C003D4++0x03
|
|
line.long 0x00 "ERRINT_ST,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF2C00400++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00404++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00408++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0040C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00410++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00414++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00418++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0041C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00420++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00424++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00428++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0042C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00430++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00434++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00438++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0043C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00440++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00444++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00448++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0044C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00450++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00454++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00458++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0045C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00460++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00464++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00468++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0046C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00470++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00474++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00478++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0047C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00480++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00484++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00488++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0048C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00490++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00494++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00498++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0049C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C004FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00500++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00504++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00508++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0050C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00510++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00514++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00518++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0051C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00520++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00524++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00528++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0052C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00530++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00534++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00538++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0053C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00540++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00544++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00548++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0054C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00550++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00554++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00558++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0055C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00560++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00564++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00568++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0056C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00570++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00574++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00578++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0057C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00580++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00584++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00588++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0058C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00590++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00594++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00598++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0059C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C005FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00600++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00604++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00608++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0060C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00610++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00614++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00618++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0061C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00620++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00624++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00628++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0062C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00630++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00634++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00638++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0063C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00640++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00644++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00648++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0064C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00650++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00654++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00658++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0065C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00660++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00664++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00668++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0066C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00670++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00674++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00678++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0067C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00680++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00684++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00688++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0068C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00690++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00694++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00698++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0069C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C006FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00700++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00704++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00708++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0070C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00710++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00714++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00718++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0071C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00720++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00724++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00728++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0072C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00730++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00734++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00738++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0073C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00740++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00744++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00748++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0074C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00750++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00754++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00758++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0075C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00760++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00764++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00768++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0076C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00770++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00774++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00778++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0077C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00780++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00784++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00788++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0078C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00790++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00794++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00798++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0079C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C007FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00800++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00804++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00808++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0080C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00810++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00814++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00818++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0081C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00820++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00824++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00828++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0082C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00830++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00834++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00838++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0083C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00840++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00844++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00848++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0084C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00850++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00854++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00858++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0085C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00860++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00864++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00868++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0086C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00870++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00874++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00878++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0087C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00880++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00884++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00888++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0088C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00890++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00894++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00898++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0089C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C008FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00900++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00904++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00908++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0090C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00910++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00914++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00918++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0091C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00920++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00924++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00928++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0092C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00930++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00934++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00938++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0093C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00940++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00944++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00948++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0094C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00950++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00954++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00958++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0095C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00960++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00964++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00968++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0096C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00970++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00974++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00978++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0097C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00980++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00984++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00988++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0098C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00990++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00994++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00998++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C0099C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C009FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00A9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00ABC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00ACC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00ADC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00AFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00B9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BBC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BCC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BDC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00BFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C00F00++0x03
|
|
line.long 0x00 "VICADDRESS,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C01000++0x03
|
|
line.long 0x00 "AHB_INJ_EN,ahb e2e error injection enable. (only for VIC_SFSS and VIC_SPSS)"
|
|
bitfld.long 0x00 0. " VAL ,error injection enable" "0,1"
|
|
group ad:0xF2C01004++0x03
|
|
line.long 0x00 "AHB_HWDATA_INJ,ahb hwdata error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,hwdata error injection"
|
|
group ad:0xF2C01008++0x03
|
|
line.long 0x00 "AHB_HWECC_INJ,ahb hwecc error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,hwecc error injection"
|
|
group ad:0xF2C0100C++0x03
|
|
line.long 0x00 "SFERR_INJ_EN,safe error injection enable (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: corerr irq injection bit bit30: uncerr irq injection bit bit29: lp_mode fail injection bit bit28: intsrc check error injection bit bit27: reserved bit26: reserved bit25: selftest mode check fail injection bit bit24:is_lockstep_fail(.."
|
|
group ad:0xF2C01010++0x03
|
|
line.long 0x00 "WDT_PNCHK_INJ,vic wdt reduntant check error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--5. 1. " VAL ,bit5: irq_b timeout pn parity injection bit bit4: fiq_b timeout pn parity injection bit bit3: fiq_b pn parity injection bit bit2: irq_b pn parity injection bit bit1: wdt enable cfg pn parity injection bit bit0: wdt reduntant check injection .."
|
|
group ad:0xF2C0101C++0x03
|
|
line.long 0x00 "CMP_INJ_EN,lockstep compare error injection enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SEL ,injection selection"
|
|
bitfld.long 0x00 0. " ENABLE ,injection enable" "0,1"
|
|
group ad:0xF2C01020++0x03
|
|
line.long 0x00 "CMP_INJ_BIT0,compare injection data bit31~bit0"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,64bit injection data internal signal selected: to use bit9~bit0 memory ecc selected: to use bit17~bit0 memory selected: to use bit42~bit0 cpu ack selected: to use bit34~bit0 irq selected: to use bit3~bit0 apb selected: to use bit41~bit0.."
|
|
group ad:0xF2C01024++0x03
|
|
line.long 0x00 "CMP_INJ_BIT1,compare injection data bit63~bit32"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF2C01F00++0x03
|
|
line.long 0x00 "SFINT_MASK,safe irq mask (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF2C01F04++0x03
|
|
line.long 0x00 "SFINT_CLR,safe irq clear (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr(correctable) bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check .."
|
|
group ad:0xF2C01F08++0x03
|
|
line.long 0x00 "SFINT_RAW,safe irq raw (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF2C01F0C++0x03
|
|
line.long 0x00 "SFINT_ST,safe irq status (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF2C02000++0x03
|
|
line.long 0x00 "VIC_MNT0,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C02004++0x03
|
|
line.long 0x00 "VIC_MNT1,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C02008++0x03
|
|
line.long 0x00 "VIC_MNT2,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C0200C++0x03
|
|
line.long 0x00 "VIC_MNT3,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C02010++0x03
|
|
line.long 0x00 "VIC_MNT4,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C0F000++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F004++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F008++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F00C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F010++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F014++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F018++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F01C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F020++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F024++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F028++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F02C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F030++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F034++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F038++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F03C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F040++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F044++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F048++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F04C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F050++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F054++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F058++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F05C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F060++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F064++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F068++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F06C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F070++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F074++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F078++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F07C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F080++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F084++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F088++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F08C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F090++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F094++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F098++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F09C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F0FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F100++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F104++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F108++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F10C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F110++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F114++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F118++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F11C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F120++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F124++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F128++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F12C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F130++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F134++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F138++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F13C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F140++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F144++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F148++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F14C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F150++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F154++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F158++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F15C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F160++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F164++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F168++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F16C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F170++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F174++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F178++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F17C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F180++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F184++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F188++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F18C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F190++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F194++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F198++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F19C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F1FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F200++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F204++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F208++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F20C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F210++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F214++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F218++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F21C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F220++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F224++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F228++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F22C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F230++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F234++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F238++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F23C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F240++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F244++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F248++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F24C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F250++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F254++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F258++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F25C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F260++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F264++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F268++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F26C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F270++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F274++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F278++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F27C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F280++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F284++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F288++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F28C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F290++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F294++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F298++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F29C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F2FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F300++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F304++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F308++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F30C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F310++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F314++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F318++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F31C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F320++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F324++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F328++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F32C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F330++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F334++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F338++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F33C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F340++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F344++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F348++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F34C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F350++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F354++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F358++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F35C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F360++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F364++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F368++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F36C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F370++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F374++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F378++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F37C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F380++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F384++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F388++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F38C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F390++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F394++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F398++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F39C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F3FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F400++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F404++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F408++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F40C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F410++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F414++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F418++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F41C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F420++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F424++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F428++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F42C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F430++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F434++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F438++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F43C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F440++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F444++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F448++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F44C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F450++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F454++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F458++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F45C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F460++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F464++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F468++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F46C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F470++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F474++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F478++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F47C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F480++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F484++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F488++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F48C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F490++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F494++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F498++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F49C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F4FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F500++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F504++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F508++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F50C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F510++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F514++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F518++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F51C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F520++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F524++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F528++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F52C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F530++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F534++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F538++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F53C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F540++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F544++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F548++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F54C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F550++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F554++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F558++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F55C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F560++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F564++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F568++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F56C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F570++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F574++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F578++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F57C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F580++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F584++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F588++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F58C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F590++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F594++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F598++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F59C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F5FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F600++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F604++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F608++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F60C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F610++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F614++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F618++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F61C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F620++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F624++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F628++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F62C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F630++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F634++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F638++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F63C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F640++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F644++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F648++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F64C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F650++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F654++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F658++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F65C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F660++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F664++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F668++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F66C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F670++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F674++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F678++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F67C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F680++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F684++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F688++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F68C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F690++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F694++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F698++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F69C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F6FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F700++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F704++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F708++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F70C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F710++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F714++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F718++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F71C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F720++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F724++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F728++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F72C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F730++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F734++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F738++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F73C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F740++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F744++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F748++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F74C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F750++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F754++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F758++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F75C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F760++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F764++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F768++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F76C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F770++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F774++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F778++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F77C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F780++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F784++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F788++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F78C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F790++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F794++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F798++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F79C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C0F7FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
tree.end
|
|
tree "VIC2PortB"
|
|
width 17.
|
|
group ad:0xF2C10000++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10004++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10008++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C1000C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10010++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10014++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10018++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C1001C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10020++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10024++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10028++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C1002C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10030++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10034++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10038++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C1003C++0x03
|
|
line.long 0x00 "VICIRQSTATUS,IRQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,IRQ status register"
|
|
group ad:0xF2C10040++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10044++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10048++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C1004C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10050++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10054++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10058++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C1005C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10060++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10064++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10068++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C1006C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10070++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10074++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10078++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C1007C++0x03
|
|
line.long 0x00 "VICFIQSTATUS,FIQ status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,FIQ status register"
|
|
group ad:0xF2C10080++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C10084++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C10088++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C1008C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C10090++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C10094++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C10098++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C1009C++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C100A0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C100A4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C100A8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C100AC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C100B0++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C100B4++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C100B8++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C100BC++0x03
|
|
line.long 0x00 "VICRAWINTR,raw interrupt status"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,raw interrupt status"
|
|
group ad:0xF2C100C0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100C4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100C8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100CC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100D0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100D4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100D8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100DC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100E0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100E4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100E8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100EC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100F0++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100F4++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100F8++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C100FC++0x03
|
|
line.long 0x00 "VICINTSELECT,interrupt select"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt select"
|
|
group ad:0xF2C10100++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10104++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10108++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C1010C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10110++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10114++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10118++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C1011C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10120++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10124++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10128++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C1012C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10130++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10134++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10138++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C1013C++0x03
|
|
line.long 0x00 "VICINTENABLE,interrupt enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable"
|
|
group ad:0xF2C10140++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10144++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10148++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C1014C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10150++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10154++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10158++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C1015C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10160++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10164++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10168++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C1016C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10170++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10174++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10178++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C1017C++0x03
|
|
line.long 0x00 "VICSOFTINT,software interrupt"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software interrupt"
|
|
group ad:0xF2C10180++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C10184++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C10188++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C1018C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C10190++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C10194++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C10198++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C1019C++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C101A0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C101A4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C101A8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C101AC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C101B0++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C101B4++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C101B8++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C101BC++0x03
|
|
line.long 0x00 "VICSWMASK,software mask"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,software mask"
|
|
group ad:0xF2C101C0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101C4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101C8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101CC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101D0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101D4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101D8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101DC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101E0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101E4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101E8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101EC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101F0++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101F4++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101F8++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C101FC++0x03
|
|
line.long 0x00 "VICINTENCLEAR,interrupt enable clear"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,interrupt enable clear"
|
|
group ad:0xF2C10200++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10204++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10208++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C1020C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10210++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10214++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10218++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C1021C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10220++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10224++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10228++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C1022C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10230++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10234++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10238++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C1023C++0x03
|
|
line.long 0x00 "VICSOFTINTCLEAR,software interrupt clear"
|
|
hexmask.long 0x00 0.--31. 1. " VIC ,software interrupt clear"
|
|
group ad:0xF2C10380++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C10384++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C10388++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C1038C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C10390++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C10394++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C10398++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C1039C++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C103A0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C103A4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C103A8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C103AC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C103B0++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C103B4++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C103B8++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C103BC++0x03
|
|
line.long 0x00 "WDT_EN,time out enable"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,time out enable for interrupt source"
|
|
group ad:0xF2C103C0++0x03
|
|
line.long 0x00 "WDT_TH,timeout settings"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: timeout function enable bit25~bit16: reference clock DIvider bit7~bit0: timeout threshold(configure threshold to 0 is not allowed)"
|
|
group ad:0xF2C103C4++0x03
|
|
line.long 0x00 "AHB_PRTENB,ahb prot enable, privileged access only"
|
|
bitfld.long 0x00 0. " VAL ,ahb prot enable, privileged access only" "0,1"
|
|
group ad:0xF2C103C8++0x03
|
|
line.long 0x00 "ERRINT_MASK,error mask only for apss"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF2C103CC++0x03
|
|
line.long 0x00 "ERRINT_CLR,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,write 1 to clear"
|
|
group ad:0xF2C103D0++0x03
|
|
line.long 0x00 "ERRINT_RAW,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF2C103D4++0x03
|
|
line.long 0x00 "ERRINT_ST,error interrupt(only for APSS) bit0: time out"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF2C10400++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10404++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10408++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1040C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10410++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10414++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10418++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1041C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10420++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10424++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10428++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1042C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10430++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10434++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10438++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1043C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10440++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10444++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10448++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1044C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10450++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10454++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10458++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1045C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10460++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10464++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10468++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1046C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10470++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10474++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10478++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1047C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10480++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10484++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10488++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1048C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10490++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10494++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10498++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1049C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C104FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10500++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10504++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10508++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1050C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10510++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10514++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10518++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1051C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10520++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10524++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10528++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1052C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10530++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10534++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10538++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1053C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10540++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10544++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10548++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1054C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10550++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10554++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10558++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1055C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10560++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10564++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10568++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1056C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10570++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10574++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10578++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1057C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10580++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10584++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10588++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1058C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10590++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10594++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10598++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1059C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C105FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10600++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10604++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10608++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1060C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10610++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10614++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10618++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1061C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10620++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10624++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10628++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1062C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10630++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10634++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10638++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1063C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10640++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10644++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10648++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1064C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10650++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10654++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10658++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1065C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10660++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10664++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10668++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1066C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10670++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10674++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10678++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1067C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10680++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10684++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10688++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1068C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10690++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10694++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10698++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1069C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C106FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10700++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10704++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10708++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1070C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10710++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10714++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10718++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1071C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10720++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10724++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10728++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1072C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10730++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10734++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10738++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1073C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10740++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10744++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10748++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1074C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10750++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10754++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10758++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1075C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10760++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10764++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10768++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1076C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10770++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10774++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10778++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1077C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10780++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10784++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10788++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1078C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10790++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10794++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10798++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1079C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C107FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10800++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10804++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10808++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1080C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10810++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10814++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10818++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1081C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10820++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10824++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10828++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1082C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10830++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10834++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10838++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1083C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10840++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10844++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10848++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1084C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10850++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10854++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10858++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1085C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10860++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10864++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10868++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1086C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10870++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10874++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10878++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1087C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10880++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10884++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10888++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1088C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10890++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10894++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10898++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1089C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C108FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10900++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10904++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10908++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1090C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10910++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10914++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10918++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1091C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10920++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10924++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10928++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1092C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10930++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10934++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10938++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1093C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10940++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10944++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10948++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1094C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10950++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10954++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10958++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1095C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10960++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10964++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10968++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1096C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10970++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10974++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10978++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1097C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10980++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10984++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10988++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1098C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10990++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10994++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10998++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C1099C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109A0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109A4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109A8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109AC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109B0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109B4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109B8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109BC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109C0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109C4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109C8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109CC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109D0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109D4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109D8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109DC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109E0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109E4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109E8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109EC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109F0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109F4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109F8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C109FC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10A9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10ABC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10ACC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10ADC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10AFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B00++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B04++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B08++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B0C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B10++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B14++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B18++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B1C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B20++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B24++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B28++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B2C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B30++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B34++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B38++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B3C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B40++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B44++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B48++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B4C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B50++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B54++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B58++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B5C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B60++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B64++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B68++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B6C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B70++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B74++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B78++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B7C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B80++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B84++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B88++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B8C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B90++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B94++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B98++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10B9C++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BA0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BA4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BA8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BAC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BB0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BB4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BB8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BBC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BC0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BC4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BC8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BCC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BD0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BD4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BD8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BDC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BE0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BE4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BE8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BEC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BF0++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BF4++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BF8++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10BFC++0x03
|
|
line.long 0x00 "VICVECTPRIORITY,vector priority"
|
|
bitfld.long 0x00 0.--3. " VAL ,vector priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group ad:0xF2C10F00++0x03
|
|
line.long 0x00 "VICADDRESS,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C11000++0x03
|
|
line.long 0x00 "AHB_INJ_EN,ahb e2e error injection enable. (only for VIC_SFSS and VIC_SPSS)"
|
|
bitfld.long 0x00 0. " VAL ,error injection enable" "0,1"
|
|
group ad:0xF2C11004++0x03
|
|
line.long 0x00 "AHB_HWDATA_INJ,ahb hwdata error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,hwdata error injection"
|
|
group ad:0xF2C11008++0x03
|
|
line.long 0x00 "AHB_HWECC_INJ,ahb hwecc error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,hwecc error injection"
|
|
group ad:0xF2C1100C++0x03
|
|
line.long 0x00 "SFERR_INJ_EN,safe error injection enable (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit31: corerr irq injection bit bit30: uncerr irq injection bit bit29: lp_mode fail injection bit bit28: intsrc check error injection bit bit27: reserved bit26: reserved bit25: selftest mode check fail injection bit bit24:is_lockstep_fail(.."
|
|
group ad:0xF2C11010++0x03
|
|
line.long 0x00 "WDT_PNCHK_INJ,vic wdt reduntant check error injection (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long.byte 0x00 0.--5. 1. " VAL ,bit5: irq_b timeout pn parity injection bit bit4: fiq_b timeout pn parity injection bit bit3: fiq_b pn parity injection bit bit2: irq_b pn parity injection bit bit1: wdt enable cfg pn parity injection bit bit0: wdt reduntant check injection .."
|
|
group ad:0xF2C1101C++0x03
|
|
line.long 0x00 "CMP_INJ_EN,lockstep compare error injection enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SEL ,injection selection"
|
|
bitfld.long 0x00 0. " ENABLE ,injection enable" "0,1"
|
|
group ad:0xF2C11020++0x03
|
|
line.long 0x00 "CMP_INJ_BIT0,compare injection data bit31~bit0"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,64bit injection data internal signal selected: to use bit9~bit0 memory ecc selected: to use bit17~bit0 memory selected: to use bit42~bit0 cpu ack selected: to use bit34~bit0 irq selected: to use bit3~bit0 apb selected: to use bit41~bit0.."
|
|
group ad:0xF2C11024++0x03
|
|
line.long 0x00 "CMP_INJ_BIT1,compare injection data bit63~bit32"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,"
|
|
group ad:0xF2C11F00++0x03
|
|
line.long 0x00 "SFINT_MASK,safe irq mask (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF2C11F04++0x03
|
|
line.long 0x00 "SFINT_CLR,safe irq clear (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr(correctable) bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check .."
|
|
group ad:0xF2C11F08++0x03
|
|
line.long 0x00 "SFINT_RAW,safe irq raw (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF2C11F0C++0x03
|
|
line.long 0x00 "SFINT_ST,safe irq status (only for VIC_SFSS and VIC_SPSS)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,bit10: is_lockstep_fail(configure signal check from scr_xx pn parity) bit9: wdt reduntant check bit8: memdata corerr bit7: memdata uncerr bit6: selftest fail bit5: lp_mode fail bit4: lockstep fail bit3: time out bit2: intsrc check bit1: .."
|
|
group ad:0xF2C12000++0x03
|
|
line.long 0x00 "VIC_MNT0,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C12004++0x03
|
|
line.long 0x00 "VIC_MNT1,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C12008++0x03
|
|
line.long 0x00 "VIC_MNT2,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C1200C++0x03
|
|
line.long 0x00 "VIC_MNT3,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C12010++0x03
|
|
line.long 0x00 "VIC_MNT4,vic monitor value (only for VIC_SPSS in split-mode)"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,output port monitor value"
|
|
group ad:0xF2C1F000++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F004++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F008++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F00C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F010++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F014++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F018++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F01C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F020++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F024++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F028++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F02C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F030++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F034++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F038++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F03C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F040++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F044++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F048++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F04C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F050++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F054++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F058++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F05C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F060++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F064++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F068++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F06C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F070++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F074++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F078++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F07C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F080++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F084++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F088++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F08C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F090++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F094++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F098++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F09C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F0FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F100++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F104++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F108++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F10C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F110++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F114++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F118++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F11C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F120++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F124++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F128++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F12C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F130++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F134++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F138++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F13C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F140++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F144++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F148++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F14C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F150++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F154++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F158++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F15C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F160++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F164++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F168++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F16C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F170++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F174++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F178++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F17C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F180++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F184++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F188++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F18C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F190++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F194++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F198++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F19C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F1FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F200++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F204++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F208++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F20C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F210++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F214++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F218++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F21C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F220++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F224++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F228++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F22C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F230++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F234++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F238++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F23C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F240++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F244++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F248++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F24C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F250++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F254++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F258++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F25C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F260++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F264++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F268++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F26C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F270++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F274++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F278++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F27C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F280++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F284++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F288++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F28C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F290++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F294++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F298++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F29C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F2FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F300++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F304++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F308++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F30C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F310++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F314++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F318++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F31C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F320++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F324++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F328++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F32C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F330++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F334++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F338++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F33C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F340++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F344++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F348++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F34C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F350++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F354++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F358++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F35C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F360++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F364++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F368++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F36C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F370++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F374++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F378++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F37C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F380++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F384++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F388++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F38C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F390++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F394++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F398++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F39C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F3FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F400++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F404++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F408++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F40C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F410++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F414++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F418++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F41C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F420++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F424++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F428++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F42C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F430++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F434++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F438++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F43C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F440++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F444++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F448++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F44C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F450++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F454++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F458++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F45C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F460++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F464++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F468++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F46C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F470++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F474++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F478++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F47C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F480++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F484++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F488++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F48C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F490++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F494++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F498++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F49C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F4FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F500++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F504++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F508++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F50C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F510++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F514++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F518++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F51C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F520++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F524++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F528++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F52C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F530++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F534++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F538++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F53C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F540++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F544++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F548++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F54C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F550++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F554++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F558++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F55C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F560++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F564++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F568++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F56C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F570++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F574++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F578++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F57C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F580++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F584++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F588++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F58C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F590++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F594++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F598++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F59C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F5FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F600++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F604++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F608++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F60C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F610++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F614++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F618++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F61C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F620++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F624++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F628++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F62C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F630++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F634++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F638++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F63C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F640++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F644++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F648++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F64C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F650++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F654++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F658++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F65C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F660++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F664++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F668++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F66C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F670++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F674++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F678++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F67C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F680++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F684++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F688++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F68C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F690++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F694++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F698++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F69C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F6FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F700++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F704++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F708++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F70C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F710++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F714++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F718++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F71C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F720++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F724++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F728++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F72C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F730++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F734++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F738++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F73C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F740++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F744++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F748++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F74C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F750++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F754++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F758++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F75C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F760++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F764++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F768++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F76C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F770++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F774++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F778++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F77C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F780++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F784++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F788++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F78C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F790++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F794++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F798++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F79C++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7A0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7A4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7A8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7AC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7B0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7B4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7B8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7BC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7C0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7C4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7C8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7CC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7D0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7D4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7D8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7DC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7E0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7E4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7E8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7EC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7F0++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7F4++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7F8++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
group ad:0xF2C1F7FC++0x03
|
|
line.long 0x00 "VICVECADDR,vector address"
|
|
hexmask.long 0x00 0.--31. 1. " VAL ,vector address"
|
|
tree.end
|
|
tree.end
|
|
config 16. 8.
|
|
tree "WDT"
|
|
tree "WDT1"
|
|
width 27.
|
|
group ad:0xF07E0000++0x03
|
|
line.long 0x00 "WDT_CTRL,WDT GLOBAL CONTROL REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " PRE_DIV_NUM ,Wdt pre_en DIvider ration"
|
|
bitfld.long 0x00 10. " WDT_EN_STA ,wdt enable status, need to check after set wdt_en to 1'b1 1: wdt enable done 0: wdt enable not done" "0,1"
|
|
bitfld.long 0x00 9. " SELFTEST_TRIG ,selftest trigger" "0,1"
|
|
bitfld.long 0x00 8. " WDT_EN_SRC ,wdt module enable source select. 1: from register WDT_EN 0: from fuse" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "DBG_HALT_EN ,Wdt halt enable in debug mode. 1: debug halt enable 0: debug halt DIsable" "0,1"
|
|
bitfld.long 0x00 6. " AUTO_RESTART ,Wdt overflow auto restart enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 5. " WTC_SRC ,Wdt terminal count value source. 1: from register WDT_WTC 0: from fuse or soc integration" "0,1"
|
|
bitfld.long 0x00 2.--4. " CLK_SRC ,Wdt clock source select. 3'b000: main clock 3'b001: bus clock 3'b010: ext clock 3'b011: tie off 3'b1xx: lp_clk 32KHz xtal" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 1. "WDT_EN ,Wdt module enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " SOFT_RST ,Wdt software reset, can auto clear, only need to set 1. 1: reset 0: normal operation need to check until it turn to 0 after set it to 1" "0,1"
|
|
group ad:0xF07E0004++0x03
|
|
line.long 0x00 "WDT_WTC,WDT TERMINAL COUNT VALUE"
|
|
hexmask.long 0x00 0.--31. 1. " WTC_VAL ,Wdt terminal count value"
|
|
group ad:0xF07E0008++0x03
|
|
line.long 0x00 "WDT_WRC_CTL,WDT REFRESH CONTROL"
|
|
bitfld.long 0x00 3. " REFR_TRIG ,Refresh trigger, auto clear" "0,1"
|
|
bitfld.long 0x00 2. " SEQ_REFR_EN ,Sequence based WDT refresh enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 1. " MODE1_EN ,Window based refresh, only when programing to refr_trig within a preconfigured time window is treated as validate refresh event. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " MODE0_EN ,Refresh without any conDItion. 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF07E000C++0x03
|
|
line.long 0x00 "WDT_WRC_VAL,WDT REFRESH WINDOW LIMIT"
|
|
hexmask.long 0x00 0.--31. 1. " WIN_LOW_LIMIT ,Window low limit"
|
|
group ad:0xF07E0010++0x03
|
|
line.long 0x00 "WDT_WRC_SEQ,WDT REFRESH SEQUENCE DELTA"
|
|
hexmask.long 0x00 0.--31. 1. " SEQ_DELTA ,Sequence delta"
|
|
group ad:0xF07E0014++0x03
|
|
line.long 0x00 "WDT_RST_CTL,WDT RESET CONTROL"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if INT_RST_EN is 1"
|
|
bitfld.long 0x00 18. " WDT_RST_EN ,internal system reset restart wdt enable" "0,1"
|
|
bitfld.long 0x00 17. " INT_RST_MODE ,internal system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " INT_RST_EN ,internal system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF07E0018++0x03
|
|
line.long 0x00 "WDT_EXT_RST_CTL,WDT EXTERNAL RESET CONTROL"
|
|
bitfld.long 0x00 28. " RST_REQ_POL ,Rst request polarity selection register. Output ext_rst_req_b is low active, if rst_req_pol sets to 0. 0. low active 1. high active" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if EXT_RST_EN is 1"
|
|
bitfld.long 0x00 17. " EXT_RST_MODE ,external system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " EXT_RST_EN ,external system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF07E001C++0x03
|
|
line.long 0x00 "WDT_CNT,WDT COUNTER"
|
|
hexmask.long 0x00 0.--31. 1. " WDT_CNT ,Wdt counter value"
|
|
group ad:0xF07E0020++0x03
|
|
line.long 0x00 "WDT_TSW,WDT TIMESTAMP"
|
|
hexmask.long 0x00 0.--31. 1. " TSW ,timestamp value"
|
|
group ad:0xF07E0024++0x03
|
|
line.long 0x00 "WDT_INT,WDT INTERRUPT"
|
|
bitfld.long 0x00 8. " OVFLOW_INT_CLR ,Wdt timer overflow interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 7. " ILL_SEQ_REFR_INT_CLR ,Illegal sequential refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 6. " ILL_WIN_REFR_INT_CLR ,Illegal counter refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 5. " OVFLOW_INT_STA ,Wdt timer overflow interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "ILL_SEQ_REFR_INT_STA ,Illegal sequential refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 3. " ILL_WIN_REFR_INT_STA ,Illegal counter refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 2. " OVFLOW_INT_EN ,Wdt timer overflow interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " ILL_SEQ_REFR_INT_EN ,Illegal sequential refresh interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ILL_WIN_REFR_INT_EN ,Illegal counter refresh interrupt enable" "0,1"
|
|
group ad:0xF07E0028++0x03
|
|
line.long 0x00 "RST_REQ_MON,WDT RESET REQUEST MONITOR"
|
|
bitfld.long 0x00 3. " EXT_RST_REQ_REC ,external reset request record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 2. " INT_RST_REQ_REC ,internal reset request monitor, record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 1. " EXT_RST_REQ_MON ,external reset request monitor, real time after sync to pclk" "0,1"
|
|
bitfld.long 0x00 0. " INT_RST_REQ_MON ,internal reset request monitor, real time after sync to pclk" "0,1"
|
|
group ad:0xF07E002C++0x03
|
|
line.long 0x00 "DUMMY_RES,DUMMY RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DUMMY ,reserved registers"
|
|
group ad:0xF07E0040++0x03
|
|
line.long 0x00 "WDT_LOCK,WDT LOCK"
|
|
bitfld.long 0x00 6. " CLK_SRC_LOCK ,lock for clk_src in WDT_CTRL register" "0,1"
|
|
bitfld.long 0x00 5. " INT_LOCK ,lock for wtc interrupt registers." "0,1"
|
|
bitfld.long 0x00 4. " EXT_RST_LOCK ,lock for external reset registers." "0,1"
|
|
bitfld.long 0x00 3. " RST_LOCK ,lock for reset registers." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "WRC_LOCK ,lock for refresh registers" "0,1"
|
|
bitfld.long 0x00 1. " WTC_LOCK ,lock for wtc registers." "0,1"
|
|
bitfld.long 0x00 0. " CTL_LOCK ,lock for wtc control registers." "0,1"
|
|
group ad:0xF07E004C++0x03
|
|
line.long 0x00 "WDT_ERR_INJ_EN,WDT ERROR INJECTION ENABLE REGISTER"
|
|
bitfld.long 0x00 2. " OUT_INJ_EN ,wdt output error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_INJ_EN ,IRQ error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " APB_INJ_EN ,APB E2E error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF07E0050++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF07E0054++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF07E0058++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF07E005C++0x03
|
|
line.long 0x00 "WDT_FUSA_INT,WDT FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " SYNC_ERR_CLR ,fusa sync err irq clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,fusa sync irq status" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,fusa sync irq enable" "0,1"
|
|
group ad:0xF07E0060++0x03
|
|
line.long 0x00 "WDT_ERR_INJ,WDT ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 4. " EXT_RST_REQ_INJ ,ext_rst_req_b injection" "0,1"
|
|
bitfld.long 0x00 3. " INT_RST_REQ_INJ ,int_rst_req injection" "0,1"
|
|
bitfld.long 0x00 2. " UNC_IRQ_INJ ,unc irq error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR_IRQ_INJ ,cor irq error injection" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "WDT_IRQ_INJ ,wdt irq error injection" "0,1"
|
|
group ad:0xF07E0070++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
|
|
bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
|
|
group ad:0xF07E0074++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF07E0078++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
tree.end
|
|
tree "WDT2"
|
|
width 27.
|
|
group ad:0xF07F0000++0x03
|
|
line.long 0x00 "WDT_CTRL,WDT GLOBAL CONTROL REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " PRE_DIV_NUM ,Wdt pre_en DIvider ration"
|
|
bitfld.long 0x00 10. " WDT_EN_STA ,wdt enable status, need to check after set wdt_en to 1'b1 1: wdt enable done 0: wdt enable not done" "0,1"
|
|
bitfld.long 0x00 9. " SELFTEST_TRIG ,selftest trigger" "0,1"
|
|
bitfld.long 0x00 8. " WDT_EN_SRC ,wdt module enable source select. 1: from register WDT_EN 0: from fuse" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "DBG_HALT_EN ,Wdt halt enable in debug mode. 1: debug halt enable 0: debug halt DIsable" "0,1"
|
|
bitfld.long 0x00 6. " AUTO_RESTART ,Wdt overflow auto restart enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 5. " WTC_SRC ,Wdt terminal count value source. 1: from register WDT_WTC 0: from fuse or soc integration" "0,1"
|
|
bitfld.long 0x00 2.--4. " CLK_SRC ,Wdt clock source select. 3'b000: main clock 3'b001: bus clock 3'b010: ext clock 3'b011: tie off 3'b1xx: lp_clk 32KHz xtal" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 1. "WDT_EN ,Wdt module enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " SOFT_RST ,Wdt software reset, can auto clear, only need to set 1. 1: reset 0: normal operation need to check until it turn to 0 after set it to 1" "0,1"
|
|
group ad:0xF07F0004++0x03
|
|
line.long 0x00 "WDT_WTC,WDT TERMINAL COUNT VALUE"
|
|
hexmask.long 0x00 0.--31. 1. " WTC_VAL ,Wdt terminal count value"
|
|
group ad:0xF07F0008++0x03
|
|
line.long 0x00 "WDT_WRC_CTL,WDT REFRESH CONTROL"
|
|
bitfld.long 0x00 3. " REFR_TRIG ,Refresh trigger, auto clear" "0,1"
|
|
bitfld.long 0x00 2. " SEQ_REFR_EN ,Sequence based WDT refresh enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 1. " MODE1_EN ,Window based refresh, only when programing to refr_trig within a preconfigured time window is treated as validate refresh event. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " MODE0_EN ,Refresh without any conDItion. 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF07F000C++0x03
|
|
line.long 0x00 "WDT_WRC_VAL,WDT REFRESH WINDOW LIMIT"
|
|
hexmask.long 0x00 0.--31. 1. " WIN_LOW_LIMIT ,Window low limit"
|
|
group ad:0xF07F0010++0x03
|
|
line.long 0x00 "WDT_WRC_SEQ,WDT REFRESH SEQUENCE DELTA"
|
|
hexmask.long 0x00 0.--31. 1. " SEQ_DELTA ,Sequence delta"
|
|
group ad:0xF07F0014++0x03
|
|
line.long 0x00 "WDT_RST_CTL,WDT RESET CONTROL"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if INT_RST_EN is 1"
|
|
bitfld.long 0x00 18. " WDT_RST_EN ,internal system reset restart wdt enable" "0,1"
|
|
bitfld.long 0x00 17. " INT_RST_MODE ,internal system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " INT_RST_EN ,internal system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF07F0018++0x03
|
|
line.long 0x00 "WDT_EXT_RST_CTL,WDT EXTERNAL RESET CONTROL"
|
|
bitfld.long 0x00 28. " RST_REQ_POL ,Rst request polarity selection register. Output ext_rst_req_b is low active, if rst_req_pol sets to 0. 0. low active 1. high active" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if EXT_RST_EN is 1"
|
|
bitfld.long 0x00 17. " EXT_RST_MODE ,external system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " EXT_RST_EN ,external system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF07F001C++0x03
|
|
line.long 0x00 "WDT_CNT,WDT COUNTER"
|
|
hexmask.long 0x00 0.--31. 1. " WDT_CNT ,Wdt counter value"
|
|
group ad:0xF07F0020++0x03
|
|
line.long 0x00 "WDT_TSW,WDT TIMESTAMP"
|
|
hexmask.long 0x00 0.--31. 1. " TSW ,timestamp value"
|
|
group ad:0xF07F0024++0x03
|
|
line.long 0x00 "WDT_INT,WDT INTERRUPT"
|
|
bitfld.long 0x00 8. " OVFLOW_INT_CLR ,Wdt timer overflow interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 7. " ILL_SEQ_REFR_INT_CLR ,Illegal sequential refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 6. " ILL_WIN_REFR_INT_CLR ,Illegal counter refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 5. " OVFLOW_INT_STA ,Wdt timer overflow interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "ILL_SEQ_REFR_INT_STA ,Illegal sequential refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 3. " ILL_WIN_REFR_INT_STA ,Illegal counter refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 2. " OVFLOW_INT_EN ,Wdt timer overflow interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " ILL_SEQ_REFR_INT_EN ,Illegal sequential refresh interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ILL_WIN_REFR_INT_EN ,Illegal counter refresh interrupt enable" "0,1"
|
|
group ad:0xF07F0028++0x03
|
|
line.long 0x00 "RST_REQ_MON,WDT RESET REQUEST MONITOR"
|
|
bitfld.long 0x00 3. " EXT_RST_REQ_REC ,external reset request record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 2. " INT_RST_REQ_REC ,internal reset request monitor, record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 1. " EXT_RST_REQ_MON ,external reset request monitor, real time after sync to pclk" "0,1"
|
|
bitfld.long 0x00 0. " INT_RST_REQ_MON ,internal reset request monitor, real time after sync to pclk" "0,1"
|
|
group ad:0xF07F002C++0x03
|
|
line.long 0x00 "DUMMY_RES,DUMMY RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DUMMY ,reserved registers"
|
|
group ad:0xF07F0040++0x03
|
|
line.long 0x00 "WDT_LOCK,WDT LOCK"
|
|
bitfld.long 0x00 6. " CLK_SRC_LOCK ,lock for clk_src in WDT_CTRL register" "0,1"
|
|
bitfld.long 0x00 5. " INT_LOCK ,lock for wtc interrupt registers." "0,1"
|
|
bitfld.long 0x00 4. " EXT_RST_LOCK ,lock for external reset registers." "0,1"
|
|
bitfld.long 0x00 3. " RST_LOCK ,lock for reset registers." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "WRC_LOCK ,lock for refresh registers" "0,1"
|
|
bitfld.long 0x00 1. " WTC_LOCK ,lock for wtc registers." "0,1"
|
|
bitfld.long 0x00 0. " CTL_LOCK ,lock for wtc control registers." "0,1"
|
|
group ad:0xF07F004C++0x03
|
|
line.long 0x00 "WDT_ERR_INJ_EN,WDT ERROR INJECTION ENABLE REGISTER"
|
|
bitfld.long 0x00 2. " OUT_INJ_EN ,wdt output error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_INJ_EN ,IRQ error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " APB_INJ_EN ,APB E2E error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF07F0050++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF07F0054++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF07F0058++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF07F005C++0x03
|
|
line.long 0x00 "WDT_FUSA_INT,WDT FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " SYNC_ERR_CLR ,fusa sync err irq clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,fusa sync irq status" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,fusa sync irq enable" "0,1"
|
|
group ad:0xF07F0060++0x03
|
|
line.long 0x00 "WDT_ERR_INJ,WDT ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 4. " EXT_RST_REQ_INJ ,ext_rst_req_b injection" "0,1"
|
|
bitfld.long 0x00 3. " INT_RST_REQ_INJ ,int_rst_req injection" "0,1"
|
|
bitfld.long 0x00 2. " UNC_IRQ_INJ ,unc irq error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR_IRQ_INJ ,cor irq error injection" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "WDT_IRQ_INJ ,wdt irq error injection" "0,1"
|
|
group ad:0xF07F0070++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
|
|
bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
|
|
group ad:0xF07F0074++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF07F0078++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
tree.end
|
|
tree "WDT3"
|
|
width 27.
|
|
group ad:0xF2100000++0x03
|
|
line.long 0x00 "WDT_CTRL,WDT GLOBAL CONTROL REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " PRE_DIV_NUM ,Wdt pre_en DIvider ration"
|
|
bitfld.long 0x00 10. " WDT_EN_STA ,wdt enable status, need to check after set wdt_en to 1'b1 1: wdt enable done 0: wdt enable not done" "0,1"
|
|
bitfld.long 0x00 9. " SELFTEST_TRIG ,selftest trigger" "0,1"
|
|
bitfld.long 0x00 8. " WDT_EN_SRC ,wdt module enable source select. 1: from register WDT_EN 0: from fuse" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "DBG_HALT_EN ,Wdt halt enable in debug mode. 1: debug halt enable 0: debug halt DIsable" "0,1"
|
|
bitfld.long 0x00 6. " AUTO_RESTART ,Wdt overflow auto restart enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 5. " WTC_SRC ,Wdt terminal count value source. 1: from register WDT_WTC 0: from fuse or soc integration" "0,1"
|
|
bitfld.long 0x00 2.--4. " CLK_SRC ,Wdt clock source select. 3'b000: main clock 3'b001: bus clock 3'b010: ext clock 3'b011: tie off 3'b1xx: lp_clk 32KHz xtal" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 1. "WDT_EN ,Wdt module enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " SOFT_RST ,Wdt software reset, can auto clear, only need to set 1. 1: reset 0: normal operation need to check until it turn to 0 after set it to 1" "0,1"
|
|
group ad:0xF2100004++0x03
|
|
line.long 0x00 "WDT_WTC,WDT TERMINAL COUNT VALUE"
|
|
hexmask.long 0x00 0.--31. 1. " WTC_VAL ,Wdt terminal count value"
|
|
group ad:0xF2100008++0x03
|
|
line.long 0x00 "WDT_WRC_CTL,WDT REFRESH CONTROL"
|
|
bitfld.long 0x00 3. " REFR_TRIG ,Refresh trigger, auto clear" "0,1"
|
|
bitfld.long 0x00 2. " SEQ_REFR_EN ,Sequence based WDT refresh enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 1. " MODE1_EN ,Window based refresh, only when programing to refr_trig within a preconfigured time window is treated as validate refresh event. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " MODE0_EN ,Refresh without any conDItion. 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF210000C++0x03
|
|
line.long 0x00 "WDT_WRC_VAL,WDT REFRESH WINDOW LIMIT"
|
|
hexmask.long 0x00 0.--31. 1. " WIN_LOW_LIMIT ,Window low limit"
|
|
group ad:0xF2100010++0x03
|
|
line.long 0x00 "WDT_WRC_SEQ,WDT REFRESH SEQUENCE DELTA"
|
|
hexmask.long 0x00 0.--31. 1. " SEQ_DELTA ,Sequence delta"
|
|
group ad:0xF2100014++0x03
|
|
line.long 0x00 "WDT_RST_CTL,WDT RESET CONTROL"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if INT_RST_EN is 1"
|
|
bitfld.long 0x00 18. " WDT_RST_EN ,internal system reset restart wdt enable" "0,1"
|
|
bitfld.long 0x00 17. " INT_RST_MODE ,internal system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " INT_RST_EN ,internal system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF2100018++0x03
|
|
line.long 0x00 "WDT_EXT_RST_CTL,WDT EXTERNAL RESET CONTROL"
|
|
bitfld.long 0x00 28. " RST_REQ_POL ,Rst request polarity selection register. Output ext_rst_req_b is low active, if rst_req_pol sets to 0. 0. low active 1. high active" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if EXT_RST_EN is 1"
|
|
bitfld.long 0x00 17. " EXT_RST_MODE ,external system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " EXT_RST_EN ,external system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF210001C++0x03
|
|
line.long 0x00 "WDT_CNT,WDT COUNTER"
|
|
hexmask.long 0x00 0.--31. 1. " WDT_CNT ,Wdt counter value"
|
|
group ad:0xF2100020++0x03
|
|
line.long 0x00 "WDT_TSW,WDT TIMESTAMP"
|
|
hexmask.long 0x00 0.--31. 1. " TSW ,timestamp value"
|
|
group ad:0xF2100024++0x03
|
|
line.long 0x00 "WDT_INT,WDT INTERRUPT"
|
|
bitfld.long 0x00 8. " OVFLOW_INT_CLR ,Wdt timer overflow interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 7. " ILL_SEQ_REFR_INT_CLR ,Illegal sequential refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 6. " ILL_WIN_REFR_INT_CLR ,Illegal counter refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 5. " OVFLOW_INT_STA ,Wdt timer overflow interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "ILL_SEQ_REFR_INT_STA ,Illegal sequential refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 3. " ILL_WIN_REFR_INT_STA ,Illegal counter refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 2. " OVFLOW_INT_EN ,Wdt timer overflow interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " ILL_SEQ_REFR_INT_EN ,Illegal sequential refresh interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ILL_WIN_REFR_INT_EN ,Illegal counter refresh interrupt enable" "0,1"
|
|
group ad:0xF2100028++0x03
|
|
line.long 0x00 "RST_REQ_MON,WDT RESET REQUEST MONITOR"
|
|
bitfld.long 0x00 3. " EXT_RST_REQ_REC ,external reset request record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 2. " INT_RST_REQ_REC ,internal reset request monitor, record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 1. " EXT_RST_REQ_MON ,external reset request monitor, real time after sync to pclk" "0,1"
|
|
bitfld.long 0x00 0. " INT_RST_REQ_MON ,internal reset request monitor, real time after sync to pclk" "0,1"
|
|
group ad:0xF210002C++0x03
|
|
line.long 0x00 "DUMMY_RES,DUMMY RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DUMMY ,reserved registers"
|
|
group ad:0xF2100040++0x03
|
|
line.long 0x00 "WDT_LOCK,WDT LOCK"
|
|
bitfld.long 0x00 6. " CLK_SRC_LOCK ,lock for clk_src in WDT_CTRL register" "0,1"
|
|
bitfld.long 0x00 5. " INT_LOCK ,lock for wtc interrupt registers." "0,1"
|
|
bitfld.long 0x00 4. " EXT_RST_LOCK ,lock for external reset registers." "0,1"
|
|
bitfld.long 0x00 3. " RST_LOCK ,lock for reset registers." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "WRC_LOCK ,lock for refresh registers" "0,1"
|
|
bitfld.long 0x00 1. " WTC_LOCK ,lock for wtc registers." "0,1"
|
|
bitfld.long 0x00 0. " CTL_LOCK ,lock for wtc control registers." "0,1"
|
|
group ad:0xF210004C++0x03
|
|
line.long 0x00 "WDT_ERR_INJ_EN,WDT ERROR INJECTION ENABLE REGISTER"
|
|
bitfld.long 0x00 2. " OUT_INJ_EN ,wdt output error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_INJ_EN ,IRQ error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " APB_INJ_EN ,APB E2E error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF2100050++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF2100054++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF2100058++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF210005C++0x03
|
|
line.long 0x00 "WDT_FUSA_INT,WDT FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " SYNC_ERR_CLR ,fusa sync err irq clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,fusa sync irq status" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,fusa sync irq enable" "0,1"
|
|
group ad:0xF2100060++0x03
|
|
line.long 0x00 "WDT_ERR_INJ,WDT ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 4. " EXT_RST_REQ_INJ ,ext_rst_req_b injection" "0,1"
|
|
bitfld.long 0x00 3. " INT_RST_REQ_INJ ,int_rst_req injection" "0,1"
|
|
bitfld.long 0x00 2. " UNC_IRQ_INJ ,unc irq error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR_IRQ_INJ ,cor irq error injection" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "WDT_IRQ_INJ ,wdt irq error injection" "0,1"
|
|
group ad:0xF2100070++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
|
|
bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
|
|
group ad:0xF2100074++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF2100078++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
tree.end
|
|
tree "WDT4"
|
|
width 27.
|
|
group ad:0xF2110000++0x03
|
|
line.long 0x00 "WDT_CTRL,WDT GLOBAL CONTROL REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " PRE_DIV_NUM ,Wdt pre_en DIvider ration"
|
|
bitfld.long 0x00 10. " WDT_EN_STA ,wdt enable status, need to check after set wdt_en to 1'b1 1: wdt enable done 0: wdt enable not done" "0,1"
|
|
bitfld.long 0x00 9. " SELFTEST_TRIG ,selftest trigger" "0,1"
|
|
bitfld.long 0x00 8. " WDT_EN_SRC ,wdt module enable source select. 1: from register WDT_EN 0: from fuse" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "DBG_HALT_EN ,Wdt halt enable in debug mode. 1: debug halt enable 0: debug halt DIsable" "0,1"
|
|
bitfld.long 0x00 6. " AUTO_RESTART ,Wdt overflow auto restart enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 5. " WTC_SRC ,Wdt terminal count value source. 1: from register WDT_WTC 0: from fuse or soc integration" "0,1"
|
|
bitfld.long 0x00 2.--4. " CLK_SRC ,Wdt clock source select. 3'b000: main clock 3'b001: bus clock 3'b010: ext clock 3'b011: tie off 3'b1xx: lp_clk 32KHz xtal" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 1. "WDT_EN ,Wdt module enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " SOFT_RST ,Wdt software reset, can auto clear, only need to set 1. 1: reset 0: normal operation need to check until it turn to 0 after set it to 1" "0,1"
|
|
group ad:0xF2110004++0x03
|
|
line.long 0x00 "WDT_WTC,WDT TERMINAL COUNT VALUE"
|
|
hexmask.long 0x00 0.--31. 1. " WTC_VAL ,Wdt terminal count value"
|
|
group ad:0xF2110008++0x03
|
|
line.long 0x00 "WDT_WRC_CTL,WDT REFRESH CONTROL"
|
|
bitfld.long 0x00 3. " REFR_TRIG ,Refresh trigger, auto clear" "0,1"
|
|
bitfld.long 0x00 2. " SEQ_REFR_EN ,Sequence based WDT refresh enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 1. " MODE1_EN ,Window based refresh, only when programing to refr_trig within a preconfigured time window is treated as validate refresh event. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " MODE0_EN ,Refresh without any conDItion. 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF211000C++0x03
|
|
line.long 0x00 "WDT_WRC_VAL,WDT REFRESH WINDOW LIMIT"
|
|
hexmask.long 0x00 0.--31. 1. " WIN_LOW_LIMIT ,Window low limit"
|
|
group ad:0xF2110010++0x03
|
|
line.long 0x00 "WDT_WRC_SEQ,WDT REFRESH SEQUENCE DELTA"
|
|
hexmask.long 0x00 0.--31. 1. " SEQ_DELTA ,Sequence delta"
|
|
group ad:0xF2110014++0x03
|
|
line.long 0x00 "WDT_RST_CTL,WDT RESET CONTROL"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if INT_RST_EN is 1"
|
|
bitfld.long 0x00 18. " WDT_RST_EN ,internal system reset restart wdt enable" "0,1"
|
|
bitfld.long 0x00 17. " INT_RST_MODE ,internal system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " INT_RST_EN ,internal system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF2110018++0x03
|
|
line.long 0x00 "WDT_EXT_RST_CTL,WDT EXTERNAL RESET CONTROL"
|
|
bitfld.long 0x00 28. " RST_REQ_POL ,Rst request polarity selection register. Output ext_rst_req_b is low active, if rst_req_pol sets to 0. 0. low active 1. high active" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if EXT_RST_EN is 1"
|
|
bitfld.long 0x00 17. " EXT_RST_MODE ,external system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " EXT_RST_EN ,external system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF211001C++0x03
|
|
line.long 0x00 "WDT_CNT,WDT COUNTER"
|
|
hexmask.long 0x00 0.--31. 1. " WDT_CNT ,Wdt counter value"
|
|
group ad:0xF2110020++0x03
|
|
line.long 0x00 "WDT_TSW,WDT TIMESTAMP"
|
|
hexmask.long 0x00 0.--31. 1. " TSW ,timestamp value"
|
|
group ad:0xF2110024++0x03
|
|
line.long 0x00 "WDT_INT,WDT INTERRUPT"
|
|
bitfld.long 0x00 8. " OVFLOW_INT_CLR ,Wdt timer overflow interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 7. " ILL_SEQ_REFR_INT_CLR ,Illegal sequential refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 6. " ILL_WIN_REFR_INT_CLR ,Illegal counter refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 5. " OVFLOW_INT_STA ,Wdt timer overflow interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "ILL_SEQ_REFR_INT_STA ,Illegal sequential refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 3. " ILL_WIN_REFR_INT_STA ,Illegal counter refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 2. " OVFLOW_INT_EN ,Wdt timer overflow interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " ILL_SEQ_REFR_INT_EN ,Illegal sequential refresh interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ILL_WIN_REFR_INT_EN ,Illegal counter refresh interrupt enable" "0,1"
|
|
group ad:0xF2110028++0x03
|
|
line.long 0x00 "RST_REQ_MON,WDT RESET REQUEST MONITOR"
|
|
bitfld.long 0x00 3. " EXT_RST_REQ_REC ,external reset request record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 2. " INT_RST_REQ_REC ,internal reset request monitor, record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 1. " EXT_RST_REQ_MON ,external reset request monitor, real time after sync to pclk" "0,1"
|
|
bitfld.long 0x00 0. " INT_RST_REQ_MON ,internal reset request monitor, real time after sync to pclk" "0,1"
|
|
group ad:0xF211002C++0x03
|
|
line.long 0x00 "DUMMY_RES,DUMMY RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DUMMY ,reserved registers"
|
|
group ad:0xF2110040++0x03
|
|
line.long 0x00 "WDT_LOCK,WDT LOCK"
|
|
bitfld.long 0x00 6. " CLK_SRC_LOCK ,lock for clk_src in WDT_CTRL register" "0,1"
|
|
bitfld.long 0x00 5. " INT_LOCK ,lock for wtc interrupt registers." "0,1"
|
|
bitfld.long 0x00 4. " EXT_RST_LOCK ,lock for external reset registers." "0,1"
|
|
bitfld.long 0x00 3. " RST_LOCK ,lock for reset registers." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "WRC_LOCK ,lock for refresh registers" "0,1"
|
|
bitfld.long 0x00 1. " WTC_LOCK ,lock for wtc registers." "0,1"
|
|
bitfld.long 0x00 0. " CTL_LOCK ,lock for wtc control registers." "0,1"
|
|
group ad:0xF211004C++0x03
|
|
line.long 0x00 "WDT_ERR_INJ_EN,WDT ERROR INJECTION ENABLE REGISTER"
|
|
bitfld.long 0x00 2. " OUT_INJ_EN ,wdt output error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_INJ_EN ,IRQ error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " APB_INJ_EN ,APB E2E error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF2110050++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF2110054++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF2110058++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF211005C++0x03
|
|
line.long 0x00 "WDT_FUSA_INT,WDT FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " SYNC_ERR_CLR ,fusa sync err irq clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,fusa sync irq status" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,fusa sync irq enable" "0,1"
|
|
group ad:0xF2110060++0x03
|
|
line.long 0x00 "WDT_ERR_INJ,WDT ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 4. " EXT_RST_REQ_INJ ,ext_rst_req_b injection" "0,1"
|
|
bitfld.long 0x00 3. " INT_RST_REQ_INJ ,int_rst_req injection" "0,1"
|
|
bitfld.long 0x00 2. " UNC_IRQ_INJ ,unc irq error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR_IRQ_INJ ,cor irq error injection" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "WDT_IRQ_INJ ,wdt irq error injection" "0,1"
|
|
group ad:0xF2110070++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
|
|
bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
|
|
group ad:0xF2110074++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF2110078++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
tree.end
|
|
tree "WDT5"
|
|
width 27.
|
|
group ad:0xF0BE0000++0x03
|
|
line.long 0x00 "WDT_CTRL,WDT GLOBAL CONTROL REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " PRE_DIV_NUM ,Wdt pre_en DIvider ration"
|
|
bitfld.long 0x00 10. " WDT_EN_STA ,wdt enable status, need to check after set wdt_en to 1'b1 1: wdt enable done 0: wdt enable not done" "0,1"
|
|
bitfld.long 0x00 9. " SELFTEST_TRIG ,selftest trigger" "0,1"
|
|
bitfld.long 0x00 8. " WDT_EN_SRC ,wdt module enable source select. 1: from register WDT_EN 0: from fuse" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "DBG_HALT_EN ,Wdt halt enable in debug mode. 1: debug halt enable 0: debug halt DIsable" "0,1"
|
|
bitfld.long 0x00 6. " AUTO_RESTART ,Wdt overflow auto restart enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 5. " WTC_SRC ,Wdt terminal count value source. 1: from register WDT_WTC 0: from fuse or soc integration" "0,1"
|
|
bitfld.long 0x00 2.--4. " CLK_SRC ,Wdt clock source select. 3'b000: main clock 3'b001: bus clock 3'b010: ext clock 3'b011: tie off 3'b1xx: lp_clk 32KHz xtal" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 1. "WDT_EN ,Wdt module enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " SOFT_RST ,Wdt software reset, can auto clear, only need to set 1. 1: reset 0: normal operation need to check until it turn to 0 after set it to 1" "0,1"
|
|
group ad:0xF0BE0004++0x03
|
|
line.long 0x00 "WDT_WTC,WDT TERMINAL COUNT VALUE"
|
|
hexmask.long 0x00 0.--31. 1. " WTC_VAL ,Wdt terminal count value"
|
|
group ad:0xF0BE0008++0x03
|
|
line.long 0x00 "WDT_WRC_CTL,WDT REFRESH CONTROL"
|
|
bitfld.long 0x00 3. " REFR_TRIG ,Refresh trigger, auto clear" "0,1"
|
|
bitfld.long 0x00 2. " SEQ_REFR_EN ,Sequence based WDT refresh enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 1. " MODE1_EN ,Window based refresh, only when programing to refr_trig within a preconfigured time window is treated as validate refresh event. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " MODE0_EN ,Refresh without any conDItion. 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF0BE000C++0x03
|
|
line.long 0x00 "WDT_WRC_VAL,WDT REFRESH WINDOW LIMIT"
|
|
hexmask.long 0x00 0.--31. 1. " WIN_LOW_LIMIT ,Window low limit"
|
|
group ad:0xF0BE0010++0x03
|
|
line.long 0x00 "WDT_WRC_SEQ,WDT REFRESH SEQUENCE DELTA"
|
|
hexmask.long 0x00 0.--31. 1. " SEQ_DELTA ,Sequence delta"
|
|
group ad:0xF0BE0014++0x03
|
|
line.long 0x00 "WDT_RST_CTL,WDT RESET CONTROL"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if INT_RST_EN is 1"
|
|
bitfld.long 0x00 18. " WDT_RST_EN ,internal system reset restart wdt enable" "0,1"
|
|
bitfld.long 0x00 17. " INT_RST_MODE ,internal system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " INT_RST_EN ,internal system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF0BE0018++0x03
|
|
line.long 0x00 "WDT_EXT_RST_CTL,WDT EXTERNAL RESET CONTROL"
|
|
bitfld.long 0x00 28. " RST_REQ_POL ,Rst request polarity selection register. Output ext_rst_req_b is low active, if rst_req_pol sets to 0. 0. low active 1. high active" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if EXT_RST_EN is 1"
|
|
bitfld.long 0x00 17. " EXT_RST_MODE ,external system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " EXT_RST_EN ,external system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF0BE001C++0x03
|
|
line.long 0x00 "WDT_CNT,WDT COUNTER"
|
|
hexmask.long 0x00 0.--31. 1. " WDT_CNT ,Wdt counter value"
|
|
group ad:0xF0BE0020++0x03
|
|
line.long 0x00 "WDT_TSW,WDT TIMESTAMP"
|
|
hexmask.long 0x00 0.--31. 1. " TSW ,timestamp value"
|
|
group ad:0xF0BE0024++0x03
|
|
line.long 0x00 "WDT_INT,WDT INTERRUPT"
|
|
bitfld.long 0x00 8. " OVFLOW_INT_CLR ,Wdt timer overflow interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 7. " ILL_SEQ_REFR_INT_CLR ,Illegal sequential refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 6. " ILL_WIN_REFR_INT_CLR ,Illegal counter refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 5. " OVFLOW_INT_STA ,Wdt timer overflow interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "ILL_SEQ_REFR_INT_STA ,Illegal sequential refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 3. " ILL_WIN_REFR_INT_STA ,Illegal counter refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 2. " OVFLOW_INT_EN ,Wdt timer overflow interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " ILL_SEQ_REFR_INT_EN ,Illegal sequential refresh interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ILL_WIN_REFR_INT_EN ,Illegal counter refresh interrupt enable" "0,1"
|
|
group ad:0xF0BE0028++0x03
|
|
line.long 0x00 "RST_REQ_MON,WDT RESET REQUEST MONITOR"
|
|
bitfld.long 0x00 3. " EXT_RST_REQ_REC ,external reset request record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 2. " INT_RST_REQ_REC ,internal reset request monitor, record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 1. " EXT_RST_REQ_MON ,external reset request monitor, real time after sync to pclk" "0,1"
|
|
bitfld.long 0x00 0. " INT_RST_REQ_MON ,internal reset request monitor, real time after sync to pclk" "0,1"
|
|
group ad:0xF0BE002C++0x03
|
|
line.long 0x00 "DUMMY_RES,DUMMY RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DUMMY ,reserved registers"
|
|
group ad:0xF0BE0040++0x03
|
|
line.long 0x00 "WDT_LOCK,WDT LOCK"
|
|
bitfld.long 0x00 6. " CLK_SRC_LOCK ,lock for clk_src in WDT_CTRL register" "0,1"
|
|
bitfld.long 0x00 5. " INT_LOCK ,lock for wtc interrupt registers." "0,1"
|
|
bitfld.long 0x00 4. " EXT_RST_LOCK ,lock for external reset registers." "0,1"
|
|
bitfld.long 0x00 3. " RST_LOCK ,lock for reset registers." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "WRC_LOCK ,lock for refresh registers" "0,1"
|
|
bitfld.long 0x00 1. " WTC_LOCK ,lock for wtc registers." "0,1"
|
|
bitfld.long 0x00 0. " CTL_LOCK ,lock for wtc control registers." "0,1"
|
|
group ad:0xF0BE004C++0x03
|
|
line.long 0x00 "WDT_ERR_INJ_EN,WDT ERROR INJECTION ENABLE REGISTER"
|
|
bitfld.long 0x00 2. " OUT_INJ_EN ,wdt output error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_INJ_EN ,IRQ error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " APB_INJ_EN ,APB E2E error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0BE0050++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF0BE0054++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF0BE0058++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF0BE005C++0x03
|
|
line.long 0x00 "WDT_FUSA_INT,WDT FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " SYNC_ERR_CLR ,fusa sync err irq clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,fusa sync irq status" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,fusa sync irq enable" "0,1"
|
|
group ad:0xF0BE0060++0x03
|
|
line.long 0x00 "WDT_ERR_INJ,WDT ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 4. " EXT_RST_REQ_INJ ,ext_rst_req_b injection" "0,1"
|
|
bitfld.long 0x00 3. " INT_RST_REQ_INJ ,int_rst_req injection" "0,1"
|
|
bitfld.long 0x00 2. " UNC_IRQ_INJ ,unc irq error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR_IRQ_INJ ,cor irq error injection" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "WDT_IRQ_INJ ,wdt irq error injection" "0,1"
|
|
group ad:0xF0BE0070++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
|
|
bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
|
|
group ad:0xF0BE0074++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
|
|
group ad:0xF0BE0078++0x03
|
|
line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
|
|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
|
|
tree.end
|
|
tree "WDT6"
|
|
width 27.
|
|
group ad:0xF0BF0000++0x03
|
|
line.long 0x00 "WDT_CTRL,WDT GLOBAL CONTROL REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " PRE_DIV_NUM ,Wdt pre_en DIvider ration"
|
|
bitfld.long 0x00 10. " WDT_EN_STA ,wdt enable status, need to check after set wdt_en to 1'b1 1: wdt enable done 0: wdt enable not done" "0,1"
|
|
bitfld.long 0x00 9. " SELFTEST_TRIG ,selftest trigger" "0,1"
|
|
bitfld.long 0x00 8. " WDT_EN_SRC ,wdt module enable source select. 1: from register WDT_EN 0: from fuse" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. "DBG_HALT_EN ,Wdt halt enable in debug mode. 1: debug halt enable 0: debug halt DIsable" "0,1"
|
|
bitfld.long 0x00 6. " AUTO_RESTART ,Wdt overflow auto restart enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 5. " WTC_SRC ,Wdt terminal count value source. 1: from register WDT_WTC 0: from fuse or soc integration" "0,1"
|
|
bitfld.long 0x00 2.--4. " CLK_SRC ,Wdt clock source select. 3'b000: main clock 3'b001: bus clock 3'b010: ext clock 3'b011: tie off 3'b1xx: lp_clk 32KHz xtal" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 1. "WDT_EN ,Wdt module enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " SOFT_RST ,Wdt software reset, can auto clear, only need to set 1. 1: reset 0: normal operation need to check until it turn to 0 after set it to 1" "0,1"
|
|
group ad:0xF0BF0004++0x03
|
|
line.long 0x00 "WDT_WTC,WDT TERMINAL COUNT VALUE"
|
|
hexmask.long 0x00 0.--31. 1. " WTC_VAL ,Wdt terminal count value"
|
|
group ad:0xF0BF0008++0x03
|
|
line.long 0x00 "WDT_WRC_CTL,WDT REFRESH CONTROL"
|
|
bitfld.long 0x00 3. " REFR_TRIG ,Refresh trigger, auto clear" "0,1"
|
|
bitfld.long 0x00 2. " SEQ_REFR_EN ,Sequence based WDT refresh enable. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 1. " MODE1_EN ,Window based refresh, only when programing to refr_trig within a preconfigured time window is treated as validate refresh event. 1: enable 0: DIsable" "0,1"
|
|
bitfld.long 0x00 0. " MODE0_EN ,Refresh without any conDItion. 1: enable 0: DIsable" "0,1"
|
|
group ad:0xF0BF000C++0x03
|
|
line.long 0x00 "WDT_WRC_VAL,WDT REFRESH WINDOW LIMIT"
|
|
hexmask.long 0x00 0.--31. 1. " WIN_LOW_LIMIT ,Window low limit"
|
|
group ad:0xF0BF0010++0x03
|
|
line.long 0x00 "WDT_WRC_SEQ,WDT REFRESH SEQUENCE DELTA"
|
|
hexmask.long 0x00 0.--31. 1. " SEQ_DELTA ,Sequence delta"
|
|
group ad:0xF0BF0014++0x03
|
|
line.long 0x00 "WDT_RST_CTL,WDT RESET CONTROL"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if INT_RST_EN is 1"
|
|
bitfld.long 0x00 18. " WDT_RST_EN ,internal system reset restart wdt enable" "0,1"
|
|
bitfld.long 0x00 17. " INT_RST_MODE ,internal system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " INT_RST_EN ,internal system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF0BF0018++0x03
|
|
line.long 0x00 "WDT_EXT_RST_CTL,WDT EXTERNAL RESET CONTROL"
|
|
bitfld.long 0x00 28. " RST_REQ_POL ,Rst request polarity selection register. Output ext_rst_req_b is low active, if rst_req_pol sets to 0. 0. low active 1. high active" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. " RST_WIN ,pulse mode reset window this field set to non 0 if EXT_RST_EN is 1"
|
|
bitfld.long 0x00 17. " EXT_RST_MODE ,external system reset request mode. 1. pulse mode 0. level mode" "0,1"
|
|
bitfld.long 0x00 16. " EXT_RST_EN ,external system reset request enable." "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. "RST_CNT ,reset counter, the time between wdt overflow to reset trigger"
|
|
group ad:0xF0BF001C++0x03
|
|
line.long 0x00 "WDT_CNT,WDT COUNTER"
|
|
hexmask.long 0x00 0.--31. 1. " WDT_CNT ,Wdt counter value"
|
|
group ad:0xF0BF0020++0x03
|
|
line.long 0x00 "WDT_TSW,WDT TIMESTAMP"
|
|
hexmask.long 0x00 0.--31. 1. " TSW ,timestamp value"
|
|
group ad:0xF0BF0024++0x03
|
|
line.long 0x00 "WDT_INT,WDT INTERRUPT"
|
|
bitfld.long 0x00 8. " OVFLOW_INT_CLR ,Wdt timer overflow interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 7. " ILL_SEQ_REFR_INT_CLR ,Illegal sequential refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 6. " ILL_WIN_REFR_INT_CLR ,Illegal counter refresh interrupt clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 5. " OVFLOW_INT_STA ,Wdt timer overflow interrupt status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. "ILL_SEQ_REFR_INT_STA ,Illegal sequential refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 3. " ILL_WIN_REFR_INT_STA ,Illegal counter refresh interrupt status" "0,1"
|
|
bitfld.long 0x00 2. " OVFLOW_INT_EN ,Wdt timer overflow interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " ILL_SEQ_REFR_INT_EN ,Illegal sequential refresh interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "ILL_WIN_REFR_INT_EN ,Illegal counter refresh interrupt enable" "0,1"
|
|
group ad:0xF0BF0028++0x03
|
|
line.long 0x00 "RST_REQ_MON,WDT RESET REQUEST MONITOR"
|
|
bitfld.long 0x00 3. " EXT_RST_REQ_REC ,external reset request record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 2. " INT_RST_REQ_REC ,internal reset request monitor, record, write 1 to clear, can only be reset by por reset" "0,1"
|
|
bitfld.long 0x00 1. " EXT_RST_REQ_MON ,external reset request monitor, real time after sync to pclk" "0,1"
|
|
bitfld.long 0x00 0. " INT_RST_REQ_MON ,internal reset request monitor, real time after sync to pclk" "0,1"
|
|
group ad:0xF0BF002C++0x03
|
|
line.long 0x00 "DUMMY_RES,DUMMY RESERVED REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " DUMMY ,reserved registers"
|
|
group ad:0xF0BF0040++0x03
|
|
line.long 0x00 "WDT_LOCK,WDT LOCK"
|
|
bitfld.long 0x00 6. " CLK_SRC_LOCK ,lock for clk_src in WDT_CTRL register" "0,1"
|
|
bitfld.long 0x00 5. " INT_LOCK ,lock for wtc interrupt registers." "0,1"
|
|
bitfld.long 0x00 4. " EXT_RST_LOCK ,lock for external reset registers." "0,1"
|
|
bitfld.long 0x00 3. " RST_LOCK ,lock for reset registers." "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "WRC_LOCK ,lock for refresh registers" "0,1"
|
|
bitfld.long 0x00 1. " WTC_LOCK ,lock for wtc registers." "0,1"
|
|
bitfld.long 0x00 0. " CTL_LOCK ,lock for wtc control registers." "0,1"
|
|
group ad:0xF0BF004C++0x03
|
|
line.long 0x00 "WDT_ERR_INJ_EN,WDT ERROR INJECTION ENABLE REGISTER"
|
|
bitfld.long 0x00 2. " OUT_INJ_EN ,wdt output error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 1. " IRQ_INJ_EN ,IRQ error injection enable 0: DIsable 1: enable" "0,1"
|
|
bitfld.long 0x00 0. " APB_INJ_EN ,APB E2E error injection enable 0: DIsable 1: enable" "0,1"
|
|
group ad:0xF0BF0050++0x03
|
|
line.long 0x00 "WDAT_ERR_INJ,APB WDATA ERROR INJECTION REGISTER"
|
|
hexmask.long 0x00 0.--31. 1. " ERR_INJ ,wdata error injection"
|
|
group ad:0xF0BF0054++0x03
|
|
line.long 0x00 "WECC_ERR_INJ,APB WECC ERROR INJECTION REGISTER"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_INJ ,wecc error injection"
|
|
group ad:0xF0BF0058++0x03
|
|
line.long 0x00 "APB_ERR_INT,APB ERROR INTERRUPT REGISTER"
|
|
bitfld.long 0x00 15. " PADDR_INT_STA ,paddr uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 14. " PUSER_INT_STA ,puser uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 13. " PCTRL1_INT_STA ,pctrl1 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 12. " PCTRL0_INT_STA ,pctrl0 uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. "PWDAT_C_INT_STA ,pwdata correctable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 10. " PWDAT_U_INT_STA ,pwdata uncorrectable error interrupt status write 1 to clear" "0,1"
|
|
bitfld.long 0x00 9. " PWDAT_F_INT_STA ,pwdata fatal error interrupt status. write 1 to clear" "0,1"
|
|
bitfld.long 0x00 7. " PADDR_INT_EN ,paddr uncorrectable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. "PUSER_INT_EN ,puser uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. " PCTRL1_INT_EN ,pctrl1 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. " PCTRL0_INT_EN ,pctrl0 uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. " PWDAT_C_INT_EN ,pwdata correctable error interrupt enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. "PWDAT_U_INT_EN ,pwdata uncorrectable error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. " PWDAT_F_INT_EN ,pwdata fatal error interrupt enable" "0,1"
|
|
group ad:0xF0BF005C++0x03
|
|
line.long 0x00 "WDT_FUSA_INT,WDT FUSA INTERRUPT REGISTER"
|
|
bitfld.long 0x00 16. " SYNC_ERR_CLR ,fusa sync err irq clear. this bit can be auto cleared, you only need set this bit." "0,1"
|
|
bitfld.long 0x00 8. " SYNC_ERR_STA ,fusa sync irq status" "0,1"
|
|
bitfld.long 0x00 0. " SYNC_ERR_EN ,fusa sync irq enable" "0,1"
|
|
group ad:0xF0BF0060++0x03
|
|
line.long 0x00 "WDT_ERR_INJ,WDT ERROR INJECTION REGISTER"
|
|
bitfld.long 0x00 4. " EXT_RST_REQ_INJ ,ext_rst_req_b injection" "0,1"
|
|
bitfld.long 0x00 3. " INT_RST_REQ_INJ ,int_rst_req injection" "0,1"
|
|
bitfld.long 0x00 2. " UNC_IRQ_INJ ,unc irq error injection" "0,1"
|
|
bitfld.long 0x00 1. " COR_IRQ_INJ ,cor irq error injection" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. "WDT_IRQ_INJ ,wdt irq error injection" "0,1"
|
|
group ad:0xF0BF0070++0x03
|
|
line.long 0x00 "PRDATAINJ,APB Read Data (q_prdata) injection"
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bitfld.long 0x00 0. " B0 ,RESERVED" "0,1"
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group ad:0xF0BF0074++0x03
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line.long 0x00 "REG_PARITY_ERR_INT_STAT,Register parity error interrupt status register"
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bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt statu" "0,1"
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group ad:0xF0BF0078++0x03
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line.long 0x00 "REG_PARITY_ERR_INT_SIG_EN,Register parity error interrupt signal enable register"
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|
bitfld.long 0x00 0. " REG_PARITY_ERR ,Register parity error interrupt signal enable" "0,1"
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tree.end
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tree.end
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